Rainer Leupers

🎤 On Air at Digitalisierung bei Bayern Innovativ “Redefining Human Machine Interfaces with Quantum Sensing”. Among multiple distinguished experts in the quantum sensing field, I am pleased to introduce you to Q.ANT GmbH's quantum-based Native Sensing technology. 🤝 Imagine a world, where we humans have intuitive control over artificial machines like prosthetics, robots, or even a computer mouse. The only thing needed is our native biosignals. Computer cursor to the left, roll your eye - open an app - snip with your finger - move the robot to the left - move your arm. This is why we call it #NativeSensing. This is no longer a distant dream—We are inviting innovators to join us on this journey. From January 2025, our first sensor generation will be available to endeavor in this new world. 🌟 Thank you Dr. Andreas Böhm for your well-organized workshop. It is my pleasure to give more details on this technology together with Prof. Dr. Kai Bongs Prof. Dr.-Ing. Roland Nagy, Dr. Dr. Bernd Burchard, @Dr. Sebastian Luber, Dr. Peter Burgholzer, Fleming Bruckmaier. Curious? Learn more and register: https://lnkd.in/e8t8R3PW #QuantumSensing #NativeSensing #HumanMachineInterface #IndustryInnovation

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🚨 RISC-V ecosystem members Andes Technology Corporation and Lauterbach GmbH have teamed up to supercharge the debugging and tracing experience for engineers. As the demand for RISC-V architectures continues to grow across various applications, the combination of Lauterbach’s TRACE32 tools and Andes’ NCETRACE200 trace solution enables developers to gain deep, non-intrusive trace visibility into their System-on-Chip (SoC). This collaboration helps with debugging and tracing, speeding up time-to-market, and enhancing reliability, performance, and efficiency in embedded products. Learn more: https://hubs.ly/Q02-nrgF0

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Updating the MCU-Link and MCU-Link debug probes is now easier and simpler: no need to set a jumper. https://lnkd.in/eQHprqnv

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Dual-core ARM Cortex-A55 SoM starting from $34 https://lnkd.in/eC4M4PUa

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The coolest processor Architecture when I was in University. While Alpha did not survive I think many of the developed technologies continues to live in current architecures like x86, ARM v8/v9 and offcourse RISC V. Anyone actually built a open source Alpha implementation? How close is Alpha and x86S?

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WHO KNEW THIS WAS HAPPENING? This press release triggers so many questions, especially considering the critical role that photonics will play in next generation AI infrastructure. From my experience with Optica meetings, so many important players/countries seem to be absent. What am I missing here? https://lnkd.in/d96FxPCW The (EuroHPC Joint Undertaking (EuroHPC JU))  has just selected seven proposals to establish and operate the first "AI Factories" across Europe. They will be deployed by 2025-2026. The EU says it is one step closer to realising President Ursula von der Leyen's commitment to setting up the first AI Factories. The first AI Factories will represent a €1.5 billion investment, combining national and EU funding. The EU will fund half of this through the Digital Europe Programme for AI infrastructure and Horizon Europe for AIF services. The selected AI Factories will be hosted at leading research and technology hubs across Europe: Barcelona, Spain: “BSC AIF” at the Barcelona Supercomputing Centre Bologna, Italy: “IT4LIA” at CINECA - Bologna Tecnopolo Kajaani, Finland: “LUMI AIF” at CSC Bissen, Luxembourg: “Meluxina-AI” at LuxProvide Linköping, Sweden: “MIMER” at the University of Linköping Stuttgart, Germany: “HammerHAI” at the University of Stuttgart Athens, Greece: “Pharos” at GRNET The seven AI Factories involve 15 Member States and two EuroHPC participating States. Portugal, Romania and Türkiye have joined the BSC AIF; Austria and Slovenia have joined the ITA4LIA; and Czechia, Denmark, Estonia, Norway and Poland have joined the LUMI AIF. Five of the selected hosting sites will deploy new world-class AI-optimised supercomputers in Finland, Germany, Italy, Luxembourg, and Sweden. The AI Factory in Spain will result from the upgrade of the existing EuroHPC system, MareNostrum 5. In Greece, an AI Factory will be established and operated, associated with the DAEDALUS supercomputer, a EuroHPC supercomputer currently under deployment in Greece. The AI Factories in Spain and Finland will also feature an experimental platform, providing a cutting-edge infrastructure for developing and testing innovative AI models and applications and fostering collaboration across Europe. These AI Factories will more than double EuroHPC computing capacity, addressing specific need and boosting the European capabilities in AI.

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CALL THIS WEEK FOR EUROPEAN CHIPS ACT 2.0. WHAT?? I am looking forward to chairing a very topical panel at the Optica GLOBAL PHOTONICS ECONOMIC FORUM in Malaga on Day One (Oct 1st). I will be quizzing the following specialists. Gregg Bartlett, CTO, GlobalFoundries;  Burkhard Slischka, Co-founder & CEO, ALLOS Semiconductors;  Ed Bailey, GM/VP, Jabil;  Martin Schell, Executive Director, Fraunhofer Heinrich Hertz Institute HHI; Torsten Vahrenkamp, CEO, ficonTEC; M. Ashkan Seyedi, Principal, NVIDIA. I expect this week’s story to come up. ESIA Calls for a Chips Act 2.0 The European Semiconductor Industry Association (ESIA), representing major players like NXP Semiconductors, Infineon Technologies, imec, and Fraunhofer, is urging the European Union to fast-track a second phase of its semiconductor strategy through a "Chips Act 2.0." The goal? To keep the region competitive in the fast-moving global race for semiconductor dominance. The original EU Chips Act, which became law in September 2023, seeks to mobilize €43 billion in public and private investment to strengthen Europe’s semiconductor capabilities, targeting 20% of the global market share by 2030. However, in a statement released Monday, ESIA warned that Europe must do more. While acknowledging the significance of the Chips Act as a "fundamental building block," the group emphasized the need to refine the scope, streamline funding processes, and fill existing gaps. Accelerating State Aid for Global Attractiveness One of the critical mechanisms under the Chips Act is providing state aid to attract global semiconductor manufacturers. Yet, delays in approval are hampering progress. For example, Intel’s proposed €30 billion mega-fab in Germany is still awaiting final approval. By contrast, Taiwan’s TSMC received €5 billion in support from the EU for its new chip facility in Dresden, but this came a year after the company’s commitment to invest in the bloc. ESIA advocates for the EU to fast-track these funding approvals to ensure Europe remains an attractive destination for chipmakers. Open Trade and Strategic Cooperation Beyond funding, ESIA calls for a more open trade policy to maintain global partnerships. They argue for a proactive approach to economic security rather than relying on protectionist measures. The Dutch government, under pressure from the US, has now announced further limits on the export of chipmaking machinery to China. The machines in question are ASML's 1970i and 1980i DUV (Deep Ultraviolet) immersion lithography tools. Toward a Coordinated Industrial Strategy Finally, ESIA recommends a coordinated, long-term industrial strategy led by a "Chips Envoy," an official tasked with aligning Europe’s semiconductor (and photonics?) goals across multiple industries. For the photonics industry, staying close to these developments is essential. Curious on the details?: read the attached document. Credit to Ioanna Lykiardopoulou of TNW for spotting this development.

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MODULAR SCALABLE Silicon Photonics GUARANTEED: INSIDE OpenLight WITH Adam Carter. We get many questions from young photonics companies trying to scale up production to serve new markets and increase their turnover. And that’s where Optica can help. We have access to the leading CEOs and CTOs in over 600 photonics businesses who have a wealth of experience and are willing to share their advice with others. NEW INTERVIEW SERIES In this long-form interview series hosted on our YouTube channel, we explore the business strategies being developed by industry leaders. I’m joined at the questioner's table by Michael Hochberg, an authority in the Silicon Photonics industry. https://lnkd.in/d9TPJexs For this edition, we sat down with Dr Adam Carter, the CEO at OpenLight. Formed as a joint venture between Juniper Networks and Synopsys Inc, the company has a proven ability to integrate lasers, optical amplifiers, DFBs, EA-modulators, and photodetectors on a single chip. They grant their customers access to a comprehensive library of photonics components that are heterogeneously integrated on the PASIC. OpenLight’s approach removes the need to source and package separate lasers on silicon photonics chips and improves device performance. In our interview, Adam explains that their approach will be key to producing next-generation, pluggable transceivers for datacenters and AI/ML applications. We discuss their partnership with Optica corporate member Jabil. This move is to meet the needs of the global Silicon Photonics market, which, according to some reports, is expected to grow in value to around US$8.3 billion by 2030. Earlier this year, they also announced strategic partnerships with Optica members like VLC Photonics (Hitachi Group), an end-to-end integrated photonics services firm, now part of the Hitachi group. VLC Photonics now offers design and test services using the OpenLight process design kit (PDK). The collaboration increases the number of designs that OpenLight can support at any one time on the Tower Semiconductor PH18DA process. We also spotted a similar agreement with Optica corporate member Spark Photonics in the US. Who is Adam? Dr Adam Carter has more than 25 years of experience at large and small companies. He is perhaps best known for being chief commercial officer at Foxconn Interconnect Technology (FIT), Cisco, and, earlier, at Oclaro at the time of its acquisition by Lumentum. Originally from the UK, we started by asking Adam to sketch what it was like when the Telecom Bubble burst at the start of this Millennium. I hope you enjoy this conversation. Feedback encouraged.

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The German Federal Ministry for Economic Affairs and Climate Action (BMWK) has announced the formal launch of the European Semiconductor Manufacturing Company (ESMC) chip factory in Dresden, a joint venture between TSMC, Bosch, Infineon, and NXP. With a total investment exceeding €10 billion, the project is supported by up to €5 billion in government funding, making it one of the largest initiatives under the EU Chips Act. TSMC holds a 70% stake with a €3.5 billion contribution, while the other partners each invest €500 million for 10% stakes. This facility, focused on producing semiconductors for automotive and IoT applications, aims to fill a critical gap in Europe's chip industry with planned annual production of nearly 500,000 wafers at full capacity. It is expected to create 2,000 direct jobs and up to 11,000 indirect roles in the semiconductor ecosystem. The project signifies Germany's commitment to advancing microelectronics and reducing dependency on global markets. TSMC Infineon TechnologiesBosch Sensortec GmbHNXP Semiconductors #semiconductor #dresden #germany #chipsact #euchipsact #saxony Silicon Saxony LINK ⬇️

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This paper proposes a #promising #transceiver #architecture relying on #stacked #intelligent #metasurfaces (#SIM). An SIM is constructed by stacking an array of programmable metasurface layers, where each layer consists of a massive number of #low-#cost #passive #meta-#atoms that individually manipulate the #electromagnetic (#EM) waves. By appropriately configuring the passive meta-atoms, an SIM is capable of accomplishing advanced computation and signal processing tasks, such as #multiple-#input #multiple-#output (#MIMO) precoding/combining, multi-user interference mitigation, and radar sensing, as the EM wave propagates through the multiple layers of the metasurface, which effectively reduces both the #RF-#related #energy #consumption and #processing #delay. Inspired by this, the authors provide an overview of the #SIM-#aided #MIMO #transceiver #design, which encompasses its hardware architecture and its potential benefits over state-of-the-art solutions. ----Jiancheng An, Chau Yuen, @Chao Xu, @Hongbin Li, @Derrick Wing Kwan Ng, @Marco Di Renzo, @Mérouane Debbah, @Lajos Hanzo More details can be found at this link: https://lnkd.in/gQcumtwn

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This paper proposes a #promising #transceiver #architecture relying on #stacked #intelligent #metasurfaces (#SIM). An SIM is constructed by stacking an array of programmable metasurface layers, where each layer consists of a massive number of #low-#cost #passive #meta-#atoms that individually manipulate the #electromagnetic (#EM) waves. By appropriately configuring the passive meta-atoms, an SIM is capable of accomplishing advanced computation and signal processing tasks, such as #multiple-#input #multiple-#output (#MIMO) precoding/combining, multi-user interference mitigation, and radar sensing, as the EM wave propagates through the multiple layers of the metasurface, which effectively reduces both the #RF-#related #energy #consumption and #processing #delay. Inspired by this, the authors provide an overview of the #SIM-#aided #MIMO #transceiver #design, which encompasses its hardware architecture and its potential benefits over state-of-the-art solutions. ----Jiancheng An, Chau Yuen, @Chao Xu, @Hongbin Li, @Derrick Wing Kwan Ng, Marco Di Renzo, Merouane Debbah, Lajos Hanzo More details can be found at this link: https://lnkd.in/gQcumtwn

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This paper proposes a #promising #transceiver #architecture relying on #stacked #intelligent #metasurfaces (#SIM). An SIM is constructed by stacking an array of programmable metasurface layers, where each layer consists of a massive number of #low-#cost #passive #meta-#atoms that individually manipulate the #electromagnetic (#EM) waves. By appropriately configuring the passive meta-atoms, an SIM is capable of accomplishing advanced computation and signal processing tasks, such as #multiple-#input #multiple-#output (#MIMO) precoding/combining, multi-user interference mitigation, and radar sensing, as the EM wave propagates through the multiple layers of the metasurface, which effectively reduces both the #RF-#related #energy #consumption and #processing #delay. Inspired by this, the authors provide an overview of the #SIM-#aided #MIMO #transceiver #design, which encompasses its hardware architecture and its potential benefits over state-of-the-art solutions. ----Jiancheng An, Chau Yuen, @Chao Xu, @Hongbin Li, @Derrick Wing Kwan Ng, @Marco Di Renzo, @Merouane Debbah, @Lajos Hanzo More details can be found at this link: https://lnkd.in/gQcumtwn

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This paper proposes a #promising #transceiver #architecture relying on #stacked #intelligent #metasurfaces (#SIM). An SIM is constructed by stacking an array of programmable metasurface layers, where each layer consists of a massive number of #low-#cost #passive #meta-#atoms that individually manipulate the #electromagnetic (#EM) waves. By appropriately configuring the #passive #meta-#atoms, an SIM is capable of accomplishing advanced computation and signal processing tasks, such as #multiple-#input #multiple-#output (#MIMO) precoding/combining, #multi-#user interference mitigation, and radar sensing, as the EM wave propagates through the multiple layers of the metasurface, which effectively reduces both the #RF-#related #energy #consumption and #processing #delay. Inspired by this, the authors provide an overview of the #SIM-#aided #MIMO #transceiver #design, which encompasses its hardware architecture and its potential benefits over state-of-the-art solutions. ----Jiancheng An, Chau Yuen, @Chao Xu, @Hongbin Li, @Derrick Wing Kwan Ng, @Marco Di Renzo, @Merouane Debbah, @Lajos Hanzo More details can be found at this link: https://lnkd.in/gQcumtwn

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Let me be clear 10% yield is not a process. You managed to turn cutting edge expensive wafers into scrap (90%). I have not seen a non-paid and convincing source that shows a path to high yield and better than TSMC features. Also, my pet peeve for so many years. Intel 10nm competed against N7 (TSMC 7nm). That is marketing 101. You are saying that a billion dollar company cannot afford one marketer that understands preception? 18A vs 2nm. We like to laugh about 9.9 vs 9.11 which is bigger (a LLM dataset issue) but we do see that 18 is bigger than 1 right? Keyboard warriors know smaller is better (that sums up their semi knowledge). I repeat (and have posted about it many times, that the nm stuff is pure marketing, it is no longer the gate dimension. You can name your process Super Ultra 1nm if you want to. Or 1nm-- (wink to 14nm++). You need every little helper to market your foundry if you want it to succeed, it is always the sum of all departments involved. That said, I still have major questions. What is your strategic advantage? Should you actively lobby for reunification of Taiwan to temporarily hold an edge? Desperate people take desperate actions. People that follow me know I tend to exaggerate on purpose. Shake the tree, think outside the box (which in this case is still in the box, we are talking 101 stuff). I don't see a Su/Papermaster play here, still betting on the organisation that essentially brought Intel to the edge of the abyss. Don't forget that they offered all technical experts an exit package and many took it. Brain drain. Plus, the people on the inside that talk to other people to get a real feel of the problems, I see them exit as well these days. What is Intel doing to attract the extreme qualified to replace the gap? I rest my case, your honor. https://lnkd.in/duEeh_cQ

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Red Semiconductor has announced the availability of its Versatile Intrinsic Structured Computing (VISC) architecture for RISC-V. VISC is an extension to RISC-V IP that accelerates complex algorithms and adds parallel processing to improve AI operations in edge computing. One of RISC-V's strong value points is the amount of customization possible within the standard. Red Semiconductor has taken advantage of that aspect to develop a licensable high-performance architecture. The VISC instruction set architecture (ISA) adds edge AI, autonomy, and cryptography capabilities to open-source RISC-V. The code is optimized for FPGA and ASIC SoCs. VISC is a vector processing engine built within a RISC-V processor chip. It has its origins in open-source Libre-SOC. Libra-SOC is designed to bring complex algorithms, typically reserved for GPUs, to microcontrollers and small CPU-based devices. Red Semiconductor built VISC upon Libra-SOC and the open-source CPU RISC-V architecture. The result is a CPU core that is compatible with RISC-V and has vector AI processing extensions. Red Semiconductor claims VISC performs higher and with less power than other small system/high computation-need processing devices. It improves performance by using hardware elements to deconstruct algorithms into blocks optimized for parallel processing. The VISC RISC-V processors purportedly deliver up to 100x efficiency in algorithms typically used in AI and machine learning and other highly complex math operations like cryptography and codecs. It relies on a single-issue multi-execute architecture and memory-efficient 64 x 128 deep byte-accessible registers to reduce power consumption. The system breaks algorithms into smaller parts that can be executed in parallel without synchronization issues that often occur in parallel processing. By doing so, large computations can take considerably less time and use less power. If 2023 was the year of cloud-based generative AI, 2024 will be the year of edge AI. This technology requires more power in remote devices, however. Cars, smartphones, medical devices, industrial controls, and other products in the field need to process, interpret, make decisions, and act without taking the time to route data to and from the cloud. VISC gives developers the option to add highly AI-optimized RISC-V to their edge devices while remaining conservative with their power and cost budgets. #RISC_V #VISC

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In the last post I wrote about how the authors of “The RISC-V Reader” posed the BCD (Binary Coded Decimal) operations of the x86 as a mistake of the past. I countered this supposition and argued that it is a useful feature for certain applications. But I didn't want to leave the reader with the impression that I thought that there were no features that I would regard as design mistakes. That is certainly not the case. The 8051 was an early design by Intel and was copied by many other manufacturers. It has features that are truly design mistakes that should never have happened. It is an architecture which should have been left to die an early death but was perpetuated by hardware people who are deficient in their software capabilities. One of its design mistakes is its upward-growing stack. What this does is to reverse the order of the bytes so that they don't appear like they should in memory. They are useless as local variables. Advanced programming languages like C heavily use variables stored in the stack for active temporary storage. But because of the deficiency of the 8051's stack-relative address modes, it is a moot point. It is akin to a blind person finding himself without binoculars when they would be useful for identifying birds for example. The Motorola HC08 has a downward-growing stack and it has good stack relative addressing modes. But even this architecture has a minor design mistake. It uses post-decrement instead of pre-decrement for pushes and pre-increment instead of post-increment for pulls. This flaw was corrected in the HC12. But Motorola decided to keep the flaw in the HC08 to maintain software compatibility. All-in-all, the HC08 is still far superior to the 8051. The x86 got it right when it comes to push and pull stack operations. Intel just used the wrong key word for "pull". RISC-V doesn't have built-in push and pull operations. It is a raw primitive architecture like IBM's mainframes. #Intel8051 #ISA #assembly #programming #computers #microcontrollers

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This letter proposes a scalable channel estimation and reflection optimization framework for #reconfigurable #intelligent #surface (#RIS)-enhanced #orthogonal #frequency #division #multiplexing (#OFDM) systems. Specifically, the proposed scheme firstly generates a training set of RIS reflection coefficient vectors offline. For each RIS reflection coefficient vector in the training set, the proposed scheme estimates only the end-to-end composite channel and then performs the transmit power allocation. As a result, the RIS reflection optimization is simplified by searching for the optimal reflection coefficient vector maximizing the achievable rate from the pre-designed training set. The proposed scheme is capable of flexibly adjusting the training overhead according to the given channel coherence time, which is in sharp contrast to the conventional counterparts. Moreover, the authors discuss the computational complexity of the proposed scheme and analyze the theoretical scaling law of the achievable rate versus the number of training slots. ---- Jiancheng An, Qingqing Wu, Chau Yuen More details can be found at this link: https://lnkd.in/eK6dgdST

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EMC emissions due to the clock line. It has been a long time since I wrote anything about how to fix EMC DIY. This article explains how you can fix narrowband emissions caused by clock lines. I hope you will like it. https://lnkd.in/eYbVgwTS #emc

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