ARM PROCESSOR

MODES
TEAM 28
DHIVYAA 2023105520
RITHANYAA
2023105523
What Are Processor Modes?

•Definition: The different operating environments a processor creates for itself.

•Key Role: They control how the processor manages system memory and running
tasks.

•The Need: Modern processors are highly capable and require multiple modes to
handle
multitasking, security, and complex exceptions, unlike older CPUs.

•Security & Control: Modes enforce a level of privilege to prevent user programs
from interfering with the kernel or hardware.
 ARM Modes
•User mode
•System mode
•Supervisor mode (SVC)
•FIQ mode (Fast Interrupt Request)
•IRQ mode (Interrupt Request)
•Abort mode
•Undefined mode
 Mode Identifier
Mode Privilege Level Primary Function
(Mnemonic)
Standard application
User Unprivileged usr
execution

Privileged OS tasks (uses

System Privileged sys
User registers)

Protected mode for the

Supervisor Privileged svc
Operating System (OS)

Handling high-priority
FIQ Privileged fiq
interrupts (Fast Interrupt)

Handling general-
IRQ Privileged purpose/low-priority irq
interrupts

Handles memory access

Abort Privileged violations (data/prefetch abt
failures)

Entered when an invalid

Undefined Privileged und
instruction is executed
 USER MODE VS SYSTEM MODE
Feature User Mode (usr) System Mode (sys)
Unprivileged Privileged
Privilege
Cannot change mode Can access files (except
Access freely; restricted system kernel) and modify mode
resources bits in CPSR
Uses the same register
Register Set Uses the base set (R0-R15)
set as User Mode
No banked registers
No SPSR; registers are not (unique among privileged
Banking
banked modes)

Only from another

Entry Default execution state privileged mode by
changing CPSR mode bits
Supervisor Mode (SVC)
•Role: The protected mode exclusively for the Operating
System (OS)
•Entry Points:
[Link] Reset (core starts here)
[Link] a Software Interrupt (SWI) instruction.
•Kernel Access: Being privileged, it can access, update, and
modify kernel files
(e.g., "rooting" devices to install a new OS)
•Register Banking: R13 , R14 and the CPSR are banked (a new
set is switched in)
Interrupts: FIQ vs. IRQ
Both are privileged modes that use banked registers (R13, R14, and CPSR/SPSR) to handle external requests.

FIQ (Fast Interrupt

Feature IRQ (Interrupt Request)
Request)
Priority Higher priority Lower priority
Reserved for hardware
General-purpose interrupt
requiring faster response
Purpose/Use handling (e.g., keyboard,
times (e.g., high-speed
screen sync).
DMA transfers).
Provides a larger number
of banked registers (R8 to Only R13, R14, and CPSR
Register Banking
R14) for faster context registers are banked.
save/restore.
Automatically masked out
Disables IRQ while active
Masking when the core is servicing
(to prevent disruption).
a FIQ.
Exception Modes: Abort and Undefined
These modes handle errors that stop the normal program flow.

Feature Abort Mode (abt) Undefined Mode (und)

Execution of an invalid
Failed attempt to access
Trigger or undefined
memory.
instruction.
Memory access violation
Instruction decoding
Type (Data Abort or Prefetch
failure.
Abort).
A warning/error mode An error mode that
Status
that stalls processing. stalls processing.
Allows for software
Indicates a critical fault
emulation of the invalid
Handling that must be resolved
instruction (e.g.,
before proceeding.
coprocessors).
Summary: The Role of Multiple Modes
•Efficiency: Banked registers allow the processor to switch context faster
during
interrupts and exceptions, minimizing overhead.
•Reliability: System mode (ARMv4+) provides a way for exception handlers to be
re-entrant
by safely dealing with the link register (R14) corruption that plagued older
designs..
•Security: Privileged modes (SVC, IRQ, FIQ, Abort, Undefined, System) enforce a
hierarchy of control,
ensuring critical OS and exception tasks are protected from user applications..
THANKYOU