Pipelining and 8086 Architecture (week 4)
CS222
Computer Organization and Assembly Language
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Pipeline Hazards
Types of Pipeline Hazards
[Link] Hazards – Occur when an instruction depends on the result of
a previous instruction.
[Link] Hazards – Occur due to branch instructions.
[Link] instruction fetch like jmp
[Link]: Branch prediction, delayed branching.
[Link] Hazards – Occur when multiple instructions compete for
the same hardware resource.
[Link]: Memory access conflicts.
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Data Hazards
• Data hazards occur when an instruction's execution depends on the
results of some previous instruction that is still being processed in the
pipeline. Consider the example below.
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Contd…
..
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Data Hazards classification
• Data hazards are classified into three categories based
on the order of READ or WRITE operation on the register
and as follows:
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RAW
(Read
after
Write)
[Flow/Tru
e data
depende • This is a case where an instruction uses data
produced by a previous one. Example
ncy]
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WAR
(Write
after
Read)
[Anti-
Data
depende • This is a case where the second instruction writes
onto register before the first instruction reads.
ncy] This is rare in a simple pipeline structure.
However, in some machines with complex and
special instructions case, WAR can happen.
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WAW
(Write
after
Write)
[Output
data
depende • This is a case where two parallel instructions write the
same register and must do it in the order in which they
ncy]
were issued.
• WAW and WAR hazards can only occur when instructions
are executed in parallel or out of order.
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Structural Hazards
Structural hazards arise due to hardware resource conflict amongst the
instructions in the pipeline. A resource here could be the Memory, a
Register in ALU. This resource conflict is said to occur when more than
one instruction in the pipe is requiring access to the same resource in
the same clock cycle. This is a situation that the hardware cannot
handle all possible combinations in an overlapped pipelined execution.
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Contd…
..
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Control Hazards
Control hazards are called Branch hazards and caused by Branch Instructions. Branch
instructions control the flow of program/ instructions execution. Recall that we use
conditional statements in the higher-level language either for iterative loops or with
conditions checking (correlate with for, while, if, case statements). These are transformed
into one of the variants of BRANCH instructions.
Thus a Conditional hazard occurs when the decision to execute an instruction is based on
the result of another instruction like a conditional branch, which checks the condition’s
resultant value.
• The branch and jump instructions decide the program flow by loading the appropriate
location in the Program Counter(PC). The PC has the value of the next instruction
to be fetched and executed by CPU. Consider the following sequence of instructions.
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Hazard Solutions
• Forwarding: Bypassing data between pipeline stages.
• Stalling: Pausing pipeline execution until dependencies resolve.
• Branch Prediction: Guessing branch outcomes to minimize control
hazards.
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Outline for this week
Extending ia32 to ia64
Microprocessor architecture
RISC vs CISC
8086 hardware structure
Components of Control Unit (CU)
Pipelining in 8086 architecture
Internal Registers (General Purpose, Index and Pointers, Segment and
Flag register)
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CPU
• Brain of Computer; controls all operations
• Uses Memory Circuits to store information
• Uses I/O Circuits to communicate with I/O Devices
• Executes programs stored in memory
• System programs
• Application programs
• Instruction Set: Instructions performed by CPU
• Two main components:
• Execution Unit (EU)
• Bus Interface Unit (BIU)
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Intel 8086
Microproc
essor
Organizat
ion
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Execution Unit (EU)
• Purpose: Execute instructions
• Contains ALU (Arithmetic & Logic Unit)
• To perform arithmetic (+, -, x,/) and logic (AND, OR, NOT)
operations.
• The data for the operations are stored in circuits called Registers.
• A register is like a memory location except that it is referred by a name
not a number (address).
• EU uses registers for:
• Storing data.
• Holding operands for ALU
• To reflect result of a computation – FLAG register
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Bus Interface Unit (BIU)
Facilitates communication Responsible for transmitting
between the EU and the memory address, data and control signals
or I/O circuits. on the buses.
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Internal Bus
• The EU and BIU are connected by an internal bus and they work
together.
• While EU is executing, the BIU fetches up to six bytes of the next
instruction and places them in the instruction queue.
• Instruction Pre-fetch
• Purpose: Speed up the processor
• If the EU needs to communicate with memory or the peripherals, the
BIU suspends instruction pre-fetch and performs the needed
operations.
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Registers
• Registers are high-speed storage locations inside the microprocessor.
• Designed to be accessed at much higher speed than conventional
memory.
• Registers are classified according to the functions they perform.
• General Types of Registers:
• Data Registers: To hold data for an operation.
• Address Registers: To hold the address of an instruction or data.
• Status/Flag Register: keeps the current status of the processor or
result of an arithmetic operation.
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8086 Internal registers 16 bits (2 bytes
each)
AX, BX, CX and DX are two
bytes wide and each byte can
be accessed separately
These registers are used as
memory pointers.
6 status; 3 control ; 7 unused
Segment registers are used
as base address for a segment
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General Purpose/Data Registers
• Following four registers are available to the programmer for general
data manipulation:
• AX (Accumulator): Used in arithmetic, logic and data transfer
instructions. Also required in multiplication, division and input/output
operations.
• BX (Base): It can hold a memory address that points to a variable.
• CX (Counter): Act as a counter for repeating or looping instructions.
These instructions automatically repeat and decrement CX and quit
when equals to 0.
• DX (Data): It has a special role in multiply and divide operations. Also
used in input/output operations.
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Pointers and Index Registers
• These can be accessed only as 16 bit registers.
• IP - instruction pointer: Always points to next instruction to be executed. IP register
always works together with CS segment register and it points to currently executing
instruction.
• SI - source index register: Can be used for pointer addressing of data. Offset address
relative to DS
• DI - destination index register: Can be used for pointer addressing of data . Offset
address relative to ES
• SI and DI used in string movement instructions.
• SP and BP are used to access data inside the stack segment
• BP - base pointer: Primarily used to access parameters passed via the stack. Offset
address relative to SS
• SP – stack pointer: Always points to top item on the stack. Offset address relative to
SS
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Segment Registers
• Store addresses of instruction and data in memory.
• These values are used by the processor to access memory locations.
• CS (Code): Defines the starting address of the section of memory
holding code.
• DS (Data): Defines the section of memory that holds most of the data
used by programs.
• ES (Extra): This is an additional data segment that is used by some of
the string instructions.
• SS (Stack): It defines the area of the memory used for stack
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32-bit Registers
• The 80386/80486 processor contain 32-bit registers which greatly
improve the efficiency of program that take advantage of them.
• EAX, EBX, ECX, EDX,
• EFLAGS
• EIP
• EBP, ESP, ESI, EDI.
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• 64-Bit Operation Modes
• Compatibility mode – can run existing 16-bit and 32-bit
applications (Windows supports only 32-bit apps in this
mode)
• 64-bit mode – Windows 64 uses this
• Basic Execution Environment
• addresses can be 64 bits (48 bits, in practice)
• 16 64-bit general purpose registers
• 64-bit instruction pointer named RIP
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64-bit General Purpose
Registers
• 32-bit general purpose registers:
• EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D, R9D, R10D, R11D,
R12D, R13D, R14D, R15D
• CS,DS,ES,SS,FS,GS
• 64-bit general purpose registers:
• RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9, R10, R11, R12, R13,
R14, R15
• CS,DS,ES,SS,FS,GS
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