POSSESION OF MOBILES INEXAM IS UFM PRACTICE.

Name Enrollment No.

Jaypee Institute of Information Technology, Noida
T2 Exanmination, ODD Semester 2024
[Link] / Integrated [Link] III Semester
Course Title: DigitalCircuit Design Maximum Time: 1Hr
Course Code: 18B11EC215 Maximum Marks :20
CO1 Remember conversion of
various number systems and binary codes.
CO2 Understand Boolean Algebra and its minimization techniques. Understand fundamentals of programmable logic
devices and digital logic families.
CO3 Applying basic concepts of Boolean Algebra to construct combinational and sequential logic circuits. Applying
timer IC to classify wave shaping circuits.
CO4 Analysis of sequential circuits using Flip Flops. Develop skills to analyze Finite State Machines using logic circuits.
COS Design Finite State Machines using concepts of combinational and sequential circuit.
Note: All questions are compulsory.
Qla) Realize a full subtractor using 4:1 multiplexers only.
b) Calculate minimum number of 4:1multiplexers required to implement 256:1 multiplexer.
[CO3(Applying), 3+2]

Q2 a) Realize 1-bit magnitude comparator using 2:4 decoder and OR gates only.
b) A3-bit binary parallel adder is implemented using 2-input Ex-OR, AND and OR gates,
whose propagation delays are 15ns, 10ns and 10ns respectively. Find propagation delays of
final CARRY and SUM of final stage of 3-bit adder. Assume that inputs are available and
stable at time t-0 sec. [CO3(Applying), 2+3]

Q3. Design adder cum subtractor circuit using.4-bit binary parallel adder and logic gates. Also
perform the operation (1001)2-(0111)2 using the designed circuit. [CO3(Applying), 3]

Q4. For the given characteristics table of AB Flip-Flop with inputs A and B
A B Q(t+1)
0 0 Q0)
--
Q)
a)Find the excitation table of ABFlip-Flop.
b) Realize the AB Flip-Flop using T Flip -Flop. (CO3(Applying), 4]

Q5. What is the difference between a Latch and Flip-Flop. Discuss the working of Master-slave JK
Flip Flop along with the circuit diagram. (COJ(Applying), 3]
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POSSESION OF MOBILES IN EXAM IS UFM PRACTICE

Name Enrollment No.
Jaypee Institute of Information Technology, Noida
Make-Up Examination, 2024
[Link] / Integrated [Link], IIISemester
Course Title: Digital Circuit IDesign
Course Code: 18B11EC215
Maximum Time: 1Hr
Maximum Marks: 20
CO1 Rememtber conversion of various number systems and binary codes.
CO2 Understand Boolean Algebra and its minimization techniques. Understand fundamentals of programmable logic devices and
digital logic families.
CO3 Applying basic concepts of Boolean Algebra to construct combinational and sequential logic circuits. Applying timer [C to
classify wave shaping circuits.
C04
COS
Analysis ofsequential circuits using Flip Flops. Develop skills to analyzeFinite State Machines using logic circuits.
Design Finite StateMachines using concepts of combinational and sequential circuit.

Note: All questionsare compulsory.

Q1. a) Apcrson on Saturn has property worth (1,00,000)1s, He has three daughters and two sons. He wants to
distribute half the money equally to his sons and remaining half to his daughters equally. How much will
his each son and cach daughter get in Indian currency?
b) An Indian started on an expedition to Saturn with rupees 1,00,000. The expenditure on Saturn will be in
the ratio of [Link] for food, clothing and travelling. How much will he be spending on food and clothing in
the currency of Saturn? (Assume (10)10-(A)18, (11)-(B)8, (12)16-(C)h8, (13)-(D)1s, (14)10-(E)6,
(15)0-(F)ik. (16)h6-(G)s, (17)-(H)8) [CO1 (Remembering), 2+2 Marks]

Q2. Simplify the following Boolean function using K-map in SOP and POS forms:
F(A, B, C, D, E) = )m(0,1,2,4,7,8,12,14,15,16,17,18,20,24,28,30,31) (C02 (Understanding), 4Marks]

Q3. Design a combinationalcircuit with minimum hardware to detect the Decimal numbers 0, 1, 4, 6, 7, and 8
in a 4-bit Excess-3 code input. [CO3(Applying), 5Marks]

Q4. Design a 4-bit by 3-bit Binary multiplier circuit using 4-bit binary parallel adder and logic gates. Also
perform the operation (1011, X(101) using the designed circuit. [CO3 (Applying), 5 Marks]

The following
Q5. 11011001 serial data are applied to the Flip Flop shown in Fig. 1: J, - 10110110 K,=10010110 J, =
K,=11011011. Determine the resulting serial data that appears on the Qoutput, after each clock
pulse. Assume that, Q is initially 0 and the rightmost bits are applied first.

[CO3 (Applying), 2 Marks]

 POSSESION OF MOBILES IN EXAM IS UFM PRACTICE
Name Enrollment No.
Jaypee Institute of Information Technology, Noida
End-Semester Examination, 2024
[Link]/lntegrated [Link], IIISemester
Course Title: Digital Circuit Design Maximum Time: 2 Hrs
Course Code: 18B11EC215 Maximum Marks: 35

CO1 Remember conversion of various number systems and binary codes.

C02 Understand Boolean algebra and its minimization techniques. Understand fundamentals of
programmable logic devices and digital logic families.
COS Applying basic concepts of Boolean algebra to construct combinational and sequential logic circuits.
Applying time IC to classify wave-shaping circuits.
CO4 Analysis of sequential circuits using Flip Flops. Develop skills to analyze Finite State Machines using
logic circuits.
COS Design Finite State Machincs using concepts of combinational and sequential circuit.

Note: All the questions are compulsory.

Q1. Perform the following operations:
(a) Add (7F)\6 and (BA)16.
(b) Subtract (75)8 from (26)8.
(c) Convert (247.36)s to equivalent hexadecimal number.
(d) Convert Gray number 10110010 to binary number.
[Co1 (Remembering), 1+1+1+1 Marks]
Q2. (a) Design a 2-bit magnitude comparator using ROM.
(b) Implement the following functions using PLA:
F;(A,B, C) = AB + AC + F(A,B, C) = AB + B
[CO2(Understanding), 3+2 Marks]
Q3. (a) Implement F(A, B, C, D) = ABC + Dusing CMOS logic.
(6) Draw standard 2-input NOR gate using Resistor Transistor Logic (RTL).
(c) Given VOH =5V, VoL= 0.1V, VH -1.5V, Vn= 0.7V, loH- 360uA, Io =164A ,IH= 40uA, and In =
1.6uA for a logic implementation. Determine noise margin (NM; and NM) and Fan-out.
C02 (Understanding), 2+1+2 Marks]
Q4. (a) Implement the function F(a, b,c) = ab + bc using a4:1 MUX.
(b) Implement SR-Flip Flop using D-Flip Flop. Show the design steps.
CO3 (Applying), 2+3 Marks]
Q5. (a) Design a synchronous Mod-6 Gray code counter using T-Flip Flop. Show the design steps.
(b) A4-bit shift register shown in Fig. 1, which shifts 1-bit to the right at every clock pulse is initialized to
value 1010 for (Q0Q1 Qa Q3). Show the contents of shift register after every clock pulse (CP), till 4clock pulses
have been applied. (Show the contents after CP1, CP2, CP3, and CP4).

Fig. 1
(c) Calculate the resistance values (RA and Rp) of ICS55 bascd astable multivibrator for gencraling 10 kHz.
signal having 60% duty cycle. Assumecapacitancc C= 0.01 uF.
CO3(Applying), 4+2+2 Marks]
Q6. Analyse thecircuit given in Fig. 2 and
(a) Determine state cquations and output equations.
(b) Draw the state table.
(c) Draw the state diagram.
C04 (Analysing), 2+1+2 Marks

(output)

Fig. 2

Q7. (2) Draw the state diagram of a Mealy FSM which can detect the overlapping sequence '101".
(b) Illustrate the differences between Mealy and Moore FSM.
COS (Evaluating), 2+1 Marks]
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