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cn

Laboratory 2 : 2024.11.21 - 2024.12.12

《电 路 原 理》 实 验 报 告

1 Pre-Lab

1.1 Voltage-Voltage Characteristics of Inverting Amplifier

The output voltage Vout as a function of input voltage Vin is shown in Fig.1, where VT is the threshold voltage of
teh MOSFET.

alloutNDS VaD 4ㄒ
Vs VaDCUT
Yout EVs Van
Eus
n houtt.sn
Ins
V InsIDs K Nas VDVDs.li
11s kzEMas.lk2 7 Ups
Vs RLIDS
Vin Vas

灤
线
讋 牲
区 城 KNas
VTND YDSEVs
RLID VoutzY KRNas
l.li
Figure 1: Voltage-Voltage Characteristics of Inverting Amplifier

For easy reference, we summarize the formula as:



 VS , VGS ∈ [0, VT ) (Cut-Off Region)



 KR
 L 2
VS − 2 (VGS − VT ) , VGS ∈ [VT , V0 ) (Saturation Region)
Vout = 1−σ (1)

 VGS − VT + , VGS ∈ [V0 , V0 + ∆V ) (Transition Region)

 KRL

 VS

 , VGS ∈ [V0 + ∆V, Vmax ] (Linear Region)
KRL (VGS − VT )
Where V0 is the second solution VGS,2 of equations:

VGS = VS − KRL (VGS − VT )2 √
2 2KRL VS + 1 + KRL VT − 1
=⇒ V0 = (2)
V = V KRL
GD T

And σ is the discriminant of the quadratic equation:

√
σ = K 2 RL VGS + 2KRL (1 − KRL VT ) VGS + [K 2 RL
2 2
VT − 2KRL (VT + VS ) + 1]
2 2
(3)

When the input voltage Vin (VGS ) > V0 is large enough, i.e. Vin ⩾ V0 + ∆V , an approximation can be made:
VS
IDS ≈ K (VGS − VT ) VDS =⇒ Vout = (4)
KRL (VGS − VT )

1.2 Small Voltage Gain of Inverting Amplifier

We have alread driven the small signal voltage gain during the last homework. Assuming the small AC input
voltage is uin , and MOS is biased into saturation region, it follows that:
uout
A= = −gm RL = −K (VGS − VT ) RL (5)
uin

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1.3 RC Transient Process

By the three-element method, we can obtain:
R2 V I ( ) R 1 R2
1 − e− τ ,
t
Vout = τ = (R1 ∥ R2 ) C = C (6)
R1 + R2 R 1 + R2

1.4 Transient Time

R2 VI
Given VT in the range [0, VS ] (VS = R1 +R2
the time where Vout reaches VT is:
),
( )
VS R1 R2 R2 VI
∆t = τ ln , τ= C, VS = (7)
VS − VT R1 + R2 R1 + R2

2 In-Lab

2.1 Static Input-Output Relationship of Inverting Amplifier

2.1.1 Measure In-Out Voltage Relationship

Construct the circuit in Fig.2, then we can obtain the voltage relationship shown in Fig.3.

Figure 2: Measure In-Out Voltage Relationship

Figure 3: Operational Characteristics of Inverting Amplifier

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2.1.2 The Threshold of The MOSFET

With VS = 5.0185 V, RL = 1 KΩ (998 Ω) and the data obtained in the last section, we can get the threshold
voltage of the MOSFET:

VT = 1.85 V, V0 = 2.3934 V, ∆V = 0.2066 V (8)

2.1.3 Tables of Input-Output Voltage

Table 1: Input-Output Voltage Relationship

Output (V) 5 4 3 2 1 0.0116

Input (V) 0.2765 2.1767 2.2686 2.3238 2.3712 4.9599

2.2 Small Signal Voltage Gain

2.2.1 Voltage Gain of Inverting Amplifier

dVDS
With the data measured in section 2.1.1, we can derived the voltage gain Av = dVGS
via matrix difference (see
Fig.4).

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Figure 4: Small Signal Voltage Gain of Inverting Amplifier

Since transconductance satisfies A = −gm RL , we can also get the transconductance by dividing the limiting
resistance RL = 1 KΩ (998 Ω).
Construct the circuit to measure the voltage gain where the output voltage is 2 V and the sine wave has 50 mV
amplitude (from -50 mV to + 50 mV). The measured result and the data in Fig.4 is:
−1.0056 V
(Av )meas = = −20.1120, (Av )fig = −20.1513 (9)
50 mV
As we can see, almost no deviation.

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2.2.2 Clipping Distortion

Set the amplitude of sine wave to 50 mV ([−50 mV, +50 mV]), the lower and upper bias limits are (see Fig.5
and Fig.6):
Vbias,min = 2.00 V, Vbias,max = 2.39 V (10)

Figure 5: The Lower Limit of The Input Bias Voltage

Figure 6: The Upper Limit of The Input Bias Voltage

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2.3 The Delay of Inverting Amplifier as a Digital Inverter

2.3.1 Measure The Gate to Source Capacitance of Inverting Amplifier

Use a 500 KΩ resistor and a 30 KΩ resistor to measure the gate to source capacitance CGS of the MOSFET,
respectively. The measured results are:
dVout V0
RL = 500 KΩ, lim+ = 57070.3 V · s−1 , Vsteady = 3.3198 V =⇒ C = = 116.3407 pF (11)
t→0 dt RL k 0+
dVout V0
RL = 30.0 KΩ, lim+ = 948889.8 V · s−1 , Vsteady = 4.9032 V =⇒ C = = 172.2434 pF (12)
t→0 dt RL k 0+

Figure 7: Gate to Source Capacitance of 2N7000, RL = 500 KΩ

Figure 8: Gate to Source Capacitance of 2N7000, RL = 30 KΩ

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It is puzzling that C = with RL = 500 KΩ. Actually, with the resistance RL = 500 KΩ, the steady voltage
V0 is limited to 3.3198 V (see Fig.7), which is not the expected value. Why is it like that? Because the oscilloscope
input resistance is not large enough. We keep this to the Post-Lab,

(a) The Gate to Source Capacitance of Inverting Amplifier (b) The Delay of Inverting Amplifier as a Digital Inverter

Figure 9: In-Lab 3.1 and In-Lab 3.2

2.3.2 Measure The Delay of Inverting Amplifier

With RL,1 = 30 KΩ and RL,2 = 1 KΩ, construct the circuit in Fig.9 (b), obtain the delay time of the inverting
amplifier as a digital inverter (see Fig.10 and Fig.11).

start to fall: ∆t1 = 1.504 µs, reach low: ∆t2 = 3.799 µs (13)

Figure 10: The Output Voltage Starts to Fall

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Figure 11: The Output Voltage Reaches to Low

It is interesting that resonance phenomena occurs, see Fig.12 and Fig.13.

Figure 12: Input Voltage (Yellow) and Output Voltage (Blue) of The First MOS

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Figure 13: Input Voltage (Yellow) and Output Voltage (Blue) of The Second MOS

3 Post-Lab

3.1 Voltage-Voltage Characteristics Comparison

3.1.1 Transconductance Sensitivity K

Use the voltage-voltage characteristics data in section 2.1.1 to calculate the transconductance sensitivity K of
the MOSFET: 
IDS = K (VGS − VT )2 2 (VS − VDS )
2
=⇒ K = (14)
V = V − I R RL (VGS − VT )
2
DS S DS L

Where VT = 1.85 V, RL = 1 KΩ (998 Ω) and VS = 5.0185 V. Plot the curve K = K(VGS ), as shown in Fig.14 (a):

0.06
4

0.05 3.5

3
0.04
2.5
0.03 2

0.02
1.5

1
0.01
0.5

0
1.9 2 2.1 2.2 2.3 2.4 1.9 2 2.1 2.2 2.3 2.4

(a) Transconductance Sensitivity K as a Function of VGS (b) Drain to Source Current as a Function of VGS

Figure 14: Transconductance Sensitivity

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As we can see, K is not a ideal constant value. So we try fitting IDS as a function of VDS , and the result is shown
in Fig.14 (b), R2 = 0.9511.
K
K = 0.02572 A · V−2 ,
2
IDS = (VGS − VT ) , VT = 1.85 V (15)
2
3
It is funny that the fitting result is exllecent if we use IDS = K
2
(VGS − VT ) , which has a high R2 = 0.9977.

3.1.2 Comparison of Operational Characteristics

With the four parameters VT = 1.85 V, K = 0.02572 A · V−2 , VS = 5 V and RL = 1 KΩ (998 Ω), we can
compute and plot the theoretical operational characteristics of the inverting amplifier, as shown in Fig.15. Below are
the other parameters for our theoretical model:
√
2KRL VS + 1 + KRL VT − 1
V0 = = 2.4376 V, ∆V = 1.5 (V0 − VT ) = 0.8814V (16)
KRL

4.5

3.5

2.5

1.5

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Figure 15: Operational Characteristics Comparison

3.2 Small Signal Voltage Gain

The voltage gain Av measured during In-Lab 2-2 (section 2.2.1), by the operational characteristics obtained in
In-Lab 2-1 (section 2.1.1) and the theoretical module from Pre-Lab are respectively (at Output VGS = 2 V):

Table 2: Voltage Gain at Output 2 V by Different Methods

By Experimental Measurement By Operational Characteristics By Theoretical Op Characteristics

-20.1120 -20.1513 -12.1670

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3.3 Capacitance and Delay Analysis

3.3.1 Total Input Capacitance

In Fig.7, we have seen that the output voltage drops to 3.3198 V, when RL = 500 KΩ and VS = 5 V. It follows
that:
Rosci RL
Vout = VS =⇒ Rosci = = 987.9 KΩ ≈ 1MΩ (17)
Rosci + RL VS
−1
Vout

Assuming Vsource = 5 V, we can obtain the total input capacitance, including GS capacitance CGS and oscilloscope
input capacitance Cosci :



Vsteady
 k 0+ =
 τ
VS
Vsteady = Rosci
· Vsource =⇒ CGS + Cosci = = 175.2225 pF (18)

 Rosci +RL k 0+ RL

τ = (R
osci ∥ RL ) (CGS + Cosci )

If oscilloscope input capacitance Cosci is about 15 pF, then we have CGS ≈ 160 pF.

3.3.2 The Delay Used as a Digital Inverter

Let CGS ≈ 160 pF, VT = 1.85 V, V0 + ∆V = 3.22 V VI = 5 V, yielding:

 ( )

 ∆t = τ ln VS
− V

 VS T

R1 R2 =⇒ start to fall: ∆t1 = 0.1287µs, reach low: ∆t2 = 1.3040µs (19)

 τ = R1 +R2 C


 V = R2 · V
S R1 +R2 I

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