ALU

Muhammed Adel Ahmed

 Project description

About The Project:

It is required to design the ALU shown in Fig.1. This ALU can
execute arithmetic and logical operations. The operation of the
ALU is described by table 1. The output (arithmetic or logical) is
selected by the MSB of the selection line, while the required
operation is selected by the other 3 bits. It is also required to
design flip-flops at the inputs and outputs of the ALU.
 2. Verilog Code
ALU Code:

1- signed arithmetic and unsigned logic:

𝑚𝑜𝑑𝑢𝑙𝑒 𝑎𝑙𝑢(
𝑖𝑛𝑝𝑢𝑡 [3: 0] 𝐴, // 4 − 𝑏𝑖𝑡 𝑖𝑛𝑝𝑢𝑡 𝑜𝑝𝑒𝑟𝑎𝑛𝑑 𝐴
𝑖𝑛𝑝𝑢𝑡 [3: 0] 𝐵, // 4 − 𝑏𝑖𝑡 𝑖𝑛𝑝𝑢𝑡 𝑜𝑝𝑒𝑟𝑎𝑛𝑑 𝐵
𝑖𝑛𝑝𝑢𝑡 [3: 0] 𝑆𝑒𝑙, // 4 − 𝑏𝑖𝑡 𝑠𝑒𝑙𝑒𝑐𝑡𝑖𝑜𝑛 𝑠𝑖𝑔𝑛𝑎𝑙 (𝑆𝑒𝑙[3] 𝑑𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑒𝑠 𝑎𝑟𝑖𝑡ℎ𝑚𝑒𝑡𝑖𝑐 𝑜𝑟 𝑙𝑜𝑔𝑖𝑐𝑎𝑙 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛𝑠)
𝑜𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑔 [5: 0] 𝑌 // 6
− 𝑏𝑖𝑡 𝑜𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑠𝑢𝑙𝑡 (𝑟𝑒𝑠𝑢𝑙𝑡 𝑤𝑖𝑑𝑡ℎ 𝑎𝑙𝑙𝑜𝑤𝑠 𝑓𝑜𝑟 𝑒𝑥𝑡𝑒𝑛𝑑𝑒𝑑 𝑟𝑎𝑛𝑔𝑒 𝑓𝑜𝑟 𝑎𝑟𝑖𝑡ℎ𝑚𝑒𝑡𝑖𝑐 𝑎𝑛𝑑 𝑙𝑜𝑔𝑖𝑐𝑎𝑙 𝑟𝑒𝑠𝑢𝑙𝑡𝑠)
);

𝑎𝑙𝑤𝑎𝑦𝑠 @(∗) 𝑏𝑒𝑔𝑖𝑛

// 𝐶ℎ𝑒𝑐𝑘 𝑡ℎ𝑒 𝑚𝑜𝑠𝑡 𝑠𝑖𝑔𝑛𝑖𝑓𝑖𝑐𝑎𝑛𝑡 𝑏𝑖𝑡 𝑜𝑓 𝑆𝑒𝑙 (𝑆𝑒𝑙[3])
// 𝐼𝑓 𝑆𝑒𝑙[3] 𝑖𝑠 0, 𝑝𝑒𝑟𝑓𝑜𝑟𝑚 𝑎𝑟𝑖𝑡ℎ𝑚𝑒𝑡𝑖𝑐 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛𝑠
𝑖𝑓 (! 𝑆𝑒𝑙[3]) 𝑏𝑒𝑔𝑖𝑛
// 𝑈𝑠𝑒 𝑡ℎ𝑒 𝑙𝑜𝑤𝑒𝑟 𝑡ℎ𝑟𝑒𝑒 𝑏𝑖𝑡𝑠 𝑜𝑓 𝑆𝑒𝑙 𝑡𝑜 𝑐ℎ𝑜𝑜𝑠𝑒 𝑡ℎ𝑒 𝑎𝑟𝑖𝑡ℎ𝑚𝑒𝑡𝑖𝑐 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛
𝑐𝑎𝑠𝑒({𝑆𝑒𝑙[2], 𝑆𝑒𝑙[1], 𝑆𝑒𝑙[0]})
3′𝑏000 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) + 4′𝑏0001; // 𝐼𝑛𝑐𝑟𝑒𝑚𝑒𝑛𝑡 𝐴 𝑏𝑦 1
3′𝑏001 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) − 4′𝑏0001; // 𝐷𝑒𝑐𝑟𝑒𝑚𝑒𝑛𝑡 𝐴 𝑏𝑦 1
3′𝑏010 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) << 2; // 𝑆ℎ𝑖𝑓𝑡 𝐴 𝑙𝑒𝑓𝑡 𝑏𝑦 2 (𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑦 𝐴 𝑏𝑦 4)
3′𝑏011 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵) + 4′𝑏0001; // 𝐼𝑛𝑐𝑟𝑒𝑚𝑒𝑛𝑡 𝐵 𝑏𝑦 1
3′𝑏100 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵) − 4′𝑏0001; // 𝐷𝑒𝑐𝑟𝑒𝑚𝑒𝑛𝑡 𝐵 𝑏𝑦 1
3′𝑏101 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵) << 2; // 𝑆ℎ𝑖𝑓𝑡 𝐵 𝑙𝑒𝑓𝑡 𝑏𝑦 2 (𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑦 𝐵 𝑏𝑦 4)
3′𝑏110 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) + $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵);// 𝐴𝑑𝑑 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏111 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) << 4; // 𝑆ℎ𝑖𝑓𝑡 𝐴 𝑙𝑒𝑓𝑡 𝑏𝑦 4 (𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑦 𝐴 𝑏𝑦 16)
𝑒𝑛𝑑𝑐𝑎𝑠𝑒
𝑒𝑛𝑑
// 𝐼𝑓 𝑆𝑒𝑙[3] 𝑖𝑠 1, 𝑝𝑒𝑟𝑓𝑜𝑟𝑚 𝑙𝑜𝑔𝑖𝑐𝑎𝑙 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛𝑠
𝑒𝑙𝑠𝑒 𝑏𝑒𝑔𝑖𝑛
// 𝑈𝑠𝑒 𝑡ℎ𝑒 𝑙𝑜𝑤𝑒𝑟 𝑡ℎ𝑟𝑒𝑒 𝑏𝑖𝑡𝑠 𝑜𝑓 𝑆𝑒𝑙 𝑡𝑜 𝑐ℎ𝑜𝑜𝑠𝑒 𝑡ℎ𝑒 𝑙𝑜𝑔𝑖𝑐𝑎𝑙 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛
𝑐𝑎𝑠𝑒({𝑆𝑒𝑙[2], 𝑆𝑒𝑙[1], 𝑆𝑒𝑙[0]})
3′𝑏000 ∶ 𝑌 <= ~$𝑠𝑖𝑔𝑛𝑒𝑑(𝐴); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑁𝑂𝑇 𝑜𝑓 𝐴
3′𝑏001 ∶ 𝑌 <= ~$𝑠𝑖𝑔𝑛𝑒𝑑(𝐵); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑁𝑂𝑇 𝑜𝑓 𝐵
3′𝑏010 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) & $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝐴𝑁𝐷 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏011 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) | $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑂𝑅 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏100 ∶ 𝑌 <= $𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) ^ $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑋𝑂𝑅 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏101 ∶ 𝑌 <= ~($𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) ^ $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵)); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑋𝑁𝑂𝑅 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏110 ∶ 𝑌 <= ~($𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) & $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵)); // 𝐵𝑖𝑡𝑤𝑖𝑠𝑒 𝑁𝐴𝑁𝐷 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵
3′𝑏111 ∶ 𝑌 <= ~($𝑠𝑖𝑔𝑛𝑒𝑑(𝐴) + $𝑠𝑖𝑔𝑛𝑒𝑑(𝐵)); // 𝑁𝑒𝑔𝑎𝑡𝑒𝑑 𝑠𝑢𝑚 𝑜𝑓 𝐴 𝑎𝑛𝑑 𝐵 (𝑡𝑤𝑜′𝑠 𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡)
𝑒𝑛𝑑𝑐𝑎𝑠𝑒
𝑒𝑛𝑑
𝑒𝑛𝑑
𝑒𝑛𝑑𝑚𝑜𝑑𝑢𝑙𝑒

2-signed arithmetic and signed logic (Bonus):

module alu_2(
input signed [3:0] A, // 4-bit input operand A
input signed [3:0] B, // 4-bit input operand B
input signed [3:0] Sel, // 4-bit selection signal (Sel[3] determines arithmetic or logical operations)
output reg [5:0] Y // 6-bit output result (result width allows for extended range for arithmetic and logical
results)
);
always @(*) begin
// Check the most significant bit of Sel (Sel[3])
// If Sel[3] is 0, perform arithmetic operations
if (!Sel[3]) begin
// Use the lower three bits of Sel to choose the arithmetic operation
case({Sel[2], Sel[1], Sel[0]})
3'b000 : Y <= A + 4'b0001; // Increment A by 1
3'b001 : Y <= A - 4'b0001; // Decrement A by 1
3'b010 : Y <= A << 2; // Shift A left by 2 (multiply A by 4)
3'b011 : Y <= B + 4'b0001; // Increment B by 1
3'b100 : Y <= B - 4'b0001; // Decrement B by 1
3'b101 : Y <= B << 2; // Shift B left by 2 (multiply B by 4)
3'b110 : Y <= A + B;// Add A and B
3'b111 : Y <= A << 4; // Shift A left by 4 (multiply A by 16)
endcase
end
// If Sel[3] is 1, perform logical operations
else begin
// Use the lower three bits of Sel to choose the logical operation
case({Sel[2], Sel[1], Sel[0]})
3'b000 : Y <= ~(A); // Bitwise NOT of A
3'b001 : Y <= ~(B); // Bitwise NOT of B
3'b010 : Y <= (A & B); // Bitwise AND of A and B
3'b011 : Y <= (A | B); // Bitwise OR of A and B
3'b100 : Y <= (A ^ B); // Bitwise XOR of A and B
 3'b101 : Y <= ~(A ^ B); // Bitwise XNOR of A and B
3'b110 : Y <= ~(A & B); // Bitwise NAND of A and B
3'b111 : Y <= ~(A + B); // Negated sum of A and B (two's complement)
endcase
end
end
endmodule
 3. Test Bench Code
Test Bench Code:

module alu_tb2;

// Testbench signals
reg [3:0] A; // 4-bit test input operand A
reg [3:0] B; // 4-bit test input operand B
reg [3:0] Sel; // 4-bit test input selection signal
wire [5:0] Y; // 6-bit test output result (wire)

// Instantiate the ALU module

alu uut (
.A(A),
.B(B),
.Sel(Sel),
.Y(Y)
);
integer i;
initial begin
// Display header
$display("Time\tA\tB\tSel\t\tY");

// Initialize inputs
A = 4'b0000;
B = 4'b0000;
Sel = 4'b0000;

// Apply test cases

for(i = 1; i <= 30; i = i + 1) begin
$display("Test Case %d", i);
A = $random % 16; // Limit to 4-bit values (0-15)
B = $random % 16; // Limit to 4-bit values (0-15)
Sel = $random % 16; // Limit to 4-bit values (0-15)
#10;
$display("%0t\t%b\t%b\t%b\t", $time, A, B, Sel, Y);
end

// Stop simulation
$stop;
end
endmodule
module alu_tb;
// Testbench signals
reg [3:0] A; // 4-bit test input operand A reg [3:0] B; // 4-bit test input operand B
reg [3:0] Sel; // 4-bit test input selection signal wire [5:0] Y; // 6-bit test output result (wire)
// Instantiate the ALU module
alu uut ( .A(A),.B(B),.Sel(Sel),.Y(Y) );
initial begin
// Display header
$display("Time\tA\tB\tSel\t\tY (Actual)\tY (Expected)");

// Apply test vectors for Arithmetic Operations (Sel[3] = 0)

A = 4'b0010; B = 4'b0001; Sel = 4'b0000;
#10;
if(Y == 6'b000011)
$display("Test Case 1 Passed"); else $display("Test Case 1 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000011); // A + 1

A = 4'b0010; B = 4'b0001; Sel = 4'b0001;

#10;
if(Y == 6'b000001)
$display("Test Case 2 Passed"); else $display("Test Case 2 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000001); // A - 1

A = 4'b0010; B = 4'b0001; Sel = 4'b0010;

#10;
if(Y == 6'b001000)
$display("Test Case 3 Passed"); else $display("Test Case 3 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b001000); // A << 2

A = 4'b0010; B = 4'b0001; Sel = 4'b0011; #10;

if(Y == 6'b000010)
$display("Test Case 4 Passed"); else $display("Test Case 4 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000010); // B + 1

A = 4'b0010; B = 4'b0001; Sel = 4'b0100;#10;

if(Y == 6'b000000)
$display("Test Case 5 Passed"); else $display("Test Case 5 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000000); // B - 1

A = 4'b0010; B = 4'b0001; Sel = 4'b0101;#10;

if(Y == 6'b000010)
$display("Test Case 6 Passed"); else $display("Test Case 6 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000100); // B << 1

A = 4'b0010; B = 4'b0011; Sel = 4'b0110; #10;

if(Y == 6'b000101)
$display("Test Case 7 Passed"); else $display("Test Case 7 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000101); // A + B

A = 4'b0010; B = 4'b0001; Sel = 4'b0111; #10;

if(Y == 6'b001000)
$display("Test Case 8 Passed"); else $display("Test Case 8 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b001000); // A << 4

else
$display("Test Case 11 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000010); // A AND B

A = 4'b0010; B = 4'b0011; Sel = 4'b1011;

// Apply test vectors for Logical Operations (Sel[3] = 1)
A = 4'b0010; B = 4'b0001; Sel = 4'b1000; #10;
if(Y == 6'b111101)
$display("Test Case 9 Passed"); else $display("Test Case 9 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b111101); // NOT A

A = 4'b0010; B = 4'b0001; Sel = 4'b1001; #10;

if(Y == 6'b111110)
$display("Test Case 10 Passed"); else $display("Test Case 10 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b111110); // NOT B

A = 4'b0010; B = 4'b0011; Sel = 4'b1010; #10;

if(Y == 6'b000010)
$display("Test Case 11 Passed"); else $display("Test Case 11 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000010); // A AND B

A = 4'b0010; B = 4'b0011; Sel = 4'b1011;

#10;
if(Y == 6'b000011)
$display("Test Case 12 Passed");
else
$display("Test Case 12 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000011); // A OR B

A = 4'b0010; B = 4'b0011; Sel = 4'b1100;

#10;
if(Y == 6'b000001)
$display("Test Case 13 Passed");
else
$display("Test Case 13 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b000001); // A XOR B

A = 4'b0010; B = 4'b0011; Sel = 4'b1101;

#10;
if(Y == 6'b111110)
$display("Test Case 14 Passed");
else
$display("Test Case 14 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b111110); // A XNOR B

A = 4'b0010; B = 4'b0011; Sel = 4'b1110;

#10;
if(Y == 6'b111101)
$display("Test Case 15 Passed");
else
$display("Test Case 15 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b111101); // NAND A and B

A = 4'b0010; B = 4'b0011; Sel = 4'b1111;

#10;
if(Y == 6'b111010)
$display("Test Case 16 Passed");
else
$display("Test Case 16 Failed");
$display("%0t\t%b\t%b\t%b\t\t%b\t\t%b", $time, A, B, Sel, Y, 6'b111010); // Nor A and B
$stop;
end
endmodule
2- different test cases for different inputs:
 4. Cadence schematics
• In this section, we undertake the individual design of the ALU's
schematics for each component and strive to optimize them.

• Our initial step involves designing the essential gates, serving as

the primary level of abstraction.

• We will provide a scheme and a symbol for each component

used in the design

4.1 Inverter Schematic

Defining the Wp and Wn values is a crucial aspect of the reference
inverter, and it is advantageous to assume Wp : Wn = (2:1).
According to Cadence guidelines, the minimum width available in
this technology corresponds to a width of 120nm, considering the
minimum length. Therefore, we will assign Wn as 120nm and set Wp
as 2 times Wn. Defining FP (number of fingers for pmos), FN
(number of fingers for nmos), to switch the best value of them to
choose the minimum propagation delay.
 4.1 Inverter Symbol

4.1 Inverter Testbench

Initially defining the Fp and Fn values:
 𝑻𝒑𝒅 = 𝟓. 𝟖𝟎 𝒑𝒔

Try to increase the widths by increase the number of fingers of each:

So:
𝑻𝒑𝒅 = 𝟓. 𝟓𝟑 𝒑𝒔
4.2 NAND Schematic
• Initially, we determine the gate size based on the reference
inverter, considering the worst-case scenario. 𝑊𝑛 = 2𝑊𝑛𝑟𝑒𝑓 =
320𝑛m 𝑊𝑝 = 𝑊𝑝𝑟𝑒𝑓 = 320𝑛m

4.2 NAND Symbol

 NAND Testbench

Initially

So: 𝑻𝒑𝒅 = 𝟗. 𝟔𝟖𝟑 𝒑𝒔

So: 𝑻𝒑𝒅 = 𝟗. 𝟏𝟕 𝒑𝒔
4.3 NOR Schematic

• Initially, we determine the gate size based on the reference

inverter while taking the worst-case scenario into account.

4.3 NOR Symbol

 4.1 NOR Testbench

So: 𝑻𝒑𝒅 = 𝟏𝟐 𝒑𝒔

So: 𝑻𝒑𝒅 = 𝟗. 𝟗𝟏 𝒑𝒔
 XOR Schematic

• To achieve the optimal implementation of the XOR functionality in

terms of delay time, we utilized Transmission Gate Logic (TGL) for
the XOR gate.

4.4
4.5
4.6 XOR Symbol

4.1
4.2
4.3
4.4
4.5
4.6
4.7

XOR Testbench
4.8 XNOR Schematic

• To ensure the most optimal implementation of the XNOR

functionality in terms of delay time, we employed Transmission
Gate Logic (TGL) for the XNOR gate.

4.2 XNOR Symbol

 4.3 AND Schematic
• By utilizing the NAND and NOR gates we have implemented, we can
easily obtain the AND and OR functionality by incorporating an
inverter after each respective gate. Additionally, the buffer
functionality is achieved by employing a sequence of two inverters.

4.9 AND Symbol

 4.1 AND Testbench

So: 𝑻𝒑𝒅 = 𝟏𝟒. 𝟔𝟖 𝒑𝒔

4.2 OR Schematic

4.4 OR Symbol
4.1 OR Testbench

So: 𝑻𝒑𝒅 = 𝟏𝟖. 𝟏 𝒑𝒔

4.5 Buffer Schematic

4.2 Buffer Symbol

 Buffer Testbench

So: 𝑻𝒑𝒅 = 𝟏𝟑. 𝟕𝟒 𝒑𝒔

 4.1 MUX 2x1 Schematic

• To enable the selection of various options, it is necessary to design

a multiplexer (MUX) with different configurations such as 2x1, 4x1,
or 8x1. To accomplish this, we begin by designing the fundamental
building block, which is the 2x1 MUX.
• (TG Multiplexer) is the most efficient one
• The truth table corresponding to the 2x1 MUX is as follow
MUX 2x1 Symbol

MUX 2x1 Testbench

 4.2 MUX 4x1 Schematic

• Having established the foundational building block, we can now

proceed to design larger multiplexers (MUXs) with expanded input
options. By utilizing the 2x1 MUX as a building block, we can
construct MUXs of various sizes, such as 4x1, 8x1, and beyond, to
cater to our specific needs and requirements.

4.6 MUX 4x1 Symbol

4.1 MUX 4x1 Testbench
4.2 MUX 8x1 Schematic

4.3 MUX 8x1 Symbol

MUX 8x1 Testbench
Flip Flops Schematic
4.3 Full Adder Schematic

4.4 Full Adder Symbol

4.5 Logic Unit Schematic

• With all the essential components and building blocks at our

disposal, we can proceed to construct the complete Arithmetic
Logic Unit (ALU), which comprises two primary blocks: the Logic
Unit and the Arithmetic Unit. Our initial focus will be on building
the Logic Unit.

4.4 Logic Unit Symbol

4.1 Logic Unit Testbench
Testcase: 𝑉𝑎 = 0110, 𝑉𝑏 = 1010, 𝑆 = 111, 𝑅𝑒𝑠𝑢𝑙𝑡 = 0001

Testcase: 𝑉𝑎 = 1001, 𝑉𝑏 = 0101, 𝑆 = 100, 𝑅𝑒𝑠𝑢𝑙𝑡 = 1100

Testcase: 𝑉𝑎 = 0110, 𝑉𝑏 = 1010, 𝑆 = 001, 𝑅𝑒𝑠𝑢𝑙𝑡 = 0101

Testcase: 𝑉𝑎 = 1001, 𝑉𝑏 = 0101, 𝑆 = 010, 𝑅𝑒𝑠𝑢𝑙𝑡 = 1110

Testcase: 𝑉𝑎 = 0100, 𝑉𝑏 = 1001, 𝑆 = 111, 𝑅𝑒𝑠𝑢𝑙𝑡 = 0010

Testcase: 𝑉𝑎 = 1011, 𝑉𝑏 = 0110, 𝑆 = 011, 𝑅𝑒𝑠𝑢𝑙𝑡 = 1111

Testcase: 𝑉𝑎 = 1011, 𝑉𝑏 = 0110, 𝑆 = 001, 𝑅𝑒𝑠𝑢𝑙𝑡 = 1001

Testcase: 𝑉𝑎 = 0100, 𝑉𝑏 = 1001, 𝑆 = 100, 𝑅𝑒𝑠𝑢𝑙𝑡 = 1101

 2-bit Binary Shifter Schematic
A binary left shift is used to multiply a binary number by two. It consists of shifting all the binary digits to the
left by 1 digit and adding an extra digit at the end with a value of 0.

Input D is used to decide whether a left shift (D=1) or a right shift (D=0) is applied.
 2-bit Binary Shifter Test

4x Binary Shifter
 4.2 Arithmetic Unit Schematic

• To design the Arithmetic Unit, we incorporate full adders and place

two 8x1 multiplexers (MUX) before each full adder. The purpose of
these multiplexers is to select the appropriate operation based on
our three selectors. It is important to note that the first full adder
requires three MUXs, while the subsequent full adders utilize two
MUXs each. This selection mechanism allows us to choose the
desired operation within the Arithmetic Unit based on the given
selectors.

Arithmetic Unit Symbol

 Arithmetic Unit Test

Testcase: 𝑉𝑎 = 1110, 𝑉𝑏 = 1101, 𝑆 = 000, 𝑅𝑒𝑠𝑢𝑙𝑡 = 001111

Testcase: 𝑉𝑎 = 0001, 𝑉𝑏 = 0010, 𝑆 = 001, 𝑅𝑒𝑠𝑢𝑙𝑡 = 010000

 Testcase: 𝑉𝑎 = 1110, 𝑉𝑏 = 0010, 𝑆 = 010, 𝑅𝑒𝑠𝑢𝑙𝑡 = 011100

Testcase: 𝑉𝑎 = 0001, 𝑉𝑏 = 0010, 𝑆 = 111, 𝑅𝑒𝑠𝑢𝑙𝑡 = 000100

Testcase: 𝑉𝑎 = 1110, 𝑉𝑏 = 1101, 𝑆 = 100, 𝑅𝑒𝑠𝑢𝑙𝑡 = 011100

Testcase: 𝑉𝑎 = 0001, 𝑉𝑏 = 0010, 𝑆 = 101, 𝑅𝑒𝑠𝑢𝑙𝑡 = 000100

5. ALU Design

5.1 ALU Schematic

• To incorporate both logical and arithmetic operations within the ALU, an

additional selector line, S3, is required. S3 serves as the most significant
bit of the selectors and distinguishes between the two types of
operations. If S3 = 1, the operation is a logical one, while if S3 = 0, it is an
arithmetic operation.

• Furthermore, it is important to note that the output of the logic unit

consists of 4 bits, whereas the output of the arithmetic unit is 6 bits. To
ensure consistency in output length, the last two bits of the logic unit
output is set to always be zero (grounded). This adjustment allows for
uniformity in the bit length of the ALU's output.
ALU Symbol