PY32F003 Datasheet

32-bit ARM® Cortex®-M0+ Microcontroller

Puya Semiconductor (Shanghai) Co., Ltd

 PY32F003 Series

32-bit ARM ® Cortex ® -M0+ Microcontroller

Features
 Core  Timer

— 32-bit ARM® Cortex® - M0+ CPU — A 16bit advanced control timer (TIM1)

— Up to 32 MHz operating frequency — 4 general purpose 16-bit timers

 Memories (TIM3/TIM14/TIM16/TIM17)

— Maximum 64 Kbytes of flash memory — A low-power timer (LPTIM), supports wake-

— Up to 8 Kbytes SRAM up from Stop mode

— An Independent Watchdog Timer (IWDT)

 Clock system

— Internal 4/8/16/ 22.12/24 MHz RC Oscillator — A Window Watchdog Timer (WWDT)

(HSI) — A SysTick timer
— Internal 32.768 kHz RC oscillator (LSI)
— A IRTIM
— 4 to 32 MHz crystal oscillator (HSE)
 RTC
 Power management and reset
 Communication Interface
— Operating voltage(x6 version): 1.7 ~ 5.5 V
— A Serial Peripheral Interface (SPI)
— Operating voltage(x7 version): 2.0 ~ 5.5 V
— Two Universal Synchronous / Asynchronous
— Low power modes: Sleep and Stop
Transceivers (USARTs) with automatic bau-
— Power-on/Power-down reset (POR/PDR) drate detection
— Brownout Detect Reset (BOR) — A I2C interface , supports standard mode (100
— Programmable Voltage Detection (PVD) kHz) , Fast mode (400 kHz) , supports 7-bit ad-

 General purpose input and output (I/O) dressing mode

— Up to 18 I/Os, all available as external inter-  Hardware CRC-32 module

rupts  Two comparators

— Driver current 8mA  Unique UID

 3-channel DMA controller  Serial wire debug (SWD)

 1 x 12-bit ADC  Operating temp. (x6 version): -40 ~ 85 ℃

— Supports up to 10 external input channels
 Operating temp. (x7 version): -40 ~ 105 ℃
— Input voltage conversion range: 0 ~ VCC
 Package: TSSOP20,QFN20,SOP20,SOP16,
MSOP10,SOP8, DFN8(3*2)
 PY32F003 Datasheet

Contents
Features ....................................................................................................................................................... 2
1. Introduction .......................................................................................................................................... 5
2. Functional overview .......................................................................................................................... 13
2.1. Arm®Cortex®-M0+ core .............................................................................................................. 13
2.2. Memories ..................................................................................................................................... 13
2.3. Boot mode .................................................................................................................................... 13
2.4. Clock System ............................................................................................................................... 14
2.5. Power management ..................................................................................................................... 15
2.5.1. Power block diagram ............................................................................................................ 15
2.5.2. Power monitoring.................................................................................................................. 15
2.5.3. Voltage regulator .................................................................................................................. 17
2.5.4. Low power mode .................................................................................................................. 17
2.6. Reset ............................................................................................................................................ 17
2.6.1. Power reset .......................................................................................................................... 17
2.6.2. System reset......................................................................................................................... 18
2.7. General-purpose input and output (GPIOs) ................................................................................. 18
2.8. DMA ............................................................................................................................................. 18
2.9. Interrupt ........................................................................................................................................ 18
2.9.1. Interrupt controller NVIC ....................................................................................................... 18
2.9.2. Extended interrupt/event controller (EXTI) ........................................................................... 19
2.10. Analog to digital converter (ADC) ............................................................................................ 19
2.11. Comparators (COMP) .............................................................................................................. 20
2.12. Timer ........................................................................................................................................ 20
2.12.1. Advanced timer..................................................................................................................... 20
2.12.2. General-purpose timer ......................................................................................................... 21
2.12.3. Low power timer (LPTIM) ..................................................................................................... 22
2.12.4. IWDG .................................................................................................................................... 22
2.12.5. WWDG ................................................................................................................................. 22
2.12.6. SysTick timer ........................................................................................................................ 22
2.13. Real time clock (RTC) .............................................................................................................. 23
2.14. I2C interface ............................................................................................................................. 23
2.15. Universal synchronous asynchronous recevicer/ transmitter (USART) ................................... 24
2.16. Serial peripheral interface (SPI) ............................................................................................... 25
2.17. SWD ......................................................................................................................................... 26
3. Pin configuration ............................................................................................................................... 27
3.1. Port A multiplexing function mapping .......................................................................................... 50
3.2. Port B multiplexing function mapping .......................................................................................... 51
3.3. Port F multiplexing function mapping ........................................................................................... 51
4. Memory Map ....................................................................................................................................... 52

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5. Electrical characteristics .................................................................................................................. 56

5.1. Test conditions ............................................................................................................................. 56
5.1.1. Min and Max ......................................................................................................................... 56
5.1.2. Typical value......................................................................................................................... 56
5.2. Absolute maximum ratings ........................................................................................................... 56
5.3. Operating conditions .................................................................................................................... 57
5.3.1. General operating conditions ............................................................................................... 57
5.3.2. Power on and down operating conditions ............................................................................ 57
5.3.3. Embedded reset and LVD module features ......................................................................... 57
5.3.4. Operating current characteristics ......................................................................................... 58
5.3.5. Low power mode wake-up time............................................................................................ 60
5.3.6. External clock source characteristics ................................................................................... 60
5.3.7. Internal high frequency clock source HSI characteristics .................................................... 61
5.3.8. Internal low frequency clock source LSI characteristics ...................................................... 62
5.3.9. Memory characteristics ........................................................................................................ 62
5.3.10. EFT characteristics ............................................................................................................... 63
5.3.11. ESD & LU Characteristics .................................................................................................... 63
5.3.12. Port characteristics ............................................................................................................... 63
5.3.13. NRST pin characteristics ...................................................................................................... 64
5.3.14. ADC characteristics .............................................................................................................. 64
5.3.15. Comparator characteristics .................................................................................................. 64
5.3.16. Temperature sensor characteristics ..................................................................................... 65
5.3.17. Internal reference voltage characteristics ............................................................................ 66
5.3.18. Timer characteristics ............................................................................................................ 66
5.3.19. Communication port characteristics ..................................................................................... 67
6. Package information ......................................................................................................................... 70
6.1. QFN20 .......................................................................................................................................... 70
6.2. TSSOP20 ..................................................................................................................................... 71
6.3. SOP20 .......................................................................................................................................... 72
6.4. SOP16 .......................................................................................................................................... 73
6.5. MSOP10 ....................................................................................................................................... 74
6.6. SOP8 ............................................................................................................................................ 75
6.7. DFN8(3*2) .................................................................................................................................... 76
7. Ordering Information ......................................................................................................................... 77
8. Version history................................................................................................................................... 78

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 PY32F003 Datasheet

1. Introduction
PY32F003 series microcontrollers are MCUs with high performance 32-bit ARM® Cortex® -M0 + core, wide
voltage operating range. It has embedded up to 64 Kbytes flash and 8 Kbytes SRAM memory, a maximum
operating frequency of 32 MHz, and contains various products in different package types. The chip inte-
grates multi-channel I2C, SPI, USART and other communication peripherals, one channel 12bit ADC, five
16bit timers, and two-channel comparators.

PY32F003 series microcontrollers are -40 ~ 85 ℃ and -40 ~ 105 ℃, the operating voltage range are 1.7 ~
5.5 V and 2.0 ~ 5.5 V. The chip provides sleep and stop low-power operating modes from meeting different
low-power applications.

The PY32F003 series of microcontrollers are suitable for various application scenarios, such as controllers,
portable devices, PC peripherals, gaming and GPS platforms, industrial applications.

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Table 1-1 PY32F003x6 series TSSOP20 product features and peripheral counts
PY32F003 PY32F003 PY32F003 PY32F003 PY32F003 PY32F003 PY32F003 PY32F003 PY32F003 PY32F003
Peripherals
F18P6 F18P6-E F16P6 F16P6-E F14P6 F26P6 F36P6 F48P6 F56P6 F68P6
Flash (Kbytes) 64 64 32 32 16 32 32 64 32 64
SRAM (Kbytes) 8 8 4 4 2 4 4 8 4 8
Advanced 1 (16-bit)
General
4 (16-bit)
pupose
Timers low power 1
SysTick 1
Watchdog 2
SPI 1
Comm.
inter- I2C 1
faces
USART 2
DMA 3ch
RTC Yes
GPIOs 18
12-bit ADC
8+2 9+2 6+2 6+2 7+2 10+2
( external + internal)
Comparators 2
Max. CPU frequency 32 MHz
Operating Voltage 1.7 ~ 5.5 V
Operating Temp. -40 ~ 85 °C
Package TSSOP20

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Table 1-2 PY32F003x6 series QFN20/SOP20 product features and peripheral counts
PY32F003F18 PY32F003F17 PY32F003F16 PY32F003F16 PY32F003F14 PY32F003F26 PY32F003F18
Peripherals
U6 U6 U6 U6-E U6 U6 S6
Flash (Kbytes) 64 48 32 32 16 32 64
SRAM (Kbytes) 8 6 4 4 2 4 8
Advanced 1 (16-bit)
General pupose 4 (16-bit)
Timers low power 1
SysTick 1
Watchdog 2
SPI 1
Comm.
I2C 1
interfaces
USART 2
DMA 3ch
RTC Yes
GPIOs 18
12-bit ADC
8+2 5+2 10+2
( external + internal)
Comparators 2
Max. CPU frequency 32 MHz
Operating Voltage 1.7 ~ 5.5 V
Operating Temperature -40 ~ 85 °C
Package QFN20 SOP20

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Table 1-3 PY32F003x6 series SOP16/MSOP10 product features and peripheral counts
Peripherals PY32F003W18S6 PY32F003W16S6 PY32F003W16S6-E PY32F003A18N6
Flash (Kbytes) 64 32 32 64
SRAM (Kbytes) 8 4 4 8
Advanced 1 (16-bit)
General pupose 4 (16-bit)
Timers low power 1
SysTick 1
Watchdog 2
SPI 1
Comm.
I2C 1
interfaces
USART 2
DMA 3ch
RTC Yes
GPIOs 14 8
12-bit ADC
10+2 5+2
( external + internal)
Comparators 2
Max. CPU frequency 32 MHz 24MHz
Operating Voltage 1.7 ~ 5.5 V
Operating Temperature -40 ~ 85 °C
Package SOP16 MSOP10

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Table 1-4 PY32F003x6 series SOP8/DFN8 product features and peripheral counts
Peripherals PY32F003L18S6 PY32F003L16S6 PY32F003L28S6 PY32F003L28D6 PY32F003L26D6 PY32F003L24D6
Flash (Kbytes) 64 32 64 64 32 16
SRAM (Kbytes) 8 4 8 8 4 2
Advanced 1 (16-bit)
General pupose 4 (16-bit)
Timers low power 1
SysTick 1
Watchdog 2
SPI 1
Comm.
I2C 1
interfaces
USART 1
DMA 3ch
RTC Yes
GPIOs 7
12-bit ADC
4+2
( external + internal)
Comparators 1 2
Max. CPU frequency 24 MHz
Operating Voltage 1.7 ~ 5.5 V
Operating Temperature -40 ~ 85 °C
Package SOP8 DFN8(3*2)

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1-5 PY32F003x7 series QFN20/TSSOP20 product features and peripheral counts

PY32F003F18 PY32F003F16 PY32F003F14 PY32F003F18 PY32F003F16 PY32F003F14 PY32F003F26 PY32F003F68
Peripherals
U7-E U7 U7 P7 P7 P7 P7 P7-E
Flash (Kbytes) 64 32 16 64 32 16 32 64
SRAM (Kbytes) 8 4 2 8 4 2 4 8
Advanced 1 (16-bit)
General
4 (16-bit)
pupose
Timers low power 1
SysTick 1
Watchdog 2
SPI 2
Comm.
I2C 1
interfaces
USART 2
DMA 3ch
RTC Yes
GPIOs 18 18 18 18
12-bit ADC
8+2 8+2 9+2 10+2
( external + internal)
Comparators 2
Max. CPU frequency 32 MHz
Operating Voltage 2.0 ~ 5.5 V
Operating Temperature -40 ~ 105 °C
Package QFN20 TSSOP20

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 PY32F003 Datasheet

1-6 PY32F003x7 series SOP16 product features and peripheral counts

Peripherals PY32F003W18S7
Flash (Kbytes) 64
SRAM (Kbytes) 8
Advanced 1 (16-bit)
General pupose 4 (16-bit)
Timers low power 1
SysTick 1
Watchdog 2
SPI 1
Comm.
I2C 1
interfaces
USART 2
DMA 3ch
RTC Yes
GPIOs 14
12-bit ADC
10+2
( external + internal)
Comparators 2
Max. CPU frequency 32 MHz
Operating Voltage 2.0 ~ 5.5 V
Operating Temp. -40 ~ 105 °C
Package SOP16

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 PY32F003 Datasheet

SWCLK POWER
SWDIO SWD DMA
Flash Memory Voltage
as AF VDD
Regulator
CPU

Bus matrix
TEST VCCIO
CORTEX-M0+ VCCA VCC
fmax= 32MHz VSS
VCC SUPPLY
SUPERVISION
SRAM
NVIC IOPORT POR/BOR

PVD PVD_IN

Filter NRST
HSI
RC 24MHz

WWDG reset
IWDG reset
GPIO

OBL reset
PA PORT A RC 32KHz HSI_10M 10MHz
LSI

S-AHB
Decoder

HSE XTAL OSC OSC_IN

PB PORT B CRC RCC 4-32MHz OSC_OUT
Reset! & clock control
PF PORT F

INT_CTRL System and peripheral

clocks, System reset
EXTI CH1~CH4, BKIN,
TIM1
CH1N~CH2N, ETR as AF
CH1~CH3, ETR
TIM3
from peripherals S-AHB TO S-APB as AF

TIM14 CH1 as AF
IN+ COMP1
IN- I/F CH1, CH1N

S-APB
T1M16/17
OUT COMP2 BKIN as AF

10xIN ADC I/F LPTIM IN1,ETR as AF

IWDG RTC 1Hz Out as AF

T sensor
S-APB

WWDG RX,TX,RTS,CTS,
USART1
CK as AF
PWR
MOSI,MISO,SCK RX,TX,RTS,CTS,
SPI1 USART2
NSS as AF SYSCFG CK as AF

DBGMCU I2C1 SCL,SDA

Power domain of analog modules: VCCA domain VCC domain VCCIO domain

Figure 1-1 Functional Module

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2 . F u n c t i o n a l o ve r vi ew
2.1. Arm®Cortex®-M0+ core
Arm ® The Cortex ® - M0+ is an entry-level 32-bit Arm Cortex processor designed for a wide range of
embedded applications. It provides developers with significant benefits, including:

 Simple structure, easy to learn and program

 Ultra-low power consumption, energy-saving operation

 Reduced code density and more

Cortex-M0+ processor is a 32-bit core optimized for area and power consumption and is a 2-stage
pipeline Von Neumann architecture. The processor offers high-end processing hardware, including
single-cycle multipliers, through a streamlined but powerful instruction set and an extensively optimized
design. Moreover, it delivers the superior performance expected from a 32-bit architecture computer,
with a higher coding density than other 8 and 16-bit microcontrollers.

The Cortex-M0+ is tightly coupled with a Nested Vectored Interrupt Controller (NVIC).

2.2. Memories
The on-chip integrated SRAM is accessed by bytes (8 bits), half-word (16bits) or word (32bits).
The on-chip integrated Flash consists of two different physical areas:
 Main flash area, which contains application and user data

 The information area has 4K bytes, and it includes the following parts:
— Option bytes
— UID bytes
— System memory

The protection of Flash main memory includes the following mechanisms:

 Read protection(RDP) prevents access from outside.
 Write protection (WRP) control prevents unwanted writes (confuse by program memory pointer
from PC). The minimum protection unit for write protection is 4K bytes.
 Option byte write protection, special unlocking design.

2.3. Boot mode

Through BOOT0 pin and boot configuration bit nBOOT1 (stored in Option bytes), three different boot
modes can be selected, as shown in the following table:

Table 2-1Boot configuration

Boot mode configuration
Mode
nBOOT1 bit BOOT0 pin
X 0 Select Main flash as the boot area
1 1 Select System memory as the boot area

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Boot mode configuration

Mode
nBOOT1 bit BOOT0 pin
0 1 Select SRAM as the boot area
The Boot loader program is stored in the System memory and used to download the Flash program through the
USART interface.

2.4. Clock System

After the CPU starts, the default system clock frequency is HSI 8 MHz, and the system clock frequency
and system clock source can be reconfigured after the program runs. The high frequency clocks that
can be selected are:

 A 4 /8/16/ 22.12/ 24 MHz configurable internal high precision HSI clock.

 A 32.768 KHz configurable internal LSI clock.

 4 ~ 32 MHz HSE clock can enable the CSS function to detect HSE. If CSS fails, the hardware will
automatically convert the system clock to HSI, and software configures the HSI frequency. Sim-
ultaneously, CPU NMI interrupt is generated.

The AHB clock can be divided based on the system clock, and the APB clock can be divided based
on the AHB clock. AHB and APB clock frequencies up to 32 MHz.

HSI：High-speed internal clock

LSI：Low-speed internal clock
HSE：High-speed external clock

LSI RC to IWDG
32.768kHz
LSI

to RTC
HSE
/32

RTCS to PWR
EL
To AHB bus, core, memory and DMA
AHB FCLK Cortex free-running clock
PRESC
/1，2...512 To Cortex system timer

LSI APB
PCLK To APB periphrals
MCO SYSCLK PRESC
/1...128 /1,2,4,8,16
HSE
HSI
PCLK
HSI RC to LPTIM
24MHz LSI

PCLK
to COMP
LSC

HSIDIV
PCLK
HSISYS to ADC
OSC_OUT HSE
HSI
4~32MHz HSE SYSCLK
OSC_IN Clock LSI If(APB prescaler=1) x1,
detector else x2

TIM_PCLK

Figure 2-1 System Clock Structure Diagram

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2.5. Power management

2.5.1. Power block diagram

VCCA VCCA domain

ADC COMP

LSI HSI

FLASH

VDD domain
VCC domain
HSI_10M HSE
POR
BOR
PDR
VDD CPU Core/Digital Peripherals
VCC VR

BG PVD VDD1
RTC IO_CTRL
PMU
IWDG LPTIMER
VCCIO
VCCIO domain
IO Ring PWR_Acon RCC_Acon
VDDA

VDDP

PWR_CR1[18]
SRAM
VDDA

Figure 2-2 Power Block Diagram

Table 2-2 Power Block Diagram

NO. Power supply Condition Power value Describe
x6 version 1.7 V ~ 5.5 V The chip is supplied with power through
1 VCC the power pins, and its power supply
x7 version 2.0 V ~ 5.5 V module is part of the analogue circuit.
x6 version 1.7 V ~ 5.5 V Power to most analogue modules from
2 VCCA VCC PAD (a separate power supply PAD
x7 version 2.0 V ~ 5.5 V can also be designed).
x6 version 1.7 V ~ 5.5 V
3 VCCIO Power supply to IO, from VCC PAD
x7 version 2.0 V ~ 5.5 V
VR supplies power to the main logic cir-
cuits and SRAM inside the chip. When
the MR is powered, it outputs 1.2 V. Ac-
4 VDD 1.2 V/1.0 V ± 10 % cording to the software configuration, en-
tering the stop mode can be powered by
MR or LPR, and the LPR output is deter-
mined to be 1.2 V or 1.0 V.

2.5.2. Power monitoring

[Link]. Power on reset (POR/PDR)

The Power on reset (POR)/Power down reset (PDR) module is designed to provide power-on and
power-off reset for the chip. The module keeps working in all modes.

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[Link]. Brown-out reset (BOR)

In addition to POR/ PDR, BOR ( brown-out reset ) is also implemented. BOR can only be enabled and
disabled through the option byte.

When the BOR is turned on, the BOR threshold can be selected by the Option byte, and both the rising
and falling detection points can be configured individually.

VCC

VBORR8
VBORF8
VBORR7
VBORF7
VBORR6
VBORF6
VBORR5
VBORF5
VBORR4
VBORF4
VBORR3
VBORF3
VBORR2
VBORF2
VBORR1
VBORF1
VPOR
VPDR
t

tRSTTEMPO

Reset with BOR off

tRSTTEMPO
Reset with BOR on
(VBOR8 VBOR1)
POR/BOR rising thresholds
PDR/BOR falling thresholds

Figure 2-3 POR/PDR/BOR threshold

[Link]. Voltage detection (PVD)

Programmable Voltage Detector (PVD) module can be used to detect the V CC power supply (it can
also detect the voltage of the PB7 pin ), and the detection point can be configured through the register.
When VCC is higher or lower than the detection point of PVD, a corresponding reset flag is generated.

This event is internally connected to line 16 of EXTI , depending on the rising/falling edge configuration
of EXTI line 16. When VCC rises above the PVD detection point, or V CC falls below the PVD detection
point , an interrupt is generated. In the service program, users can perform urgent shutdown tasks.

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VCC

VPVDRx

Configurable
hysteresis
VPVDFx

PVD output

Figure 2-4 PVD Threshold

2.5.3. Voltage regulator

The chip designs two voltage regulators:

 MR (Main regulator) keeps working when the chip is in normal operating state.

 LPR (Low power regulator) provides a lower power consumption option in stop mode.

2.5.4. Low power mode

In addition to the normal operating mode, the chip has 2 low-power modes:
 Sleep mode: Peripherals can be configured to keep working when the CPU clock is off (NVIC,
SysTick, etc.). It is recommended only to enable the modules that must work, and close the mod-
ule after the module works.
 Stop mode: In this mode, the contents of SRAM and registers are maintained, HSI and HSE are
turned off, and most modules of clocks in the VDD domain are stopped. GPIO, PVD, COMP output,
RTC and LPTIM can wake up stop mode.

2.6. Reset
Two resets are designed in the chip: power and system reset.

2.6.1. Power reset

A power reset occurs in the following situations:
 Power on reset (POR/PDR)
 Brown-out reset (BOR)

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2.6.2. System reset

A system reset occurs when the following events occur:
 Reset of NRST pin
 Windowed Watchdog Reset (WWDG)
 Independent Watchdog Reset (IWDG)
 SYSRESETREQ software reset
 Option byte load reset (OBL)
 Power reset (POR/PDR , BOR)

2.7. General-purpose input and output (GPIOs)

The software configures each GPIO as output (push-pull or open-drain ), input (floating, pull-up/down,
analogue), peripheral multiplexing function, and locking mechanism freeze I/O port configuration func-
tion.

2.8. DMA
Direct Memory Access (DMA) provides high-speed data transfer between peripherals and memory or
between memory and memory.

DMA controller has three channels, and each channel is responsible for managing memory access
requests from one or more peripherals. The DMA controller includes an arbiter for handling DMA re-
quests for each DMA request's priority..

DMA supports circular buffer management, eliminating the need for user code to intervene when the
controller reaches the end of the buffer.

Each channel is directly connected to a dedicated hardware DMA request, and each channel also
supports software triggering. These functions are configured through software.

DMA is available for peripherals: SPI, I2C, USART, all TIMx timers (except TIM14 and LPTIM) and
ADC.

2.9. Interrupt
The PY32F003 handles exceptions through the Cortex-M0+ processor's embedded Vectored Interrupt
Controller (NVIC) and an Extended Interrupt/Event Controller (EXTI).

2.9.1. Interrupt controller NVIC

NVIC is a tightly coupled IP inside the Cortex-M0+ processor. The NVIC can handle NMI (Non-Mas-
kable Interrupts) and maskable external interrupts from outside the processor and Cortex-M0+ internal
exceptions. NVIC provides flexible priority management.

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The tight coupling of the processor core to the NVIC greatly reduces the delay between an interrupt
event and the initiation of the corresponding interrupt service routine (ISR). The ISR vectors are listed
in a vector table, stored at a base address of the NVIC. The vector table base address determines the
vector address of the ISR to execute, and the ISR is used as the offset composed of serial numbers.

If a high-priority interrupt event occurs and a low-priority interrupt event is just waiting to be serviced,
the later-arriving high-priority interrupt event will be serviced first. Another optimization is called tail-
chaining. When returning from a high-priority ISR and then starting a pending low-priority ISR, unnec-
essary pushes and pops of processor contexts will be skipped. This reduces latency and improves
power efficiency.

NVIC features:
 Low latency interrupt handling

 Level 4 Interrupt Priority

 Supports one NMI interrupt

 Supports 32 maskable external interrupts

 Supports 10 Cortex-M0+ exceptions

 High-priority interrupts can interrupt low-priority interrupt responses

 Support tail-chaining optimization

 Hardware Interrupt Vector Retrieval

2.9.2. Extended interrupt/event controller (EXTI)

EXTI adds flexibility to handle physical wire events and generates wake-up events when the processor
wakes up from stop mode.

The EXTI controller has multiple channels, including a maximum of 16 GPIOs, 1 PVD output, 2 COMP
outputs, RTC and LPTIM wake-up signals. GPIO, PVD and COMP can be configured to be triggered
by a rising edge, falling edge or double edge. Any GPIO signal can be configured as EXTI0 ~ 15
channel through the select signal.

Each EXTI line can be independently masked through registers.

The EXTI controller can capture pulses shorter than the internal clock period.

Registers in the EXTI controller latch each event. Even in stop mode, after the processor wakes up
from stop mode, it can identify the wake-up source or identify the GPIO and event that caused the
interrupt.

2.10. Analog to digital converter ( ADC)

The chip has a 12-bit SAR ADC. The module has up to 12 channels to be measured, including 10
external channels and 2 internal channels.

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The conversion mode of each channel can be set to single, continuous, sweep, discontinuous mode.
Conversion results are stored in left or right-aligned 16-bit data registers.

An analogue watchdog allows the application to detect if the input voltage exceeds a user-defined high
or low threshold.

The ADC has been implemented to operate at a low frequency, resulting in lower power consumption.

At the end of sampling, conversion, and continuous conversion, an interrupt request is generated when
the conversion voltage exceeds the threshold when simulating the watchdog.

2.11. Comparators (COMP)

 Each comparator has configurable positive or negative inputs for flexible voltage selection
— Multiple I/O pins
— Power supply VCC
— The output of the temperature sensor
— Internal reference voltage and 3-part values supplied by divider (1/4, 1/2, 3/4)

 The hysteresis function is configurable

 Programmable speed and power consumption

 The output can be connected to the input of I/O or timer as a trigger

— OCREF_CLR event (current control of cycle by cycle)
— Brakes for fast PWM shutdown

Each COMP has interrupt generation capability to act as a wake-up of the chip from low-power modes
(sleep and stop modes) (via EXTI)

2.12. Timer
The characteristics of different timers of PY32F003 are shown in the following table:

Table 2-3 Timer Features

Bit Counting Capture /compare Complemen-
Types Timer Prescaler DMA
Width Direction channel tary output
superior,
Ad- Down,
TIM1 16-bit 1 ~ 65536 support 4 3
vanced center
aligned
superior,
Down,
TIM3 16-bit 1 ~ 65536 support 4 -
center
General aligned
purpose
TIM14 16-bit superior 1 ~ 65536 - 1 -
TIM16,
16-bit superior 1 ~ 65536 support 1 1
TIM17

2.12.1. Advanced timer

The advanced timer (TIM1) consists of a 16-bit auto-reload counter driven by a 16-bit programmable
prescaler. It can be used in various scenarios, including pulse length measurement of input signals

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 PY32F003 Datasheet

(input capture) or generating output waveforms (output compare, output PWM, complementary PWM
with dead-time insertion).

TIM1 includes 4 independent channels:

 Input capture

 Output comparison

 PWM generation (edge or center-aligned mode)

 Single pulse mode output

If TIM1 is configured as a standard 16-bit timer, it has the same characteristics as the TIMx timer. Full
modulation capability (0-100%) if configured as a 16-bit PWM generator.

In the MCU debug mode, TIM1 can freeze counting.

The timer feature with the same architecture is shared so that the TIM1 can work with other timers for
synchronization or event chaining through the timer chaining function.

TIM1 supports the DMA function.

2.12.2. General-purpose timer

[Link]. TIM3

The general-purpose timer TIM3 consists of a 16-bit auto-reload counter driven by a 16-bit program-
mable prescaler. It has 4 independent channels, each for input capture/output compare, PWM or single
pulse mode output.

TIM3 can work with TIM1 through the timer link function.

TIM3 supports the DMA function.

The TIM3 can process quadrature (incremental) encoder signals and digital outputs from 1 to 3 Hall
Effect Sensors.

In the MCU debug mode, the TIM 3 can freeze counting.

[Link]. TIM14

The general-purpose timer TIM14 consists of a 16-bit auto-reload counter driven by a 16-bit program-
mable prescaler.

TIM14 has one independent channel for input capture/output compare, PWM or single pulse mode
output.

In the MCU debug mode, the TIM14 can freeze counting.

[Link]. TIM16/TIM17

The general-purpose timer TIM16 and TIM17 consists of a 16-bit auto-reload counter driven by a 16-
bit programmable prescaler.

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 PY32F003 Datasheet

TIM16/TIM17 have 1 independent channel for input capture/output compare, PWM or single pulse
mode output.

TIM16/TIM17 have one independent channel for input capture/output compare, PWM or single pulse
mode output.

TIM16/TIM17 have complementary outputs with dead time.

TIM16/TIM17 supports the DMA function.

In the MCU debug mode, TIM 16/TIM17 can freeze counting.

2.12.3. Low power timer (LPTIM)

LPTIM is a 16 -bit up counter with a 3-bit prescaler and only support a single count.

LPTIM can be configured as a stop mode wakeup source.

In the MCU debug mode, LPTIM can freeze the count value.

2.12.4. IWDG
Independent watchdog (IWDG) is integrated in the chip, and this module has the characteristics of
high-security level, accurate timing and flexible use. IWDG finds and resolves functional confusion due
to software failure and triggers a system reset when the counter reaches the specified timeout value.

The IWDG is clocked by LSI, so even if the main clock fails, it can keep working.

IWDG is the best suited for applications that require the watchdog as a standalone process outside of
the main application and do not have high timing accuracy constraints.

Controlling of option byte can enable IWDG hardware mode.

IWDG is the wake-up source of stop mode, which wakes up stop mode by reset.

In the MCU debug mode, IWDG can freeze the count value.

2.12.5. WWDG
The system window watchdog is based on a 7-bit down counter and can be set to free-run. It acts as
a watchdog to reset the system when a failure shows. The count clock is the APB clock (PCLK). It has
early warning interrupt capability, and the counter can be freeze in the MCU debug mode.

2.12.6. SysTick timer

SysTick counters are specifically for real-time operating systems (RTOS) also can use as standard
down counters.

SysTick Features:

 24-bit count down

 Self-loading capability

 An interrupt can be generated when the counter reaches 0 (maskable)

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 PY32F003 Datasheet

2.13. Real time clock (RTC)

The real-time clock is an independent timer. It has a set of continuous counting counters, which can
provide a clock calendar function under the corresponding software configuration. Modifying the value
of the counter can reset the current time and date of the system.

RTC is a 32-bit programmable counter with a prescale factor of up to 220 bits.

The RTC counter clock source can be LSI and the stop wake-up source.

RTC can generate alarm interrupt, second interrupt and overflow interrupt (maskable).

RTC supports clock calibration.

In the MCU debug mode, RTC can freeze counting.

2.14. I2C interface

I2C (inter-integrated circuit) bus interface connects the microcontroller and the serial I 2C bus. It pro-
vides multi-master capability and controls all I2C bus specific sequences, protocols, arbitration and
timing. Standard (Sm ) and fast (Fm) are supported.

I2C Features:
 Slave and master mode
 Multi-host function: can be master or slave
 Support different communication speeds
— Standard Mode (Sm): Up to 100 kHz
— Fast Mode (Fm): up to 400 kHz
 As master
— Generate Clock
— Generation of Start and Stop
 As slave
— Programmable I2C address detection
— Discovery of the Stop bit
 7-bit addressing mode
 General call
 Status flag
— Transmit/receive mode flags
— Byte transfer complete flag
— I2C busy flag bit
 Error flag
— Master a rbitration loss
— ACK failure after address/data transfer
— Start/Stop error
— Overrun/Underrun (clock stretching function disable)

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 PY32F003 Datasheet

 Optional Clock Stretching

 Single-byte buffer with DMA capability
 Software reset
 Analogue noise filter function

2.15. Universal synchronous asynchronous recevicer/ transmit-

ter (USART)
PY32F003 contains 2 USARTs with precisely the same functions.

The Universal Synchronous Asynchronous Transceiver (USART) provides a flexible method for full-
duplex data exchange with external devices using the industry-standard NRZ asynchronous serial data
format. The USART utilizes a fractional baudrate generator to provide a wide range of baudrate options.

It supports simultaneous one-way communication and half-duplex single-wire communication, and it

also allows multi-processor communication.

Automatic baudrate detection is supported.

High-speed data communication can be achieved by using the DMA method of the multi-buffer config-
uration.

USART features:
 Full-duplex asynchronous communication
 NRZ standard format
 Configurable 16 times or 8 times oversampling for increased flexibility in speed and clock toler-
ance
 Programmable baudrate shared by transmit and receive, up to 4.5 Mbit/s
 Automatic baudrate detection
 Programmable data length of 8 or 9 bits
 Configurable stop bits (1 bit or 2 bits)
 Synchronous mode and clock output function for synchronous communication
 Single-wire half-duplex communication
 Independent transmit and receive enable bits
 Hardware flow control
 Receive/transmit bytes by DMA buffer
 Detection flag
— Receive full buffer
— Send empty buffer
— End of transmission
 Parity Control
— Send check digit
— Check the received data

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 PY32F003 Datasheet

 Flagged interrupt sources

— CTS change
— Send empty register
— Send completed
— Receive full data register
— Bus idle detected
— Overflow error
— Frame error
— Noise operation
— Error detection
 Multiprocessor communication
— If the address does not match, enter silent mode
 Wake-up from silent mode: by idle detection and address flag detection

2.16. Serial peripheral interface (SPI)

PY32F003 contains one SPI.

Serial Peripheral Interface (SPI) allows the chip to communicate with external devices in half-duplex,
full-duplex, and simplex synchronous serial communication. This interface can be configured in master
mode and provides the communication clock (SCK) for external slave devices. The interface can also
work in a multi-master configuration.

The SPI features are as follows:

 Master or slave mode
 3 -wire full-duplex simultaneous transmission
 2-wire half-duplex synchronous transmission (with bidirectional data line)
 2-wire simplex synchronous transmission (no bidirectional data line)
 8-bit or 16-bit transmission frame selection
 Support multi-master mode
 8 master mode baudrate prescaler factors (max fPCLK/ 4)
 Slave mode frequency (max fPCLK/4)
 Both master and slave modes can be managed by software or hardware NSS: dynamic change
of master/slave operating mode
 Programmable clock polarity and phase
 Programmable data order, MSB first or LSB first
 Dedicated transmit and receive flags that can trigger interrupts
 SPI bus busy status flag
 Motorola mode
 Interrupt-causing master mode faults, overloads
 Two 32-bit Rx and Tx FIFOs with DMA capability

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 PY32F003 Datasheet

2.17. SWD
The ARM SWD interface allows serial debugging tools to be connected to the PY32F003.

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 PY32F003 Datasheet

3. Pin configuration

PA4

PA2

PA1
PA0
PA3
19

16
20

18

17
0

PA5 1 15 PF2-NRST

PA6 2 14 PF1

PA7 3 QFN20 13 PF0

VSS 4 12 PF4
PA12 5 11 PB7
Exposed pad

10
7

9
6

8 VSS
PA13-SWD

PA14-SWC

PB6
PB5
VCC

Figure 3-1 QFN20 Pinout1 PY32F003F1xUx / PY32F003F1xUx-E

PF2-NRST
PA1
PA0

PF1
PF0
17
16
20
19

18

0
PA2 1 15 PB8

PA3 2 14 PF4
PA4 3 QFN20 13 PB7
VSS 4 12 PB5
PB2 5 11 PB4
Exposed pad
10
6

8
7

VSS
PA13-SWD

PA14-SWC
PA10
PA9
VCC

Figure 3-2 QFN20 Pinout2 PY32F003F2xUx

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 PY32F003 Datasheet

PA2 1 20 PA1

PA3 2 19 PA0

PA4 3 18 PF2-NRST

TSSOP20
PA5 4 17 PF1

PA6 5 16 PF0

PA7 6 15 PF4

VSS 7 14 PB7

PA12 8 13 PB6

VCC 9 12 PB5

PA13-SWD 10 11 PA14-SWC

Figure 3-3 TSSOP20 Pinout1 PY32F003F1xPx / PY32F003F1xPx-E

PA3 1 20 PA2
PA4 2 19 PA1

PA5 3 18 PA0
TSSOP20

PA6 4 17 PF2-NRST

PA7 5 16 PF1

PB1 6 15 PF0

VSS 7 14 PF4

PB2 8 13 PB3

VCC 9 12 PA14-SWC

PA12 10 11 PA13-SWD

Figure 3-4 TSSOP20 Pinout2 PY32F003F2xPx

PA1 1 20 PA0
PA2 2 19 PF2-NRST

PA3 3 18 PF4
TSSOP20

PA4 4 17 PB7

PF0 5 16 PB6

PA7 6 15 PB5

VSS 7 14 PB4

PB2 8 13 PB3

VCC 9 12 PA14-SWC

PA12 10 11 PA13-SWD

Figure 3-5 TSSOP20 Pinout3 PY32F003F3xPx

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 PY32F003 Datasheet

PF1 1 20 PF0
PA2/PF2-NRST 2 19 PA7

PA3 3 18 PA13-SWD

TSSOP20
PA4 4 17 PA14-SWC

PB0 5 16 PB4

PB1 6 15 PB3

VSS 7 14 PA15

PB2 8 13 PA12

VCC 9 12 PA11

PA9 10 11 PA10

Figure 3-6 TSSOP20 Pinout4 PY32F003F4xPx

PA2 1 20 PA1
PA3 2 19 PF3

PA4 3 18 PF2-NRST
TSSOP20

PA5 4 17 PF1

PA6 5 16 PF0

PA7 6 15 PF4

VSS 7 14 PB8

PB2 8 13 PB6

VCC 9 12 PB5

PA13-SWD 10 11 PA14-SWC

Figure 3-7 TSSOP20 Pinout5 PY32F003F5xPx

VCC 1 20 PA7

VSS 2 19 PA6

PB1 3 18 PA4
TSSOP20

PA10 4 17 PA3

PA11 5 16 PA2

PA12 6 15 PA1

PA14-SWC 7 14 PA0

PA13-SWD 8 13 PF2-NRST

PB0 9 12 PF1

PA5 10 11 PF0

Figure 3-8 TSSOP20 Pinout6 PY32F003F6xPx / PY32F003F6xPx-E

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 PY32F003 Datasheet

PA4 1 20 PA1
PA5 2 19 PA0
PA6 3 18 PF2-NRST
PA7 4 17 PF1

SOP20
PB0 5 16 PF0
PB1 6 15 PA2
VSS 7 14 PA3
PB2 8 13 PF4
VCC 9 12 PA14-SWC
PA12 10 11 PA13-SWD

Figure 3-9 SOP20 Pinout1 PY32F003F1xSx

VSS 1 16 VCC

PA12 2 15 PB1

PA13-SWD 3 14 PB0
SOP16

PF1/PA14-SWC 4 13 PA7

PF0/PF2-NRST 5 12 PA6

PA0 6 11 PA5

PA1 7 10 PA4

PA2 8 9 PA3

Figure 3-10 SOP16 Pinout1 PY32F003W1xSx / PY32F003W1xSx-E

VCC 1 10 VSS
MSOP10

PA12/PA13-SWD 2 9 PA2
PB6/PA14-SWC 3 8 PA1
PA4 4 7 PA0
PA3 5 6 PF2-NRST

Figure 3-11 MSOP10 PY32F003A1xNx

VCC 1 8 VSS
SOP8

PA0 2 7 PB5/PA14-SWC

PA1 3 6 PA10/PA13-SWD

PA2 4 5 PB0/PF2-NRST

Figure 3-12 SOP8 PY32F003L1xSx

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 PY32F003 Datasheet

VCC 1 8 VSS

SOP8
PA0 2 7 PB7/PA14-SWC

PA1 3 6 PA10/PA13-SWD

PA2 4 5 PB0/PF2-NRST

Figure 3-13 SOP8 PY32F003L2xSx

VCC 1 8 PB5
PA0 2 7 PA14-SWC/PB6
DFN8
PA1 3 6 PA13-SWD/PA10
Exposed pad
PA2 4 5 PB0/PF2-NRST

VSS

Figure 3-14 DFN8(3*2) PY32F003L2xDx

Table 3-1 Pin definition terminology and symbols

Types Symbol Definition
S Supply pin
G Ground p in
Port type
I/O Input/output pin
NC Undefined
COM 5V port, support analogue input and output function
Port structure Reset port, with internal weak pull-up resistor, does not
RST
support analog input and output function
Unless other specified, all ports are used as floating inputs
Notes -
between and after reset
Port Multiplexing function - Function selected by GPIOx_AFR register
function Additional function - Directly selected or enabled through peripheral registers

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 PY32F003 Datasheet

Table 3-2 QFN20/TSSOP20/SOP20 pin definition

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

USART2_RX
TIM14_CH1
13 16 16 15 5 20 16 11 16 PF0-OSC_IN I/O COM USART1_RX OSC_IN
USART2_TX
I2C_SDA
USART2_TX
USART1_TX
USART2_RX
14 17 17 16 - 1 17 12 17 PF1-OSC_OUT I/O COM OSC_OUT
I2C_SCL
SPI1_NSS
TIM14_CH1
MCO
15 18 18 17 19 2 18 13 18 PF2-NRST I/O RST (1) NRST
USART2_RX
USART1_TX
USART2_TX
- - - - - - 19 - - PF3 I/O COM RTC_OUT COMP2_INP
SPI1_NSS
TIM3_CH3
USART1_CTS
USART2_CTS
ADC_IN0
16 19 19 18 20 - - 14 19 PA0 I/O COM COMP1_OUT
COMP1_INM
TIM1_CH3
TIM1_CH1N

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 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

SPI1_MISO
USART2_TX
IR_OUT
SPI1_SCK
USART1_RTS
USART2_RTS
EVENTOUT
ADC_IN1
17 20 20 19 1 - 20 15 20 PA1 I/O COM SPI1_MOSI
COMP1_INP
USART2_RX
TIM1_CH4
TIM1_CH2N
MCO
SPI1_MOSI
USART1_TX
USART2_TX
ADC_IN2
18 1 1 20 2 2 1 16 15 PA2 I/O COM COMP2_OUT
COMP2_INM
SPI1_SCK
TIM3_CH1
I2C_SDA
USART1_RX
USART2_RX
EVENTOUT ADC_IN3
19 2 2 1 3 3 2 17 14 PA3 I/O COM
SPI1_MOSI COMP2_INP
TIM1_CH1
I2C_SCL

33of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

SPI1_NSS
USART1_CK
TIM14_CH1
USART2_CK
20 3 3 2 4 4 3 18 1 PA4 I/O COM ADC_IN4
ENENTOUT
RTC_OUT
TIM3_CH3
USART2_TX
SPI1_SCK
LPTIM_ETR
EVENTOUT
1 - 4 3 - - 4 10 2 PA5 I/O COM ADC_IN5
TIM3_CH2
USART2_RX
MCO
SPI1_MISO
TIM3_CH1
TIM1_BKIN
2 - 5 4 - - 5 19 3 PA6 I/O COM TIM16_CH1 ADC_IN6
COMP1_OUT
USART1_CK
RTC_OUT
SPI1_MOSI
TIM3_CH2
3 - 6 5 6 19 6 20 4 PA7 I/O COM ADC_IN7
TIM1_CH1N
TIM14_CH1

34of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

TIM17_CH1
EVENTOUT
COMP2_OUT
USART1_TX
USART2_TX
I2C_SDA
SPI1_MISO
SPI1_NSS
TIM3_CH3
- - - - - 5 - 9 5 PB0 I/O COM TIM1_CH2N ADC_IN8
EVENTOUT
COMP1_OUT
TIM14_CH1
TIM3_CH4 ADC_IN9
- - - 6 - 6 - 3 6 PB1 I/O COM
TIM1_CH3N COMP1_INM
EVENTOUT
4 4 7 7 7 7 - 2 7 VSS S Ground
USART1_RX
- 5 - 8 8 8 8 - 8 PB2 I/O COM COMP1_INP
USART2_RX
6 6 9 9 9 9 9 1 9 VCC S Digital power supply
USART1_CK
TIM1_CH1
- - - - - - - - - PA8 I/O COM USART2_CK -
MCO
EVENTOUT

35of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

USART1_RX
USART2_RX
SPI1_MOSI
I2C_SCL
USART1_TX
TIM1_CH2
MCO
I2C_SCL
- 7 - - - 10 - - - PA9 I/O COM EVENTOUT OSC32OUT
I2C_SDA
TIM1_BK
SPI1_SCK
USART1_RX
USART1_RX
TIM1_CH3
TIM17_BKIN
USART2_RX
I2C_SDA
- 8 - - - 11 - 4 - PA10 I/O COM OS32IN
EVENTOUT
I2C_SCL
SPI1_NSS
USART1_TX
IR_OUT
SPI1_MISO
- - - - - 12 - 5 - PA11 I/O COM -
USART1_CTS

36of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

TIM1_CH4
EVENTOUT
USART2_CTS
I2C_SCL
COMP1_OUT
SPI1_MOSI
USART1_RTS
TIM1_ETR
5 - 8 10 10 13 - 6 10 PA12 I/O COM USART2_RTS -
EVENTOUT
I2C_SDA
COMP2_OUT
SWDIO
IR_OUT
EVENTOUT
PA13
7 9 10 11 11 18 10 8 11 I/O COM (2) SPI1_MISO -
(SWDIO)
TIM1_CH2
USART1_RX
MCO
SWCLK
USART1_TX
PA14
8 10 11 12 12 17 11 7 12 I/O COM (2) USART2_TX -
(SWCLK)
EVENTOUT
MCO
- - - - - 14 - - - PA15 I/O COM SPI1_NSS -

37of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

USART1_RX
USART2_RX
EVENTOUT
SPI1_SCK
TIM1_CH2
- - - 13 13 15 - - - PB3 I/O COM USART1_RTS COMP2_INM
USART2_RTS
EVENTOUT
SPI1_MISO
TIM3_CH1
USART2_CTS
- 11 - - 14 16 - - - PB4 I/O COM COMP2_INP
USART1_CTS
TIM17_BKIN
EVENTOUT
SPI1_MOSI
TIM3_CH2
TIM16_BKIN
9 12 12 - 15 - 12 - - PB5 I/O COM USART2_CK -
USART1_CK
LPTIM_IN1
COMP1_OUT
USART1_TX
TIM1_CH3
10 - 13 - 16 - 13 - - PB6 I/O COM COMP2_INP
TIM16_CH1N
USART2_TX

38of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
TSSOP20 F1

TSSOP20 F2

TSSOP20 F3

TSSOP20 F4

TSSOP20 F5

TSSOP20 F6

SOP20 F1
QFN20 F1

QFN20 F2

Notes
Reset
Multiplexing Additional

I2C_SCL
LPTIM_ETR
EVENTOUT
USART1_RX
TIM17_CH1N
COMP2_INM
11 13 14 - 17 - - - - PB7 I/O COM USART2_RX
PVD_IN
I2C_SDA
EVENTOUT

12 14 15 14 18 - 15 - 13 PF4-BOOT0 I/O COM (3) - BOOT0

TIM16_CH1
I2C1_SCL
USART2_TX
EVENTOUT
- 15 - - - - 14 - - PB8 I/O COM COMP1_INP
USART1_TX
I2C_SDA
TIM17_CH1
IR_OUT
- - - - - - - - - VSS S Ground
1. Selecting PF2 or NRST is configured through option bytes .

2. After reset, the two pins of PA13 and PA14 are configured as SWDIO and SWCLK AF function, the former internal pull-up resistor, the latter internal pull-down
resistor is activated.

3. PF4 -BOOT0 is the default digital input mode, and the pull-down is enabled.

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 PY32F003 Datasheet

Table 3-3 SOP16/MSOP10 pin definition

Packages Functions

Port structure
Port type
MSOP10 P1
SOP16 W1

Notes
Reset
Multiplexing Additional

1 10 VSS S Ground
SPI1_MOSI
USART1_RTS
TIM1_ETR
2 2 PA12 I/O COM USART2_RTS -
EVENTOUT
I2C_SDA
COMP2_OUT
SWDIO
IR_OUT
EVENTOUT
3 2 PA13(SWDIO) I/O COM (2) SPI1_MISO -
TIM1_CH2
USART1_RX
MCO
USART2_TX
USART1_TX
USART2_RX
4 - PF1-OSC_OUT-（PF1） I/O COM OSC_OUT
I2C_SCL
SPI1_NSS
TIM14_CH
SWCLK
4 3 PA14(SWCLK) I/O COM (2) USART1_TX -
USART2_TX

40of 78
 PY32F003 Datasheet

Packages Functions

Port structure
Port type
MSOP10 P1
SOP16 W1

Notes
Reset
Multiplexing Additional

EVENTOUT
MCO
USART1_TX
TIM1_CH3
TIM16_CH1N
- 3 PB6 I/O COM USART2_TX COMP2_INP
I2C_SCL
LPTIM_ETR
EVENTOUT
USART2_RX
TIM14_CH1
5 - PF0-OSC_IN-（PF0） I/O COM USART1_RX OSC_IN
USART2_TX
I2C_SDA
MCO
5 6 PF2-NRST I/O RST (1) NRST
USART2_RX
USART1_CTS
USART2_CTS
COMP1_OUT
TIM1_CH3 ADC_IN0
6 7 PA0 I/O COM
TIM1_CH1N COMP1_INM
SPI1_MISO
USART2_TX
IR_OUT
7 8 PA1 I/O COM SPI1_SCK

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 PY32F003 Datasheet

Packages Functions

Port structure
Port type
MSOP10 P1
SOP16 W1

Notes
Reset
Multiplexing Additional

USART1_RTS
USART2_RTS
EVENTOUT
SPI1_MOSI COMP1_INP
USART2_RX ADC_IN1
TIM1_CH4
TIM1_CH2N
MCO
SPI1_MOSI
USART1_TX
USART2_TX
COMP2_INM
8 9 PA2 I/O COM COMP2_OUT
ADC_IN2
SPI1_SCK
TIM3_CH1
I2C_SDA
USART1_RX
USART2_RX
EVENTOUT COMP2_INP
9 5 PA3 I/O COM
SPI1_MOSI ADC_IN3
TIM1_CH1
I2C_SCL
SPI1_NSS
USART1_CK
10 4 PA4 I/O COM ADC_IN4
TIM14_CH1
USART2_CK

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 PY32F003 Datasheet

Packages Functions

Port structure
Port type
MSOP10 P1
SOP16 W1

Notes
Reset
Multiplexing Additional

ENENTOUT
RTC_OUT
TIM3_CH3
USART2_TX
SPI1_SCK
LPTIM_ETR
EVENTOUT
11 - PA5 I/O COM ADC_IN5
TIM3_CH2
USART2_RX
MCO
SPI1_MISO
TIM3_CH1
TIM1_BKIN
TIM16_CH1
12 - PA6 I/O COM ADC_IN6
EVENTOUT
COMP1_OUT
USART1_CK
RTC_OUT
SPI1_MOSI
TIM3_CH2
TIM1_CH1N
13 - PA7 I/O COM TIM14_CH1 ADC_IN7
TIM17_CH1
EVENTOUT
COMP2_OUT

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 PY32F003 Datasheet

Packages Functions

Port structure
Port type
MSOP10 P1
SOP16 W1

Notes
Reset
Multiplexing Additional

USART1_TX
USART2_TX
I2C_SDA
SPI1_MISO
SPI1_NSS
TIM3_CH3
14 - PB0 I/O COM TIM1_CH2N ADC_IN8
EVENTOUT
COMP1_OUT
TIM14_CH1
TIM3_CH4 COMP1_INM
15 - PB1 I/O COM
TIM1_CH3N ADC_IN9
EVENTOUT
16 1 VCC S Digital power supply
1. Selecting PF2 or NRST is configured through option bytes .

2. After reset, the two pins of PA13 and PA14 are configured as SWDIO and SWCLK AF function, the former internal pull-up resistor, the latter internal pull-down
resistor is activated.

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 PY32F003 Datasheet

Table 3-4 SOP8 pin definition

Functions

Port struc-
Packages

Port type

Notes
SOP8 L1

SOP8 L2

ture
Reset
Multiplexing Additional

1 1 VCC S Digital power supply

USART1_CTS
COMP1_OUT
TIM1_CH3 ADC_IN0
2 2 PA0 I/O COM
TIM1_CH1N COMP1_INM
SPI1_MISO
IR_OUT
SPI1_SCK
USART1_RTS
EVENTOUT
COMP1_INP
3 3 PA1 I/O COM SPI1_MOSI
ADC_IN1
TIM1_CH4
TIM1_CH2N
MCO
SPI1_MOSI
USART1_TX
4 4 PA2 I/O COM SPI1_SCK ADC_IN2
TIM3_CH1
I2C_SDA
PF2-NRST I/O RST (1) MCO NRST
SPI1_NSS
TIM3_CH3
5 5
PB0 I/O COM TIM1_CH2N ADC_IN8
EVENTOUT
COMP1_OUT
6 6 PA10 I/O COM USART1_RX

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 PY32F003 Datasheet

Functions

Port struc-
Packages

Port type

Notes
SOP8 L1

SOP8 L2

ture
Reset
Multiplexing Additional

TIM1_CH3
TIM17_BKIN
I2C_SDA
EVENTOUT
I2C_SCL
SPI1_NSS
USART1_TX
IR_OUT
SWDIO
IR_OUT
EVENTOUT
PA13(SWDIO) I/O COM (2) SPI1_MISO -
TIM1_CH2
USART1_RX
MCO
SWCLK
USART1_TX
7 PA14(SWCLK) I/O COM (2) -
EVENTOUT
MCO
SPI1_MOSI
7
TIM3_CH2
TIM16_BKIN
- PB5 I/O COM_L
USART1_CK
LPTIM_IN1
COMP1_OUT
COMP2_INM
- 7 PB7 I/O COM_L USART1_RX
PVD_IN

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 PY32F003 Datasheet

Functions

Port struc-
Packages

Port type

Notes
SOP8 L1

SOP8 L2

ture
Reset
Multiplexing Additional

TIM17_CH1N
USART2_RX
I2C_SDA
EVENTOUT
8 - VSS S Digital power supply
1. Selecting PF2 or NRST is configured through option bytes .

2. After reset, the two pins of PA13 and PA14 are configured as SWDIO and SWCLK AF function, the former internal pull-up resistor, the latter internal pull-down
resistor is activated.

Table 3-5 DFN8 pin definition

Functions

Port structure
Packages Port type

Notes
DFN8 L2

Reset
Multiplexing Additional

1 VCC S Digital power supply

USART1_CTS
COMP1_OUT
TIM1_CH3 ADC_IN0
2 PA0 I/O COM
TIM1_CH1N COMP1_INM
SPI1_MISO
IR_OUT
SPI1_SCK
USART1_RTS COMP1_INP
3 PA1 I/O COM
EVENTOUT ADC_IN1
SPI1_MOSI

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 PY32F003 Datasheet

Functions

Port structure
Packages

Port type

Notes
DFN8 L2 Reset
Multiplexing Additional

TIM1_CH4
TIM1_CH2N
MCO
SPI1_MOSI
USART1_TX
COMP2_OUT COMP2_INM
4 PA2 I/O COM
SPI1_SCK ADC_IN2
TIM3_CH1
I2C_SDA
PF2-NRST I/O RST (1) MCO NRST
SPI1_NSS
TIM3_CH3
5
PB0 I/O COM TIM1_CH2N ADC_IN8
EVENTOUT
COMP1_OUT
USART1_RX
TIM1_CH3
TIM17_BKIN
I2C_SDA
PA10 I/O COM EVENTOUT OS32IN
6 I2C_SCL
SPI1_NSS
USART1_TX
IR_OUT
SWDIO
PA13(SWDIO) I/O COM (2) -
IR_OUT

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 PY32F003 Datasheet

Functions

Port structure
Packages

Port type

Notes
DFN8 L2 Reset
Multiplexing Additional

EVENTOUT
SPI1_MISO
TIM1_CH2
USART1_RX
MCO
SWCLK
USART1_TX
PA14(SWCLK) I/O COM (2) -
EVENTOUT
MCO
USART1_TX
7
TIM1_CH3
TIM16_CH1N
PB6 I/O COM COMP2_INP
I2C_SCL
LPTIM_ETR
EVENTOUT
SPI1_MOSI
TIM3_CH2
TIM16_BKIN
8 PB5 I/O COM_L -
USART1_CK
LPTIM_IN1
COMP1_OUT
1. Selecting PF2 or NRST is configured through option bytes .

2. After reset, the two pins of PA13 and PA14 are configured as SWDIO and SWCLK AF function, the former internal pull-up resistor, the latter internal pull-down
resistor is activated.

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 PY32F003 Datasheet

3.1. Port A multiplexing function mapping

Table 3-6 Port A multiplexing function mapping
Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- USART1_CTS - - USART2_CTS - - COMP1_OUT
PA0 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- USART2_TX SPI1_MISO - - TIM1_CH3 TIM1_CH1N IR_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_SCK USART1_RTS - - USART2_RTS - - EVENTOUT
PA1
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- USART2_RX SPI1_MOSI - - TIM1_CH4 TIM1_CH2N MCO
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_MOSI USART1_TX - - USART2_TX - - COMP2_OUT
PA2
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- - SPI1_SCK - I2C_SDA TIM3_CH1 - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- USART1_RX - - USART2_RX - - EVENTOUT
PA3
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- - SPI1_MOSI - I2C_SCL TIM1_CH1 - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_NSS USART1_CK - - TIM14_CH1 USART2_CK - EVENTOUT
PA4
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- USART2_TX - - - TIM3_CH3 - RTC_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_SCK - - - - LPTIM1_ETR - EVENTOUT
PA5
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- USART2_RX - - - TIM3_CH2 - MCO
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_MISO TIM3_CH1 TIM1_BKIN - - TIM16_CH1 - COMP1_OUT
PA6
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_CK - - - - - - RTC_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SPI1_MOSI TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT
PA7
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_TX USART2_TX SPI1_MISO - I2C_SDA - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- USART1_CK TIM1_CH1 - USART2_CK MCO - EVENTOUT
PA8
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_RX USART2_RX SPI1_MOSI - I2C_SCL - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- USART1_TX TIM1_CH2 - USART2_TX MCO I2C_SCL EVENTOUT
PA9
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_RX - SPI1_SCK - I2C_SDA TIM1_BKIN - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- USART1_RX TIM1_CH3 - USART2_RX TIM17_BKIN I2C_SDA EVENTOUT
PA10
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_TX - SPI1_NSS - I2C_SCL - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA11
SPI1_MISO USART1_CTS TIM1_CH4 - USART2_CTS EVENTOUT I2C_SCL COMP1_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA12
SPI1_MOSI USART1_RTS TIM1_ETR - USART2_RTS EVENTOUT I2C_SDA COMP2_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SWDIO IR_OUT - - - - - EVENTOUT
PA13
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_RX - SPI1_MISO - - TIM1_CH2 - MCO
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
SWCLK USART1_TX - - USART2_TX - - EVENTOUT
PA14
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- - - - - - - MCO
PA15 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

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 PY32F003 Datasheet

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1_NSS USART1_RX - - USART2_RX - - EVENTOUT

3.2. Port B multiplexing function mapping

Table 3-7 Port B multiplexing function mapping
Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB0 SPI1_NSS TIM3_CH3 TIM1_CH2N - - EVENTOUT - COMP1_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB1
TIM14_CH1 TIM3_CH4 TIM1_CH3N - - - - EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB2
USART1_RX - - USART2_RX - - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB3
SPI1_SCK TIM1_CH2 - USART1_RTS USART2_RTS - - EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB4
SPI1_MISO TIM3_CH1 - USART1_CTS USART2_CTS TIM17_BKIN - EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB5
SPI1_MOSI TIM3_CH2 TIM16_BKIN USART1_CK USART2_CK LPTIM_IN1 - COMP1_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB6
USART1_TX TIM1_CH3 TIM16_CH1N - USART2_TX LPTIM_ETR I2C_SCL EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PB7
USART1_RX - TIM17_CH1N - USART2_RX - I2C_SDA EVENTOUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- - TIM16_CH1 - USART2_TX - I2C_SCL EVENTOUT
PB8
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_TX - - - I2C_SDA TIM17_CH1 - IR_OUT

3.3. Port F multiplexing function mapping

Table 3-8 Port F multiplexing function mapping
Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- - TIM14_CH1 - USART2_RX - - -
PF0-OSC_IN AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_RX USART2_TX - - I2C_SDA - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
- - - - USART2_TX - - -
PF1_OSC_OUT
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
USART1_TX USART2_RX SPI1_NSS - I2C_SCL TIM14_CH1 - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PF2-NRST
- - - - USART2_RX - MCO -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
USART1_TX - - - USART2_TX - - -
PF3
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
- - SPI1_NSS - - TIM3_CH3 - RTC_OUT
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PF4-BOOT0
- - - - - - - -

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 PY32F003 Datasheet

4. Memory Map
0xFFFF FFFF
User space

Block 7 Reserved space

ARM Cortex M0+
0xE000 0000 Internal periphrals

Block 6

0xC000 0000 0x5001 1FFF

IOPORT
0x5000 0000

Block 5
0x4002 63FF
0xA000 0000 AHB
0x4002 0000

Block 4
0x4001 5BFF
APB
0x8000 0000 0x4001 0000

0x4000 A7FF
Block 3
APB
0x4000 0000
0x6000 0000

Block 2 0x1FFF FFFF

Reserved
Periphrals 0x1FFF 1000
0x4000 0000 Reserved
0x1FFF 0F80
Factory config. bytes 0x1FFF 0F00
Block 1 Option bytes
0x1FFF 0E80
UID
0x1FFF 0E00
0x2000 0000 RAM System memory
0x1FFF 0000
0x0800 FFFF
Block 0 Code
Main flash
0x0800 0000
0x0000 0000
Main flash/ 0x0000 FFFF
System flash/
Addressable space RAM 0x0000 0000

Figure 4-1 Memory map

Table 4-1 Memory address

Type Boundary Address Size Memory Area Description
0x2000 1 000-0x3FFF FFFF 512 Mbytes Reserved
SRAM Depending on the hardware,
0x2000 0000-0x2000 1FFF 8 Kbytes SRAM
the SRAM is up to 8 kBytes
0x1FFF 1000-0x1FFF FFFF 4 Kbytes Reserved
Code
0x1FFF 0F80-0x1FFF 0FFF 128 Bytes Reserved

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 PY32F003 Datasheet

Type Boundary Address Size Memory Area Description

Store HSI triming data, flash
0x1FFF 0F00-0x1FFF 0F7F 128 Bytes Factory config erasing time configuration
parameters
0x1FFF 0E80-0x1FFF 0EFF 128 Bytes Option bytes Option bytes
0x1FFF 0E00-0x1FFF 0E7F 128 Bytes UID Unique ID
0x1FFF 0000-0x1FFF 0DFF 3.5 Kbytes System memory Store the boot loader
0x0800 8000-0x1FFE FFFF 384 Mbytes Reserved
0x0800 0000-0x0800 FFFF 64 Kbytes Main flash memory
0x0001 0000-0x07FF FFFF 8 Mbytes Reserved
According to the
Boot configuration:
1) Main flash
0x0000 0000-0x0000 FFFF 64 Kbytes memory
2) System memory
3) SRAM
1. Except for 0x1FFF 0E00-0x1FFF 0E7F, the above spaces are marked as reserved spaces, which cannot
be written and read as 0 with response error.

Table 4-2 Peripheral register address

Bus Boundary Address Size Peripheral
0xE000 0000-0xE00F FFFF 1 Mbytes M0+
0x5000 1800-0x5FFF FFFF - Reserved (1)
0x5000 1400-0x5000 17FF 1 Kbytes GPIOF
0x5000 1000-0x5000 13FF - Reserved
IOPORT 0x5000 0C00-0x5000 0FFF - Reserved
0x5000 0C00-0x5000 0FFF - Reserved
0x5000 0400-0x5000 07FF 1 Kbytes GPIOB
0x5000 0000-0x5000 03FF 1 Kbytes GPIOA
0x4002 3400-0x4FFF FFFF - Reserved
0x4002 300C-0x4002 33FF Reserved
1 Kbytes
0x4002 3000-0x4002 3008 CRC
0x4002 2400-0x4002 2FFF - Reserved
0x4002 2124-0x4002 23FF Reserved
1 Kbytes
0x4002 2000-0x4002 2120 Flash
0x4002 1C00-0x4002 1FFF - Reserved
AHB 0x4002 1888-0x4002 1BFF Reserved
1 Kbytes
0x4002 1800-0x4002 1884 EXTI(2)
0x4002 1400-0x4002 17FF - Reserved
0x4002 1064-0x4002 13FF Reserved
1 Kbytes
0x4002 1000-0x4002 1060 RCC(2)
0x4002 0C00-0x4002 0FFF - Reserved
0x4002 0040-0x4002 03FF Reserved
1 Kbytes
0x4002 0000-0x4002 003C DMA

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 PY32F003 Datasheet

Bus Boundary Address Size Peripheral

0x4001 5C00-0x4001 FFFF - Reserved
0x4001 5880-0x4001 5BFF Reserved
1 Kbytes
0x4001 5800-0x4001 587F DBG
0x4001 4C00-0x4001 57FF - Reserved
0x4001 4850-0x4001 4BFF Reserved
1 Kbytes
0x4001 4800-0x4001 484C TIM17
0x4001 4450-0x4001 47FF Reserved
1 Kbytes
0x4001 4400-0x4001 404C TIM16
0x4001 3C00-0x4001 43FF - Reserved
0x4001 381C-0x4001 3BFF Reserved
1 Kbytes
0x4001 3800-0x4001 3018 USART1
0x4001 3400-0x4001 37FF - Reserved
0x4001 3010-0x4001 33FF Reserved
1 Kbytes
0x4001 3000-0x4001 300C SPI1
0x4001 2C50-0x4001 2FFF Reserved
1 Kbytes
0x4001 2C00-0x4001 2C4C TIM1
0x4001 2800-0x4001 2BFF - Reserved
0x4001 270C-0x4001 27FF Reserved
1 Kbytes
0x4001 2400-0x4001 2708 ADC
0x4001 0400-0x4001 23FF - Reserved
APB
0x4001 0220-0x4001 03FF Reserved
0x4001 0200-0x4001 021F 1 Kbytes COMP1 and COMP2
0x4001 0000-0x4001 01FF SYSCFG
0x4000 B400-0x4000 FFFF - Reserved
0x4000 B000-0x4000 B3FF - Reserved
0x4000 8400-0x4000 AFFF - Reserved
0x4000 8000-0x4000 83FF - Reserved
0x4000 7C28-0x4000 7FFF Reserved
1 Kbytes
0x4000 7C00-0x4000 7C24 LPTIM
0x4000 7400-0x4000 7BFF - Reserved
0x4000 7018-0x4000 73FF Reserved
1 Kbytes
0x4000 7000-0x4000 7014 PWR(3)
0x4000 5800-0x4000 6FFF - Reserved
0x4000 5434-0x4000 57FF Reserved
1 Kbytes
0x4000 5400-0x4000 5430 I2C
0x4000 4800-0x4000 53FF - Reserved
0x4000 441C-0x4000 47FF Reserved
1 Kbytes
0x4000 4400-0x4000 4418 USART2
0x4000 3C00-0x4000 43FF - Reserved
0x4000 3800-0x4000 3BFF 1 Kbytes Reserved

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 PY32F003 Datasheet

Bus Boundary Address Size Peripheral

0x4000 3400-0x4000 37FF - Reserved
0x4000 3014-0x4000 33FF Reserved
1 Kbytes
0x4000 3000-0x4000 0010 IWDG
0x4000 2C0C-0x4000 2FFF Reserved
1 Kbytes
0x4000 2C00-0x4000 2C08 WWDG
0x4000 2830-0x4000 2BFF Reserved
1 Kbytes
0x4000 2800-0x4000 282C RTC(3)
0x4000 2400-0x4000 27FF - Reserved
0x4000 2054-0x4000 23FF Reserved
1 Kbytes
0x4000 2000-0x4000 0050 TIM14
0x4000 1800-0x4000 1FFF - Reserved
0x4000 1400-0x4000 17FF - Reserved
0x4000 1000-0x4000 13FF - Reserved
0x4000 0800-0x4000 0FFF - Reserved
0x4000 0450-0x4000 07FF Reserved
1 Kbytes
0x4000 0400-0x4000 044C TIM3
0x4000 0000-0x4000 03FF - Reserved

1. The address space marked as Reserved by AHB in the above table cannot be written, read is 0, and a
hardfault is generated. The address space marked as Reserved by APB cannot be written, read back
as 0, but no hardfault will be generated.

2. Not only supports 32 bits word access, but also supports halfword and byte access.

3. Not only supports 32 bits word access, but also supports halfword access.

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 PY32F003 Datasheet

5. Electrical characteristics
5.1. Test conditions
All voltages are referenced to VSS unless otherwise specified.

5.1.1. Min and Max

Unless otherwise specified, the chip is screened by mass production testing at ambient temperature
TA =25°C and TA =TA(max), guaranteed to reach the minimum value and maximum value under the worst
ambient temperature, supply voltage and clock frequency conditions.

Based on electrical characterization results, design simulations, and/or process parameters noted
below the table, not tested in production. Minimum and maximum values are referenced to sample
testing and averaged plus or minus three times the standard deviation.

5.1.2. Typical value

Unless otherwise specified, typical data is based on TA =25°C and VCC = 3.3 V. These data are for
design guidance only and have not been tested.

Typical ADC accuracy values are obtained by sampling a standard batch, tested under all temperature
ranges, and 95% of the chip error is less than or equal to the given value.

5.2. Absolute maximum ratings

If the applied voltage exceeds the absolute maximum value given in the table below, it may cause
permanent damage to the chip. Only the strength ratings that can be tolerated are listed here, and it
does not imply that the functional operation of the device is correct under these conditions. Operating
under maximum conditions for a long time may affect the reliability of the chip.

Table 5-1 Voltage characteristics (1 )

Symbol Describe Minimum Maximum Unit
VCC External mains power supply -0.3 6.25 V
VIN Input voltage of other pins -0.3 VCC + 0.3 V
1. Power supply VCC and ground VSS pins must always be connected to the external power supply within the
allowable range.

Table 5-2 Current characteristics

Symbol Describe Maximum Unit
IVCC Flowing into VCC pin (supply current) (1) 100
mA
IVSS Total current flowing out of VSS pin (outflow current) (1 ) 100

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 PY32F003 Datasheet

Output sink current of COM IO 20

IIO(PIN)
Source current for all IOs - 20
1. Power supply VCC and ground VSS pins must always be connected to the external power supply within the
allowable range.

Table 5-3 Temperature characteristics

Symbol Describe Condition Value Unit
TSTG Storage temperature range - 65 ~ + 150 ℃
x6 version - 40 ~ + 85
TO Range of operating temperature ℃
x7 version - 40 ~ + 105

5.3. Operating conditions

5.3.1. General operating conditions
Table 5-4 General operating conditions
Symbol Parameter Condition Minimum Maximum Unit
fHCLK Internal AHB clock frequency - 0 32 MHz
fPCLK Internal APB Clock Frequency - 0 32 MHz
x6 version 1.7 5.5
VCC Standard operating voltage V
x7 version 2.0 5.5
VIN IO input voltage - -0.3 VCC+0.3 V
x6 version -40 85
TA Ambient temperature ℃
x7 version -40 105
x6 version -40 90
TJ Junction temperature ℃
x7 version -40 110

5.3.2. Power on and down operating conditions

Table 5-5 Power on and Power down Operating Conditions
Symbol Parameter Condition Minimum Maximum Unit
VCC rise rate - 0 ∞
tVCC us/V
VCC fall rate - 20 ∞

5.3.3. Embedded reset and LVD module features

Table 5-6 Embedded Reset Module Features
Symbol Parameter Condition Minimum Typical Maximum Unit
tRSTTEMPO(1) Reset time - - 4.0 7.5 ms
rising edge 1.5 0 (2) 1.60 1.70 V
VPOR/PDR POR/PDR reset threshold
falling edge 1.45 ( 1 ) 1.55 1.65 (2) V
rising edge 1.70 (2) 1.80 1.90 V
VBOR1 BOR threshold 1
falling edge 1.60 1.70 1.80 (2) V

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 PY32F003 Datasheet

Symbol Parameter Condition Minimum Typical Maximum Unit

rising edge 1.90 (2) 2.00 2.10 V
VBOR2 BOR threshold 2
falling edge 1.80 1.90 2.00 (2) V
rising edge 2.10 (2) 2.20 2.30 V
VBOR3 BOR threshold 3
falling edge 2.00 2.10 2.20 (2) V
rising edge 2.30 (2) 2.40 2.50 V
VBOR4 BOR threshold 4
falling edge 2.20 2.30 2.40 (2) V
rising edge 2.50 (2) 2.60 2.70 V
VBOR5 BOR threshold 5
falling edge 2.40 2.50 2.60 (2) V
rising edge 2.70 (2) 2.80 2.90 V
VBOR6 BOR threshold 6 (2)
falling edge 2.60 2.70 2.80 V
rising edge 2.90 (2) 3.00 3.10 V
VBOR7 BOR threshold 7
falling edge 2.80 2.90 3.00 (2) V
rising edge 3.10 (2) 3.20 3.30 V
VBOR8 BOR threshold 8
falling edge 3.00 3.10 3.20 (2) V
rising edge 1.70 (2) 1.80 1.90 V
VPVD0 PVD threshold 0
falling edge 1.60 1.70 1.80 (2) V
rising edge 1.90 (2) 2.00 2.10 V
VPVD1 PVD Threshold 1
falling edge 1.80 1.90 2.00 (2) V
rising edge 2.10 (2) 2.20 2.30 V
VPVD2 PVD Threshold 2
falling edge 2.00 2.10 2.20 (2) V
rising edge 2.30 (2) 2.40 2.50 V
VPVD3 PVD Threshold 3
falling edge 2.20 2.30 2.40 (2) V
rising edge 2.50 (2) 2.60 2.70 V
VPVD4 PVD Threshold 4
falling edge 2.40 2.50 2.60 (2) V
rising edge 2.70 (2) 2.80 2.90 V
VPVD5 PVD threshold 5
falling edge 2.60 2.70 2.80 (2) V
rising edge 2.90 (2) 3.00 3.10 V
VPVD6 PVD threshold 6
falling edge 2.80 2.90 3.00 (2) V
rising edge 3.10 (2) 3.20 3.30 V
VPVD7 PVD threshold 7
falling edge 3.00 3.10 3.20 (2) V
POR / PDR hysteresis
VPOR_PDR_hyst(1) - - 50 - mV
voltage
VPVD_BOR_hyst(1) PVD hysteresis voltage - - 100 - mV
IDD(PVD) PVD power consumption - - 0.6 - uA
IDD(BOR) BOR power consumption - - 0.6 - uA
1. Guaranteed by design, not tested in production.
2. Data is based on assessment results and is not tested in production.

5.3.4. Operating current characteristics

Table 5-7 Run mode current
Condition
Typical Maxi-
Symbol System Peripheral FLASH (1) Unit
Frequency Code Run mum
clock clock sleep
IDD(run) HSI 24 MHz While Flash ON DISABLE 1.5 - mA

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 PY32F003 Datasheet

Condition
Typical Maxi-
Symbol System Peripheral FLASH (1) Unit
Frequency Code Run mum
clock clock sleep
(1)
OFF DISABLE 0.9 -
ON DISABLE 1.1 -
16 MHz
OFF DISABLE 0.7 -
ON DISABLE 0.7 -
8 MHz
OFF DISABLE 0.5 -
ON DISABLE 0.5 -
4 MHz
OFF DISABLE 0.35 -
ON DISABLE 170 -
32.768 kHz
OFF DISABLE 170 -
LSI uA
ON ENABLE 95 -
32.768 kHz
OFF ENABLE 95 -

1. Data is based on assessment results and is not tested in production.

Table 5-8 Sleep mode current

Condition
Typical
Symbol System Peripheral FLASH (1) Maximum Unit
Frequency
clock clock sleep
ON DISABLE 1 -
24 MHz
OFF DISABLE 0.6 -
ON DISABLE 0.75 -
16 MHz
OFF DISABLE 0.5 -
HSI
ON DISABLE 0.5 - mA
8 MHz
OFF DISABLE 0.35 -
IDD(sleep)
ON DISABLE 0.4 -
4 MHz
OFF DISABLE 0.35 -
ON DISABLE 170 -
32.768 kHz
OFF DISABLE 170 -
LSI
ON ENABLE 95 - uA
32.768 kHz
OFF ENABLE 96 -

1. Data is based on assessment results and is not tested in production.

Table 5-9 Stop mode current

Condition
Typical
Symbol MR/ Peripheral (1) Maximum Unit
VCC VDD LSI
LPR clock
1.2 V MR - - 70 -
RTC+IWDG+LP
6 -
TIM
IDD(stop) VCC=1.7 ~ 5.5 V IWDG 6 - uA
1.2 V LPR ON
LPTIM 6 -
RTC 6 -

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Condition
Typical
Symbol MR/ Peripheral (1) Maximum Unit
VCC VDD LSI
LPR clock
OFF No 6 -
RTC+IWDG+LP
4.5 -
TIM
IWDG 4.5 -
ON
1.0 V LPTIM 4.5 -
RTC 4.5 -
OFF No 4.5 -

1. Data is based on assessment results and is not tested in production.

5.3.5. Low power mode wake-up time

Table 5-10 Low power mode wake-up time
Symbol Parameters(1) Condition Typical(2) maximum Unit
tWUSLEEP Wake-up time from sleep - 1.65 - us
Powered by Execute program in Flash, HSI
3.5 -
Wake-up MR (24 Mhz) as system clock
tWUSTOP time from Execute program in VDD=1.2 V 6 - us
stop Powered by
Flash, HSI as sys-
LPR VDD=1.0 V 6 -
tem clock
1. The wake-up time is measured from the wake-up time until the first instruction is read by the user
program.
2. Data is based on assessment results and is not tested in production.

5.3.6. External clock source characteristics

[Link]. External high-speed clock

In the bypass mode of HSE (the HSEBYP of RCC_CR is set), when the high-speed start-up circuit in
the chip stops working, the corresponding IO is used as a standard GPIO.

Tw(HSEH)
VHSEH
90%

10%
VHSEL

tr(HSE) tf(HSE) t
Tw(HSEL)

THSE

Figure 5-1 External high-speed clock timing diagram

Table 5-11 External high-speed clock features

Symbol Parameters(1) Minimum Typical Maximum Unit
fHSE_ext User external clock frequency 0 8 32 MHz

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Symbol Parameters(1) Minimum Typical Maximum Unit

VHSEH Input pin high level voltage 0.7VCC - VCC
V
VHSEL Input pin low level voltage Vss - 0.3VCC
tW(HSEH)
Enter high or low time 15 - - ns
tW(HSEL)
tr(HSE)
Enter the rise/fall time - - 20 ns
tf(HSE)
1. Guaranteed by design, not tested in production.

[Link]. External high-speed crystal

An external 4~32 MHz crystal/ceramic resonator. In the application, the crystal and load capacitors
should be as close as possible to the pins to minimize output distortion and start-up settling time.

Table 5-12 External high-speed crystal characteristics

Symbol Parameter Condition(1) Minimum(2) Typical Maximum(2) Unit
fOSC_IN Oscillation frequency - 4 - 32 MHz
During startup - - 5.5
VCC=3 V, Rm=30 ꭥ,
- 0.58 -
CL=10 pF@8 MHz
VCC=3 V,Rm=45ꭥ,
- 0.59 -
CL=10 pF@8 MHz
HSE power con-
IDD(4) VCC=3 V,Rm=30ꭥ, mA
sumption - 0.89 -
CL=5 pF@32MHz
VCC=3 V,Rm=30ꭥ,
- 1.10 -
CL=10 pF@32 MHz
VCC=3 V,Rm=30ꭥ,
- 1.90 -
CL=20 pF@32 MHz
tSU (HSE) fOSC_IN=32 MHz - 3 -
(3) (4)
Start Time ms
fOSC_IN=4 MHz - 15 -
1. Crystal/ceramic resonator characteristics are based on the manufacturer datasheet.

2. Guaranteed by design, not tested in production.

3. tSU(HSE) is the start-up time from enable (by software) to the clock oscillation reaches stability, measured for
a standard crystal/resonator, which can vary greatly from one crystal/resonator to another .

4. Data is based on assessment results and is not tested in production.

5.3.7. Internal high frequency clock source HSI characteristics

Table 5-13 Internal high frequency clock source characteristics
Symbol Parameter Condition Minimum Typical Maximum Unit
23.83(2) 24 24.17(2)
21.97(2) 22.12 22.27(2)
fHSI HSI frequency TA=25°C,VCC=3.3 V MHz
15.89(2) 16 16.11(2)
7.94(2) 8 8.06(2)

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Symbol Parameter Condition Minimum Typical Maximum Unit

3.97(2) 4 4.03(2)
TA=0 ~ 85°C -2(2) - 2(2)
HSI frequency temperature
ΔTemp(HSI) TA=-40 ~ 85°C -4(2) - 2(2) %
drift
TA=-40 ~ 105°C -4(2) - 2.5(2)
fTRIM(1) HSI fine-tuning accuracy - - 0.1 - %
DHSI(1) Duty cycle - 45(1) 55(1) %
tStab(HSI) HSI stabilization time - - 2 4(1) us
4 MHz - 100 -
8 MHz - 105 -
IDD(HSI) (2) HSI power consumption uA
16 MHz - 150 -
22.12 MHz, 24 MHz - 180 -
1. Guaranteed by design, not tested in production.

2. Data is based on assessment results and is not tested in production.

5.3.8. Internal low frequency clock source LSI characteristics

Table 5-14 Internal low frequency clock characteristics
Symbol Parameter Condition Minimum Typical Maximum Unit
fLSI LSI frequency TA=25°C,VCC=3.3V -1 - +1 %

LSI frequency tempera- TA=0 ~ 70°C -10(2) - 10(2)

ΔTemp(LSI) %
ture drift TA=-40 ~ 105°C -20(2) - 20(2)
fTRIM(1) LSI fine-tuning accuracy - - 0.2 - %
tStab(LSI) (1) LSI stabilization time - - 150 - us
IDD(LSI) (1) LSI power consumption - - 210 - nA
1. Guaranteed by design, not tested in production.

2. Data is based on assessment results and is not tested in production.

5.3.9. Memory characteristics

Table 5-15 Memory characteristics
Symbol Parameter Condition Typical Maximum(1) Unit
tprog Page program - 1.0 1.5 ms
tERASE Page/sector/mass erase - 3.0 4.5 ms
Page programe - 2.1 2.9
IDD mA
Page/sector/mass erase - 2.1 2.9
1. Guaranteed by design, not tested in production.

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Table 5-16 Memory erase times and data retention

Symbol Parameter Condition Minimum(1) Unit
TA = -40 ~ 105℃ 100
NEND Erase and write times kcycle
TA = 85 ~ 105℃ 10

tRET Data retention period 10 kcycle TA = 55℃ 20 Year

1. Data is based on assessment results and is not tested in production.

5.3.10. EFT characteristics

Table 5-17 EFT characteristics
Symbol Parameter Condition Grade Typical Unit
EFT to Power - IEC61000-4-4 A 4 KV

5.3.11. ESD & LU Characteristics

Table 5-18 ESD & LU characteristics
Symbol Parameter Condition Typical Unit
VESD(HBM) Static Discharge Voltage (human body model) ESDA/JEDEC JS-001-2017 6 KV
Static Discharge Voltage (charging equipment
VESD(CDM) ESDA/JEDEC JS-002-2018 1 KV
model)
VESD(MM) Static discharge voltage (machine model) JESD22-A115C 200 V
LU Static Latch-Up JESD78E 200 mA

5.3.12. Port characteristics

Table 5-19 IO static characteristics
Symbol Parameter Condition Minimum Typical Maximum Unit
VIH Input high level voltage TA = -40 ~105℃ 0.7VCC - - V

VIL Input low level voltage TA = -40 ~105℃ - - 0.3VCC V

Vhys(1) Schmitt hysteresis voltage - - 200 - mV
Ilkg Input leakage current - - 1 uA
RPU Pull-up resistor - 30 50 70 kꭥ
RPD Pull-down resistor - 30 50 70 kꭥ
CIO(1) Pin capacitance - - 5 - pF

1. Guaranteed by design, not tested in production.

Table 5-20 Output Voltage Characteristics

symbol Parameters (1) condition Minimum Maximum unit
IOL = 8 mA, VCC ≥ 2.7 V - 0.4
VOL COM IO output low level V
IOL = 4 mA, VCC = 1.8 V - 0.5
IOH = 8 mA, VCC ≥ 2.7 V VCC–0.4 -
VOH COM IO output high level V
IOH = 4 mA, VCC = 1.8 V VCC–0.5 -

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1. IO types can refer to the terms and symbols defined by the pins.

5.3.13. NRST pin characteristics

Table 5-21 NRST pin characteristics
Symbol Parameter Condition Minimum Typical Maximum Unit
VIH Input high level voltage TA = -40 ~105℃ 0.7VCC - - V

VIL Input low level voltage TA = -40 ~105℃ - - 0.2VCC V

Vhys(1) Schmitt hysteresis voltage - - 300 - mV
Ilkg Input leakage current - - - 1 uA
（1）
RPU Pull-up resistor - 30 50 70 kꭥ
（1）
RPD Pull-down resistor - 30 50 70 kꭥ
CIO Pin capacitance - - 5 - pF

1. Guaranteed by design, not tested in production.

5.3.14. ADC characteristics

Table 5-22 ADC characteristics
Symbol Parameter Condition Minimum Typical Maximum Unit
IDD Power consumption @0.75 MSPS - 1.0 - mA
Internal sample and hold capac-
CIN(1) - - 5 - pF
itors
VCC=1.7~2.3 V 1 4 6(2)
FADC Convert clock frequency MHz
VCC=2.3~5.5 V 1 8 12(2)
- VCC=1.7~2.3 V 0.2 - -
tsamp(1) us
- VCC=2.3~5.5 V 0.1 - -
tconv(1) - - - 12*Tclk -
teoc (1) - - - 0.5*Tclk -
DNL(2) - - - ±2 - LSB
INL(2) - - - ±3 - LSB
Offset(2) - - - ±2 - LSB
1. Guaranteed by design, not tested in production.

2. Data is based on assessment results and is not tested in production.

5.3.15. Comparator characteristics

Table 5-23 Comparator characteristics (1)
Symbol Parameter Condition Minimum Typical Maximum Unit
Input voltage
VIN - 0 - VCC V
range
Scale input volt-
VBG - VREFINT V
age

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Symbol Parameter Condition Minimum Typical Maximum Unit

Scaler offset volt-
VSC - - ±5 ±10 mV
age
Scaler static con- BRG_EN=0(bridge disable) - 200 300 nA
IDD(SCALER)
sumption BRG_EN=1(bridge enable) - 0.8 1 uA
Scaler startup
tSTART_SCALER - - 100 200 us
time
Startup time to High-speed mode - - 5
reach propaga-
tSTART us
tion delay specifi- Medium-speed mode - - 15
cation
200 mV High-speed
- 30 50 ns
step; mode
100 mV Medium-
- 0.3 0.6 us
Propagation de- overdrive speed mode
tD
lay >200 mV High-speed
- - 10 us
step;100 mode
mV over- Medium-
drive - - 1.2 ns
speed mode
Voffset Offset error - - ±5 - mV
No hysteresis - 0 -
Low hysteresis - 10 -
Vhys Hysteresis mV
Medium hysteresis - 20 -
High hysteresis - 30 -
Static - 5 - uA
Medium-
speed With 50 kHz
mode; No and ±100 mv
- 6 - uA
deglitcher overdrive
square signal
Static - 7 - uA
Medium-
speed With 50 kHz
IDD Consumption and ±100 mv
mode With - 8 - uA
deglitcher overdrive
square signal
Static - 250 - uA
High-speed With 50 kHz
mode; No and ±100 mv
deglitcher - 250 - uA
overdrive
square signal
1. Guaranteed by design, not tested in production.

5.3.16. Temperature sensor characteristics

Table 5-24 Temperature sensor characteristics
Symbol Parameter Minimum Typical Maximum Unit
TL(1) VTS linearity with temperature - ±1 ±2 ℃
Avg_Slope(1) Average slope 2.3 2.5 2.7 mV/℃
V30 Voltage at 30℃(±5℃) 0.742 0.76 0.785 V

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 PY32F003 Datasheet

Symbol Parameter Minimum Typical Maximum Unit

tSTART(1) Start-up time entering in continuous mode - 70 120 us
ADC sampling time when reading the tem-
tS_temp(1) 9 - - us
perature
1. Guaranteed by design, not tested in production.

5.3.17. Internal reference voltage characteristics

Table 5-25 Internal reference voltage characteristics

Symbol Parameter Minimum Typical Maximum Unit

VREFINT Internal reference voltage 1.17 1.2 1.23 V
tstart_vrefint Start time of internal reference voltage - 10 15 us
Tcoeff Temperature coefficient - - 100(1) ppm/℃
Ivcc Current consumption from VCC - 12 20 uA

5.3.18. Timer characteristics

Table 5-26 Timer characteristics
Symbol Parameter Condition Minimum Maximum Unit
- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 32 MHz 20.833 - ns
Timer external clock - - fTIMxCLK/2
fEXT frequency on CH1 to MHz
CH4 fTIMxCLK = 32 MHz - 24
ResTIM Timer resolution TIM1/3/14/16/17 - 16 Bit

16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 32 MHz 0.020833 1365 us

Table 5-27LPTIM characteristics (clock selection LSI)

Prescaler PRESC[2:0] Minimum overflow Maximum overflow Unit
/1 0 0.0305 1998.848
/2 1 0.0610 3997.696
/4 2 0.1221 8001.9456
/8 3 0.2441 15997.3376
ms
/16 4 0.4883 32001.2288
/32 5 0.9766 64002.4576
/64 6 1.9531 127998.3616
/128 7 3.9063 256003.2768

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Table 5-28IWDG characteristics (clock selection LSI)

Prescaler PR[2:0] Minimum overflow Maximum overflow Unit
/4 0 0.122 499.712
/8 1 0.244 999.424
/16 2 0.488 1998.848
/32 3 0.976 3997.696 ms
/64 4 1.952 7995.392
/128 5 3.904 15990.784
/256 6 or 7 7.808 31981.568

Table 5-29 WWDG characteristics (clock select 32 MHz PCLK)

Prescaler WDGTB[1:0] Minimum overflow Maximum overflow value Unit
1*4096 0 0.085 5.461
2*4096 1 0.171 10.923
ms
4*4096 2 0.341 21.845
8*4096 3 0.683 43.691

5.3.19. Communication port characteristics

[Link]. I2C bus interface features

I2C interface meets the requirements of the I2C -bus specification and user manual :
 Standard-mode(Sm): 100 kbit/s
 Fast-mode(Fm): 400 kbit/s

Timing is guaranteed by design, provided the I2C peripheral is properly configured and the I2C CLK
frequency is greater than the minimum required in the table below.

Table 5-30 Minimum I2C CLK frequency

Symbol Parameter Condition Minimum Unit
Standard-mode 2
fI2CCLK(min) Minimum I2C CLK freq uency MHz
Fast-mode 9
I2C SDA and SCL pins have analog filtering, see table below.

Table 5-31 I2C filter characteristics

Symbol Parameter Minimum Maximum Unit
Limiting duration of spikes suppressed by the filter (Spik-
tAF 50 260 ns
ers shorter than the limiting duration are suppressed)

[Link]. Serial Peripheral Interface SPI Characteristics

Table 5-32 SPI characteristics

Symbol Parameter Condition Minimum Maximum Unit
fSCK Master mode - 12 MHz

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Symbol Parameter Condition Minimum Maximum Unit

1/tc(SCK) SPI clock fre-
Slave mode - 12
quency
tr(SCK) SPI clock rise
Capacitive load: C=15 pF - 6 ns
tf(SCK) and fall time
tsu(NSS) NSS setup time Slave mode 4Tpclk - ns
th(NSS) NSS hold time Slave mode 2Tpclk + 10 - ns
tw(SCKH) SCK high and
Master mode,presc = 4 Tpclk*2 -2 Tpclk*2 + 1 ns
tw(SCKL) low time
tsu(MI) Data input setup Master mode,presc = 4 Tpclk+5(1) -
tsu(SI) ns
time Slave mode, presc = 4 5 -
th(MI)
Data input hold Master mode 5 -
ns
th(SI) time
Slave mode Tpclk+5 -

ta(SO) Data output ac-

Slave mode, presc = 4 0 3Tpclk ns
cess time
tdis(SO) Data output dis-
Slave mode 2Tpclk+5 4Tpclk+5 ns
able time
Data output Slave mode (after enable
tv(SO) 0 1.5Tpclk(2) ns
valid ime edge)，presc = 4
tv(MO) Data output Master mode (after enable
- 6 ns
valid ime edge)
th(SO)
Data output Slave mode，presc = 4 0(3) -
ns
th(MO) hold time
Master mode 2 -

DuCy(SCK) SPI slave input

Slave mode 45 55 %
clock duty cycle
1. The Master generates 1 pclk to receive control signal before the receive edge.

2. Slave has a maximum of 1 PCLK based on the sending edge of SCK delay, considering IO delay, etc.,
define 1.5 PCLK.

3. In the case that the SCK duty cycle sent by the Master is wide between the receiving edge and the send-
ing edge, the Slave updates the data before the sending edge.

NSS input
Th(NSS)
Tc(SCK)
Tr(SCK)
Tsu(NSS) Tw(SCKH)
CPHA=0
CPOL=0
SCK input

CPHA=0
CPOL=1
Ta(SO) Th(SO) Tf(SCK) Tdis(SO)
Tw(SCKL) Tv(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

Th(SI)

Tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

Figure 5-2 SPI timing diagram – slave mode and CPHA=0

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 PY32F003 Datasheet

NSS input
Tc(SCK) Th(NSS)
Tf(SCK)
Tsu(NSS) Tw(SCKH)
CPHA=1
CPOL=0
SCK input

CPHA=1
CPOL=1
Ta(SO) Tr(SCK) Tdis(SO)
Tw(SCKL) Tv(SO) Th(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

Tsu(SI) Th(SI)

MOSI input First bit IN Next bits IN Last bit IN

Figure 5-3 SPI timing diagram – slave mode and CPHA=1

NSS input

Tc(SCK)

CPHA=0
CPOL=0
SCK input

CPHA=0
CPOL=1

CPHA=1
CPOL=0
SCK input

CPHA=1
CPOL=1
Tw(SCKH)
Tsu(MI)
Tw(SCKL)

MISO input MSB IN BIT6 IN LSB IN

Th(MI)

MOSI output MSB OUT BIT1 OUT LSB OUT

Tv(MO) Th(MO)

Figure 5-4 SPI timing diagram – master mode

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6. Package information
6.1. QFN20

TOP VIEW SIDE VIEW

D
20
Pin1
1

2 E
A
A1
c

BOTTOM VIEW
Common Dimensions
(Unit of Measure=millimeters)
L

Symbol Min Typ Max

Nd A 0.500 0.550 0.600
A1 0.000 0.020 0.050
b 0.150 0.200 0.250
b1 0.140REF
D2 c 0.150REF

D 2.900 3.000 3.100

Ne

E2

D2 1.550 1.650 1.750

2
h E 2.900 3.000 3.100
h

b1

1 E2 1.550 1.650 1.750

e 0.400BSC
Nd 1.600BSC
20
e b Ne 1.600BSC
L 0.350 0.400 0.450
h 0.200 0.250 0.300

Note：1. Dimensions are not to scale

TITLE DRAWING NO. REV

Puya QFN20L 3x3X0.55-0.4PITCH POD QRPD-0041 1.0

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6.2. TSSOP20

20
E1

C
E

A1
L

α
L1

Common Dimensions
(Unit of Measure=millimeters)
Symbol Min Typ Max
A - - 1.200
A2
A

D A1 0.050 - 0.150

A2 0.800 1.000 1.050

b 0.200 - 0.280
e c 0.090 - 0.200
b
A1

D 6.400 6.500 6.600

E 6.200 6.400 6.600
E1 4.300 4.400 4.500
e 0.650BSC
L 0.450 0.600 0.750
L1 1.000REF
θ 0 - 8°

Note：1. Dimensions are not to scale

TITLE DRAWING NO. REV

Puya TSSOP20 POD QRPD-0043 1.0

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6.3. SOP20

20
E
E1

C
1

A1
L

α
L1

Common Dimensions
(Unit of Measure=millimeters)

Symbol Min Typ Max

A2

A 2.650
A

D 0.100 0.300
A1
A2 2.100 2.300 2.500
b 0.330 0.510
e b 0.200 0.330
c
A1

D 12.600 12.800 13.000

E 10.100 10.300 10.500
E1 7.400 7.500 7.600
e 1.275BSC
h 0.300 0.500
L 0.400 1.270
L1 1.400REF

θ 0 8°

Note：1. Dimensions are not to scale

TITLE DRAWING NO. REV

Puya SOP20 POD QRPD-0048 1.0

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6.4. SOP16

b e

16

E1

E
1

A2
A
A1
h
Common Dimensions
(Unit of Measure=millimeters)

Symbol Min Typ Max

A - - 1.75
A1 0.10 - 0.25
c

A2 1.30 - -
b 0.31 - 0.51

c 0.10 - 0.25
D 9.80 - 10.20
E 5.80 - 6.20
E1 3.80 - 4.20
θ
e 1.27BSC
L 0.40 - 1.27
L L1 1.05REF
L1 θ 0 - 8°
h 0.25 - 0.50

Note： Dimensions are not to scale.

TITLE DRAWING NO. REV

PUYA SOP16 (150mil) POD QRPD-0001 1.1

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6.5. MSOP10

10
E1

C
1

A1
L

θ
b e

L1

Common Dimensions
(Unit of Measure=millimeters)
Symbol Min Typ Max
D
A 1.100
A1 0.050 0.150

A2 0.750 0.850 0.950

A2
A

b 0.180 0.270

c 0.150 0.200
D 2.900 3.000 3.100
4.700 4.900 5.100
A1

E
E1 2.900 3.000 3.100
e 0.500
L 0.400 0.700
L1 0.950

θ 0 8°

Note：1. Dimensions are not to scale

TITLE DRAWING NO. REV

Puya MSOP10 POD QRPD-0049 1.0

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6.6. SOP8

E1

C
h
1

A1
b L

θ
L1

Common Dimensions
(Unit of Measure=millimeters)
Symbol Min Typ Max
D
A 1.350 1.750
A1 0.100 0.250

A2 1.250
A2
A

b 0.310 0.510

c 0.170 0.250
D 4.800 4.900 5.000
A1

E 5.800 6.000 6.200

E1 3.800 3.900 4.000
e 1.270
L 0.400 1.270
L1 1.050

θ 0 8°
h 0.25 0.50

Note：1. Dimensions are not to scale

TITLE DRAWING NO. REV

Puya SOP8（150mil）POD QRPD-0004 1.1

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6.7. DFN8(3*2)

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7. Ordering Information
Example:
PY 32 F 003 F1 6 T 6 x - X
Company
Product family
®
ARM based 32-bit microcontroller
Product type
F = General purpose
Sub-family
003 = PY32F003xx
Pin count
F1 = 20 pins Pinout1
F2 = 20 pins Pinout2
F3 = 20 pins Pinout3
F4 = 20 pins Pinout4
F5 = 20 pins Pinout5
F6 = 20 pins Pinout6
W1 = 16 pins Pinout1
A1 = 10 pins Pinout1
L1 = 8 pins Pinout1
L2 = 8 pins Pinout2
User code memory size
8 = 64 Kbytes
7 = 48 Kbytes
6 = 32 Kbytes
4 = 16 Kbytes
Package
U = QFN
P = TSSOP
S = SOP
N = MSOP
D = DFN
Temperature range
6 = -40 to +85
7 = -40 to +105
Options
xxx = code ID of programmed parts(includes packing type)
TR = tape and reel packing
TU = Tube Packing
blank = tray packing

Delimiter character

Version
X = Version X

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8. Version history
Version Date Description
V1.0 2022-01-14 Initial version
1. Updated Table 2-1
V1.1 2022-01-18
2. Updated Table 6-15
V1.2 2022-01-24 1. Updated parameters in Table 6-30
V1.3 2023-01-24 1. Updated the format
V1.4 2024-02-06 1. Add SOP20/SOP16/MSOP10/DFN8(3*2) /SOP8 packages
V1.5 2024-02-23 1. Add PY32F003F16U6-E(QFN20 package)
V1.6 2024-03-13 1. Add PY32F003F16P6-E/PY32F003F18U7-E
V1.7 2024-05-16 1. Add PY32F003F68P7-E (TSSOP20 package)

Puya Semiconductor Co., Ltd.

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bility when products that are used on its own or designated third party products.

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Puya Semiconductor Co., Ltd. – All rights reserved

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