STA505

40V 3.5A QUAD POWER HALF BRIDGE

1 FEATURES Figure 1. Package

■ MULTIPOWER BCD TECHNOLOGY
■ MINIMUM INPUT OUTPUT PULSE WIDTH

■
DISTORTION
200mΩ RdsON COMPLEMENTARY DMOS
PowerSO36

( s )
■
OUTPUT STAGE
CMOS COMPATIBLE LOGIC INPUTS
Table 1. Order Codes
u ct
■ THERMAL PROTECTION
Part Number

o d
Package

■ THERMAL WARNING OUTPUT

STA505
STA50513TR
P r PowerSO36
in Tape & Reel
■ UNDER VOLTAGE PROTECTION
current capability.
e t e
2 DESCRIPTION
o l
The device is particularly designed to make the out-
STA505 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as b s
put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 50 + 50W @
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
- O
THD = 10% at Vcc 30V output power on 8Ω load and
80W @ THD = 10% at Vcc 36V on 8Ω load in single
capability, and as half bridge (Binary mode) with half
(s ) BTL configuration. The input pins have threshold pro-
portional to VL pin voltage.

Figure 2. Audio Application Circuit (Dual BTL)Pin Description c t

d u
r o 15
VCC1A +VCC

P
IN1A 29 M3 C30 C55
IN1A 1µF 1000µF
17 L18 22µH
VL 23

e
+3.3V OUT1A

t
CONFIG 24 16 C20
100nF
OUT1A

e PWRDN PWRDN 25 M2 C52

l 14 GND1A 330pF R98 C99

PROTECTIONS 6 100nF

o
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC

bs
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1µF
C21

O
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22µH
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1µF
100nF 100nF VCCSIGN 8 L113 22µH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1µF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22µH
GNDSUB M14
1 5 GND2B

D00AU1148B

Rev. 11
February 2006 1/10
STA505

Table 2. Pin Function

N° Pin Description

1 GND-SUB Substrate ground

2;3 OUT2B Output half bridge 2B

4 Vcc2B Positive Supply

5 GND2B Negative Supply

6 GND2A Negative Supply

7 Vcc2A Positive Supply

8;9 OUT2A Output half bridge 2A

( s )
10 ; 11 OUT1B Output half bridge 1B

uct
12 Vcc1B Positive Supply

o d
13

14
GND1B

GND1A
Negative Supply

Negative Supply P r
15 Vcc1A Positive Supply
e te
o l
16 ; 17

18
OUT1A

NC
Output half bridge 1A

Not connected
b s
19 GND-clean Logical ground
- O
20 GND-Reg Ground for regulator Vdd
(s )
21 ; 22 Vdd
c t
5V Regulator referred to ground

23 VL
d u
High logical state setting voltage

24 CONFIG
r o
Configuration pin

29 IN1A P
Input of half bridge 1A
e
25
l
PWRDN
e t Stand-by pin

26
s o
TRI-STATE Hi-Z pin

27

28 O b FAULT

TH-WAR
Fault pin advisor

Thermal warning advisor

29 IN1A Input of half bridge 1A

30 IN1B Input of half bridge 1B

31 IN2A Input of half bridge 2A

32 IN2B Input of half bridge 2B

33 ; 34 Vss 5V Regulator referred to +Vcc

35 ; 36 Vcc Sign Signal Positive Supply

2/10
 STA505

Table 3. Functional Pin Status

PIN NAME Logical value IC -STATUS

FAULT 0 Fault detected (Short circuit, or Thermal ..)

FAULT (*) 1 Normal Operation

TRI-STATE 0 All powers in Hi-Z state

TRI-STATE 1 Normal operation

PWRDN 0 Low absorpion

PWRDN 1 Normal operation

THWAR 0 Temperature of the IC =130C

( s )
THWAR(*) 1 Normal operation
u ct
CONFIG 0 Normal Operation
o d
CONFIG(**) 1
P r
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)

e
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
t e
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)

o l
Figure 3. Pin Connection
b s
- O
VCCSign 36
(s ) 1 GND-SUB
VCCSign 35
c t 2 OUT2B
VSS

d
34
u 3 OUT2B
VSS

r o 33 4 VCC2B

PIN2B 32 5 GND2B

e
IN2A 31 6 GND2A

l e t IN1B 30 7 VCC2A

o IN1A 29 8 OUT2A

bs
TH_WAR 28 9 OUT2A
FAULT 27 10 OUT1B

O TRI-STATE
PWRDN
26
25
11
12
OUT1B
VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
GND-Clean 19 18 N.C.

D01AU1273

3/10
STA505

Table 4. Absolute Maximum Ratings

Symbol Parameter Value Unit

VCC DC Supply Voltage (Pin 4,7,12,15) 40 V

Vmax Maximum Voltage on pins 23 to 32 5.5 V

Top Operating Temperature Range -40 to 90 °C

Tstg, Tj Storage and Junction Temperature -40 to 150 °C

Table 5. Thermal Data

Symbol Parameter Min. Typ. Max. Unit

( s )
ct
Tj-case Thermal Resistance Junction to Case (thermal pad) 2.5 °C/W

du
TjSD Thermal shut-down junction temperature 150 °C
Twarn Thermal warning temperature 130 °C
thSD Thermal shut-down hysteresis 25
r o °C

e P
t
Table 6. Electrical Characteristcs (VL = 3.3V; Vcc = 30V; Tamb = 25°C; fsw = 384Khz; unless otherwise

e
ol
specified)

bs
Symbol Parameter Test conditions Min. Typ. Max. Unit

RdsON Power Pchannel/Nchannel

MOSFET RdsON
Id=1A;

- O 200 270 mΩ

Idss Power Pchannel/Nchannel

leakage Idss
Vcc=35V

( s ) 50 µA

gN Power Pchannel RdsON Matching Id=1A

c t 95 %

d u
gP Power Nchannel RdsON
Matching
r o Id=1A 95 %

Dt_s

e P
Low current Dead Time (static) see test circuit no.1; see fig. 1 10 20 ns

Dt_d
l e t
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω
Id=3.5A; see fig. 3
50 ns

o
bs
td ON Turn-on delay time Resistive load 100 ns

td OFF
O
tr
Turn-off delay time

Rise time
Resistive load

Resistive load; as fig.1;

100

25
ns

ns

tf Fall time Resistive load; as fig. 1; 25 ns

VCC Supply voltage operating voltage 10 36 V

VIN-High High level input voltage VL/2 V

+300mV

VIN-Low Low level input voltage VL/2 - V

300mV

IIN-H High level Input current Pin voltage = VL 1 µA

IIN-L Low level input current Pin voltage = 0.3V 1 µA

4/10
 STA505

Symbol Parameter Test conditions Min. Typ. Max. Unit

IPWRDN-H High level PWRDN pin input 35 µA

current

VLow Low logical state voltage VLow VL = 3.3V 0.8 V

(pin PWRDN, TRISTATE) (note 1)

VHigh High logical state voltage VHigh VL = 3.3V 1.7 V

(pin PWRDN, TRISTATE) (note 1)

IVCC- Supply current from Vcc in Power PWRDN = 0 3 mA

PWRDN Down

IFAULT Output Current pins

FAULT -TH-WARN when Vpin = 3.3V 1 mA

( s )
ct
FAULT CONDITIONS

du
IVCC-hiz Supply current from Vcc in Tri- Tri-state=0 22 mA
state

IVCC Supply current from Vcc in Input pulse width = 50% Duty; 50
r o mA
operation
both channel switching)
Switching Frequency = 384KHz;
No LC filters;
e P
e t
ol
IVCC-q Isc (short circuit current limit) 3.5 6 8 A
(note 2)

VUV Undervoltage protection threshold

b s 7 V

tpw-min Output minimum pulse width No Load

- O 70 150 ns

Table 7.
(s )
c t
Notes: 1. The following table explains the VLow, VHigh variation with VL

VL VLow min VHigh max

d uUnit

2.7 0.7 1.5

r o V

3.3 0.8

e P 1.7 V

5
l e t
0.85 1.85 V

s o
O b
Note 2: See relevant Application Note AN1994

Table 8. Logic Truth Table (see fig. 5)

OUTPUT
TRI-STATE INxA INxB Q1 Q2 Q3 Q4
MODE

0 x x OFF OFF OFF OFF Hi-Z

1 0 0 OFF OFF ON ON DUMP

1 0 1 OFF ON ON OFF NEGATIVE

1 1 0 ON OFF OFF ON POSITIVE

1 1 1 ON ON OFF OFF Not used

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STA505

Figure 4. Test Circuit.

OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

Duty cycle = 50% DTr DTf

t

( s )
M58
OUTxY R 8Ω
u ct
INxY

o d
M57 +
-
V67 =

P
vdc = Vcc/2
r
gnd

e t e
D03AU1458

o l
Figure 5.
b s
-
+VCC O
(s )
c t
u
Q1 Q2

od
OUTxA OUTxB
INxA INxB

P r Q3 Q4

e
let
GND
D00AU1134

Figure 6.
s o
O b High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

Duty cycle=A Duty cycle=B

DTout(A)

M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTxA Rload=8Ω OUTxB
INxA INxB
L67 22µ L68 22µ
Iout=4.5A Iout=4.5A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D00AU1162A

6/10
 STA505

Figure 7. Typical Single BTL Configuration to Obtain 80W @ THD 10%, RL = 8Ω, VCC = 36V (note 1)

VL
+3.3V 23 18 N.C.
100nF 22µH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 8Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
22µH
10K FAULT
27
26
15
VCC1A
+36V

( s )
ct
TRI-STATE 1µF 2200µF
100nF X7R 63V
IN1A VCC1B
29 12
IN1A
IN1B
IN2A
30
31 7
VCC2A
+36V
d u
IN1B
IN2B
32 1µF
X7R
r o
P
VSS VCC2B
33 4
VSS
GND1A

e
34

t
100nF 14
X7R VCCSIGN GND1B

100nF VCCSIGN
35 13

GND2A

o l e
s
X7R 36 6

b
Add. GNDSUB GND2B
1 5

O
D01AU1274

) -
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board".

Figure 8. Typical Quad Half Bridge Configuration

c t(s
u VCC1P +VCC

od
15
IN1A 29 M3 R61 C21
IN1A 5K C31 820µF 2200µF
17 L11 22µH

Pr
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1µF
14 PGND1P R51 C81 R62

e
PROTECTIONS C41 100nF
6 5K

t
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N

C58
100nF

l e TRI-STATE
M5
11
C51
1µF
C61
100nF

so
R63
TH_WAR 28 OUTNL 5K C32 820µF
TH_WAR 10 L12 22µH

b
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4Ω

O
1µF
VDD 22 R52 C82 R64
C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34
M17 R65
C58 C53 C33 820µF
L13 22µH 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1µF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1µF 100nF
R67
OUTNR 5K C34 820µF
IN2B 2 L14 22µH
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1µF
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474

For more information refer to the application notes AN1456 and AN1661

7/10
STA505

Figure 9. Power SO36 (Slug up) Mechanical Data & Package Dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.25 3.43 0.128 0.135 MECHANICAL DATA
A2 3.1 3.2 0.122 0.126
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a1 0.030 -0.040 0.0011 -0.0015
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039

( s )
ct
E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2
E3 5.8
2.9
6.2 0.228
0.114
0.244
d u
E4 2.9 3.2 0.114 1.259
r o
e
e3
0.65
11.05
0.026
0.435

e P
G
H
0
15.5
0.075
15.9
0
0.61
0.003
0.625
l e t
h
L 0.8
1.1
1.1 0.031
0.043
0.043
so
N
s
10˚
8˚
10˚
8˚
O b
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
) -
(s
(2) No intrusion allowed inwards the leads.

c t
d u
r o
e P
l e t
s o
O b

7183931 D

8/10
 STA505

Table 9. Revision History

Date Revision Description of Changes

December 2003 8 First Issue in EDOCS DMS

June 2004 9 Note 2: See relevant Application Note AN1994

November 2004 10 Changed Vcc in Electrical Characteristics from 9 min to 10 min

February 2006 11 Changed Top value on Table 4.

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
du
r o
e P
l e t
s o
O b

9/10
STA505

( s )
u ct
o d
P r
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e t e
o l
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b s
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- O
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r o
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l t
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