a Dual Bootstrapped

MOSFET Driver
ADP3417
FEATURES FUNCTIONAL BLOCK DIAGRAM
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive VCC BST

One PWM Signal Generates Both Drives

Anticross-Conduction Protection Circuitry
APPLICATIONS
IN DRVH
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters OVERLAP
Standard-to-Synchronous Converter Adaptations PROTECTION
CIRCUIT SW

DRVL

ADP3417

PGND

GENERAL DESCRIPTION 12V

The ADP3417 is a dual MOSFET driver optimized for driving

VCC
two N-channel MOSFETs which are the two switches in a
D1
nonisolated synchronous buck power converter. Each of the
BST
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can ADP3417
CBST
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers. DRVH
IN Q1
The ADP3417 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
SW
The ADP3417 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
DELAY TO
INDUCTOR

1V DRVL
Q2

PGND
1V

Figure 1. General Application Circuit

REV. 0
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may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 [Link]
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADP3417–SPECIFICATIONS1 (VCC = 12 V, BST = 4 V to 26 V, TA = 0
C to 70
C, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY
Supply Voltage Range VCC 4.15 13.2 V
Quiescent Current ISYS VCC = BST = 12 V, IN = 0 V 5 7 mA
PWM INPUT
Input Voltage High2 2.5 V
Input Voltage Low2 0.8 V
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current VBST – VSW = 12 V 1.75 3.0 Ω
Output Resistance, Sinking Current VBST – VSW = 12 V 1.0 2.5 Ω
Transition Times3 trdrvh See Figure 2, VBST – VSW = 12 V, 45 55 ns
CLOAD = 3 nF
Transition Times3 tfdrvh See Figure 2, VBST – VSW = 12 V, 20 30 ns
CLOAD = 3 nF
Propagation Delay3, 4 tpdhdrvh See Figure 2, VBST – VSW = 12 V, 45 65 ns
tpdldrvh VBST – VSW = 12 V 15 35 ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current VCC = 12 V 1.75 3.0 Ω
Output Resistance, Sinking Current VCC = 12 V 1.0 2.5 Ω
Transition Times3 trdrvh See Figure 2, VCC = 12 V, 25 35 ns
CLOAD = 3 nF
tfdrvh See Figure 2, VCC = 12 V, 21 30 ns
CLOAD = 3 nF
Propagation Delay3, 4 (See Figure 2) tpdhdrvh See Figure 2, VCC = 12 V 30 60 ns
tpdldrvh See Figure 2, VCC = 12 V 10 20 ns
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3
AC specifications are guaranteed by characterization, but not production tested.
4
For propagation delays, “t pdh” refers to the specified signal going high; “t pdl” refers to it going low.
Specifications subject to change without notice.

–2– REV. 0
 ADP3417
ABSOLUTE MAXIMUM RATINGS * ORDERING GUIDE
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V Temperature Package Package
Model Range Description Option
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V ADP3417JR 0°C to 70°C 8-Lead Standard SO-8
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Small Outline (SOIC)
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W PIN CONFIGURATION
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C BST 1 8 DRVH

*This is a stress rating only; operation beyond these limits can cause the device to IN 2 7 SW
be permanently damaged. Unless otherwise specified, all voltages are referenced ADP3417
TOP VIEW
to PGND. NC 3 (Not To Scale) 6 PGND

VCC 4 5 DRVL

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 ␮F.
2 IN Logic-Level Input Signal, which has primary control of the drive outputs.
3 NC No Connection
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high-low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the ADP3417 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. 0 –3–
ADP3417

IN

tpdldrvl tfdrvl
tpdldrvh trdrvl
DRVL

tfdrvh
tpdhdrvh trdrvh

DRVH-SW VTH VTH

tpdhdrvl
SW 1V

Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)

–4– REV. 0
 Typical Performance Characteristics– ADP3417
60
VCC = 12V
CLOAD = 3nF
T T

IN IN 50
3 3

RISE TIME – ns
DRVH

DRVH DRVH 40
1 1
DRVL DRVL

30
DRVL
2 2

20
0 25 50 75 100 125
JUNCTION TEMPERATURE –
C

TPC 1. DRVH Fall and DRVL TPC 2. DRVL Fall and DRVH TPC 3. DRVH and DRVL Rise Times
Rise Times Rise Times vs. Temperature

28 70 28
VCC = 12V TA = 25
C DRVH TA = 25
C
CLOAD = 3nF VCC = 12V VCC = 12V
26
60
26
24

FALL TIME – ns
50 DRVL
FALL TIME – ns

DRVL
RISE TIME – ns

22
24 40 DRVH
DRVL 20
DRVH 30
18
22
20 16

20 10 14
0 25 50 75 100 125 1 2 3 4 5 1 2 3 4 5
JUNCTION TEMPERATURE –
C LOAD CAPACITANCE – nF LOAD CAPACITANCE – nF

TPC 4. DRVH and DRVL Fall Times TPC 5. DRVH and DRVL Rise Times TPC 6. DRVH and DRVL Fall Times
vs. Temperature vs. Load Capacitance vs. Load Capacitance

60 16
TA = 25
C VCC = 12V
VCC = 12V CLOAD = 3nF
50 CLOAD = 3nF fIN = 250kHz
SUPPLY CURRENT – mA

SUPPLY CURRENT – mA

15
40

30 14

20
13
10

0 12
0 200 400 600 800 1000 1200 0 25 50 75 100 125
IN FREQUENCY – kHz JUNCTION TEMPERATURE –
C

TPC 7. Supply Current vs. TPC 8. Supply Current vs.

Frequency Temperature

REV. 0 –5–
ADP3417
THEORY OF OPERATION To prevent the overlap of the gate drives during Q2’s turn OFF
The ADP3417 is a dual MOSFET driver optimized for driving and Q1’s turn ON, the overlap circuit provides a internal delay
two N-channel MOSFETs in a synchronous buck converter that is set to 50 ns. When the PWM input signal goes high, Q2
topology. A single PWM input signal is all that is required to will begin to turn OFF (after a propagation delay), but before
properly drive the high-side and the low-side FETs. Each driver Q1 can turn ON the overlap protection circuit waits for the
is capable of driving a 3 nF load. voltage at DRVL to drop to around 10% of VCC. Once the
A more detailed description of the ADP3417 and its features voltage at DRVL has reached the 10% point, the overlap protec-
follows. Refer to the Functional Block Diagram. tion circuit will wait for a 50 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.
Low-Side Driver
The low-side driver is designed to drive low RDS(ON) N-channel APPLICATION INFORMATION
MOSFETs. The maximum output resistance for the driver is Supply Capacitor Selection
3 Ω for sourcing and 2.5 Ω for sinking gate current. The low For the supply input (VCC) of the ADP3417, a local bypass
output resistance allows the driver to have 25 ns rise times capacitor is recommended to reduce the noise and to supply some
and 20 ns fall times into a 3 nF load. The bias to the low-side of the peak currents drawn. Use a 1 µF, low ESR capacitor.
driver is internally connected to the VCC supply and PGND. Multilayer ceramic chip (MLCC) capacitors provide the best
When the driver is enabled, the driver’s output is 180 degrees combination of low ESR and small size. Keep the ceramic capacitor
out of phase with the PWM input. When the ADP3417 is dis- as close as possible to the ADP3417.
abled, the low-side gate is held low. Bootstrap Circuit
High-Side Driver The bootstrap circuit uses a charge storage capacitor (CBST) and a
The high-side driver is designed to drive a floating low RDS(ON) diode, as shown in Figure 1. Selection of these components can
N-channel MOSFET. The maximum output resistance for the be done after the high-side MOSFET has been chosen.
driver is 3 Ω for sourcing and 2.5 Ω for sinking gate current. The bootstrap capacitor must have a voltage rating that is able
The low output resistance allows the driver to have 45 ns rise times to handle the maximum supply voltage. A minimum 25 V rating
and 20 ns fall times into a 3 nF load. The bias voltage for the is recommended. The capacitance is determined using the
high-side driver is developed by an external bootstrap supply following equation:
circuit, which is connected between the BST and SW pins.
QGATE
The bootstrap circuit comprises a diode, D1, and bootstrap CBST = (1)
capacitor, CBST. When the ADP3417 is starting up, the SW pin ∆VBST
is at ground, so the bootstrap capacitor will charge up to VCC where, QGATE is the total gate charge of the high-side MOSFET,
through D1. When the PWM input goes high, the high-side and ∆VBST is the voltage droop allowed on the high-side MOSFET
driver will begin to turn the high-side MOSFET, Q1, ON by drive. For example, the IRF7811 has a total gate charge of about
pulling charge out of CBST. As Q1 turns ON, the SW pin will 20 nC. For an allowed droop of 200 mV, the required boot-
rise up to VIN, forcing the BST pin to VIN + VC(BST), which is strap capacitance is 100 nF. A good quality ceramic capacitor
enough gate to source voltage to hold Q1 ON. To complete the should be used.
cycle, Q1 is switched OFF by pulling the gate down to the volt-
A small-signal diode can be used for the bootstrap diode due to
age at the SW pin. When the low-side MOSFET, Q2, turns
the ample gate drive available for the high-side MOSFET. The
ON, the SW pin is pulled to ground. This allows the bootstrap
bootstrap diode must have a minimum 15 V rating to withstand
capacitor to charge up to VCC again. The high-side driver’s
the maximum boosted supply voltage. The average forward
output is in phase with the PWM input.
current can be estimated by:
Overlap Protection Circuit
The Overlap Protection Circuit (OPC) prevents both of the main I F(AVG) ≈ QGATE × f MAX (2)
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing where fMAX is the maximum switching frequency of the control-
through both power switches and the associated losses that can ler. The peak surge current rating should be checked in-circuit,
occur during their ON-OFF transitions. The Overlap Protection since this is dependent on the source impedance of the 12 V
Circuit accomplishes this by adaptively controlling the delay from supply, and the ESR of CBST.
Q1’s turn OFF to Q2’s turn ON, and by internally setting the Printed Circuit Board Layout Considerations
delay from Q2’s turn OFF to Q1’s turn ON. Use the following general guidelines when designing printed
To prevent the overlap of the gate drives during Q1’s turn OFF circuit boards:
and Q2’s turn ON, the overlap circuit monitors the voltage at the 1. Trace out the high-current paths and use short, wide traces
SW pin. When the PWM input signal goes low, Q1 will begin to to make these connections.
turn OFF (after a propagation delay), but before Q2 can turn ON 2. Connect the PGND pin of the ADP3417 as close as possible
the overlap protection circuit waits for the voltage at the SW pin to the source of the lower MOSFET.
to fall from VIN to 1 V. Once the voltage on the SW pin has fallen
to 1 V, Q2 will begin turn ON. By waiting for the voltage on the 3. The VCC bypass capacitor should be located as close as
SW pin to reach 1 V, the overlap protection circuit ensures that possible to VCC and PGND pins.
Q1 is OFF before Q2 turns on, regardless of variations in tem-
perature, supply voltage, gate charge, and drive current.

–6– REV. 0
REV. 0
L1 270F/16V x 3
1H OS-CON SP SERIES
18m ESR(EACH)
VIN12V
+ + +
R7
C1 C2 C3 5m
VINRTN
10F  2
D1 MLCC
Typical Application Circuits

R4 1N4148
C11
10 U2 100nF
D2
1N4148 ADP3417
Q3
1 BST DRVH 8 FDB7030L
2200F/6.3V  9
C4 L2 RUBYCON MBZ SERIES VCC(CORE)
R5 2 IN SW 7
4.7F 600nH 13m ESR (EACH)
20 1.1V – 1.85V
3 NC PGND 6
C6 C13 + +
15nF 4 VCC DRVL 5 15nF
C12 R8
1F 65A
Q7 2 C20 C29 VCC(CORE)RTN
U1 FDB8030L
ADP3163

1 VID4 VCC 20 C7 10F  27

1nF C14 MLCC
solution for VCC(CORE) generation for an Intel Pentium®4 CPU.

2 VID3 REF 19 D3 U3 100nF

1N4148 ADP3417
FROM 3 VID2 PWM1 18 Q4
CPU FDB7030L
1 BST DRVH 8
DRVH

–7–
4 VID1 PWM2 17 L3
RA 2 IN SW 7
SW 600nH
32.4k
5 VID0 PWM3 16 3 NC PGND 6
Q1 C16
2N7000 4 VCC DRVL 5
DRVL 15nF
6 SHARE PC 15
OUTEN C15 R9
R2 1F 2
7 COMP PGND 14 Q8
U5 10k FDB8030L
1/6 7404 RB
COC 8 GND CS– 13
10.0k
1.2nF
9 FB CS+ 12
C17
D4 U4 100nF
10 CT PWRGD 11 1N4148
ADP3417
Q5
C9
1 BST DRVH 8
DRVH FDB7030L
150pF
L4
2 IN SW 7
SW 600nH
R3 3 NC PGND 6
C10 1k C19
100pF 4 VCC DRVL 5
DRVL 15nF
C18 R10

Figure 3. 65 A Intel Pentium 4 CPU Supply Circuit, VR Down Guideline Design

1F 2
Q9
FDB8030L

NC = NO CONNECT
The circuit in Figure 3 shows how three ADP3417 drivers can be combined with the ADP3163 to form a total power conversion
ADP3417
ADP3417
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Small Outline Package

(R-8A)

0.1968 (5.00)

C02713–.8–1/02(0)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1
0.0500 (1.27) 0.0196 (0.50)
 45

BSC 0.0099 (0.25)
0.102 (2.59)
0.0098 (0.25) 0.094 (2.39)
0.0040 (0.10) 8

SEATING
0.0192 (0.49) 0.0098 (0.25) 0
0.0500 (1.27)
PLANE 0.0138 (0.35) 0.0075 (0.19) 0.0160 (0.41)

PRINTED IN U.S.A.

–8– REV. 0