Advanced Integrated

Circuits
Lecture Notes 2025

Carsten Wulff

Built on Sun Jun 8 [Link] UTC 2025

from a53266d730c2b7fe4fd6ba90e9c2b3586e43f3e2

©Carsten Wulff 2025

Contents

Contents 3

1 Background 1

2 Introduction 3
2.1 Who . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 How I see our roles . . . . . . . . . . . . . . . . . 3
2.3 I want you to learn the skills necessary to make
your own ICs . . . . . . . . . . . . . . . . . . . . 4
2.4 There will always be analog circuits, because the
real world is analog . . . . . . . . . . . . . . . . . 5
2.4.1 Will you tape-out an IC? . . . . . . . . . . 6
2.4.2 What the team needs to know to design ICs 6
2.4.3 Zen of IC design (stolen from Zen of Python) 7
2.4.4 IC design mantra . . . . . . . . . . . . . . 8
2.4.5 Analog Design Process . . . . . . . . . . . 8
2.5 My Goal . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Syllabus . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 JNW (2025) . . . . . . . . . . . . . . . . . . . . . 10
2.7.1 Grading . . . . . . . . . . . . . . . . . . . 12
2.7.2 Group dynamics . . . . . . . . . . . . . . 12
2.8 Software . . . . . . . . . . . . . . . . . . . . . . . 13

3 A Refresher 15
3.1 There are standard units of measurement . . . . 15
3.2 Electrons . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Probability . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Uncertainty principle . . . . . . . . . . . . . . . . 17
3.5 States as a function of time and space . . . . . . 17
3.6 Allowed energy levels in atoms . . . . . . . . . . 18
3.7 Allowed energy levels in solids . . . . . . . . . . 18
3.8 Silicon Unit Cell . . . . . . . . . . . . . . . . . . . 19
3.9 Band structure . . . . . . . . . . . . . . . . . . . 20
3.10 Valence band and Conduction band . . . . . . . 21
3.11 Fermi level . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Metals . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Insulators . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Semiconductors . . . . . . . . . . . . . . . . . . . 23
3.15 Band diagrams . . . . . . . . . . . . . . . . . . . 23
3.16 Density of electrons/holes . . . . . . . . . . . . . 23
3.17 Fields . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Permittivity and Permeability . . . . . . . . . . . 24
3.19 Quantum electrodynamics . . . . . . . . . . . . . 25
3.20 Voltage . . . . . . . . . . . . . . . . . . . . . . . . 25
3.21 Current . . . . . . . . . . . . . . . . . . . . . . . 25
3.22 Drift current . . . . . . . . . . . . . . . . . . . . . 26
3.23 Diffusion current . . . . . . . . . . . . . . . . . . 27
 3.24 Why are there two currents? . . . . . . . . . . . . 27
3.25 Currents in a semiconductor . . . . . . . . . . . 27
3.26 Resistors . . . . . . . . . . . . . . . . . . . . . . . 28
3.27 Capacitors . . . . . . . . . . . . . . . . . . . . . . 28
3.28 Inductors . . . . . . . . . . . . . . . . . . . . . . 28

4 Diodes 29
4.1 Why . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Silicon . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Intrinsic carrier concentration . . . . . . . . . . . 31
4.4 It’s all quantum . . . . . . . . . . . . . . . . . . . 32
4.4.1 Density of states . . . . . . . . . . . . . . 34
4.4.2 How to think about electrons (and holes) 36
4.5 Doping . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 PN junctions . . . . . . . . . . . . . . . . . . . . 38
4.6.1 Built-in voltage . . . . . . . . . . . . . . . 38
4.6.2 Current . . . . . . . . . . . . . . . . . . . 39
4.6.3 Forward voltage temperature dependence 41
4.6.4 Current proportional to temperature . . . 42
4.7 Equations aren’t real . . . . . . . . . . . . . . . . 43
References . . . . . . . . . . . . . . . . . . . . . . 44

5 Noise 45
5.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2 Statistics . . . . . . . . . . . . . . . . . . . . . . . 45
5.3 Average Power . . . . . . . . . . . . . . . . . . . 46
5.4 Noise Spectrum . . . . . . . . . . . . . . . . . . . 47
5.5 Probability Distribution . . . . . . . . . . . . . . 48
5.6 PSD of a white noise source . . . . . . . . . . . . 49
5.7 Summing noise sources . . . . . . . . . . . . . . 49
5.8 Signal to Noise Ratios . . . . . . . . . . . . . . . 50
5.9 Noise figure and Friis formula . . . . . . . . . . 51
5.10 Spectral Density . . . . . . . . . . . . . . . . . . 51
5.10.1 Definition of Spectral Density . . . . . . . 52
5.10.2 Sources of Confusion . . . . . . . . . . . . 52
5.10.3 Example: Thermal Noise . . . . . . . . . . 54
5.10.4 Einstein: The source . . . . . . . . . . . . 54

6 Sky130nm tutorial 57
6.1 Tools . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1 Setup WSL (Applicable for Windows users) 57
6.1.2 Setup public key towards github . . . . . 57
6.1.3 Provide git with author identity . . . . . 58
6.1.4 Get AICEX and setup your shell . . . . . 58
6.1.5 On systems with python3 > 3.12 . . . . . 58
6.1.6 Install Tools . . . . . . . . . . . . . . . . . 59
6.1.7 Install cicconf . . . . . . . . . . . . . . . . 59
6.1.8 Install cicsim . . . . . . . . . . . . . . . . 60
6.1.9 Setup your ngspice settings . . . . . . . . 60
6.2 Check that magic and xschem works . . . . . . . 60
 6.3 Design tutorial . . . . . . . . . . . . . . . . . . . 60
6.3.1 Create the IP . . . . . . . . . . . . . . . . 60
6.3.2 The file structure . . . . . . . . . . . . . . 60
6.3.3 Github setup . . . . . . . . . . . . . . . . 62
6.3.4 Start working . . . . . . . . . . . . . . . . 63
6.3.5 Draw Schematic . . . . . . . . . . . . . . 63
6.3.6 Typical corner SPICE simulation . . . . . 64
6.3.7 All corners SPICE simulations . . . . . . 67
6.3.8 Draw Layout . . . . . . . . . . . . . . . . 69
6.3.9 Layout verification . . . . . . . . . . . . . 74
6.3.10 Extract layout parasitics . . . . . . . . . . 74
6.3.11 Simulate with layout parasitics . . . . . . 75
6.3.12 Make documentation . . . . . . . . . . . . 75
6.3.13 Edit [Link] . . . . . . . . . . . . . . . . 76
6.3.14 Setup github pages . . . . . . . . . . . . . 76
6.3.15 Frequency asked questions . . . . . . . . 76

7 Analog Design 77
7.1 Checklist . . . . . . . . . . . . . . . . . . . . . . . 77
7.1.1 Specification . . . . . . . . . . . . . . . . . 77
7.1.2 Design . . . . . . . . . . . . . . . . . . . . 78
7.1.3 Tapeout . . . . . . . . . . . . . . . . . . . 78
7.2 Schematic rules . . . . . . . . . . . . . . . . . . . 78
7.3 Layout rules . . . . . . . . . . . . . . . . . . . . . 80

8 IC and ESD 83
8.1 What blocks must our IC include? . . . . . . . . 83
8.2 Electrostatic Discharge . . . . . . . . . . . . . . . 86
8.2.1 When do ESD events occur? . . . . . . . . 87
8.2.2 Before/during PCB . . . . . . . . . . . . . 87
8.2.3 After PCB . . . . . . . . . . . . . . . . . . 87
8.2.4 Human body model (HBM) . . . . . . . . 88
8.2.5 Charged device model (CDM) . . . . . . 88
8.3 An HBM ESD zap example . . . . . . . . . . . . 90
8.4 Permutations . . . . . . . . . . . . . . . . . . . . 91
8.4.1 Why does this work? . . . . . . . . . . . . 93
8.5 But I just want a digital input, what do I need? . 96
8.5.1 Input buffer . . . . . . . . . . . . . . . . . 97
8.6 Latch-up . . . . . . . . . . . . . . . . . . . . . . . 98
8.6.1 How can current in one place lead to a
current somewhere else? . . . . . . . . . . 98
8.7 Want to learn more? . . . . . . . . . . . . . . . . 100

9 References and bias 101

9.1 Routing . . . . . . . . . . . . . . . . . . . . . . . 101
9.2 Bandgap voltage reference . . . . . . . . . . . . . 104
9.2.1 A voltage complementary to temperature
(CTAT) . . . . . . . . . . . . . . . . . . . . 104
9.2.2 A current proportional to temperature
(PTAT) . . . . . . . . . . . . . . . . . . . . 105
9.2.3 How to combine a CTAT with a PTAT ? . 106
 9.2.4 Brokaw reference . . . . . . . . . . . . . . 107
9.2.5 Low voltage bandgap . . . . . . . . . . . 109
9.3 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.3.1 Voltage to current conversion . . . . . . . 112
9.3.2 GM Cell . . . . . . . . . . . . . . . . . . . 113
9.4 Want to learn more? . . . . . . . . . . . . . . . . 115

10 Analog frontend and filters 117

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . 117
10.2 Filters . . . . . . . . . . . . . . . . . . . . . . . . 119
10.2.1 First order filter . . . . . . . . . . . . . . . 120
10.2.2 Second order filter . . . . . . . . . . . . . 121
10.2.3 How do we implement the filter sections? 122
10.3 Gm-C . . . . . . . . . . . . . . . . . . . . . . . . 122
10.3.1 Differential Gm-C . . . . . . . . . . . . . 123
10.3.2 Finding a transconductor . . . . . . . . . 125
10.4 Active-RC . . . . . . . . . . . . . . . . . . . . . . 126
10.4.1 General purpose first order filter . . . . . 126
10.4.2 General purpose biquad . . . . . . . . . . 129
10.5 The OTA is not ideal . . . . . . . . . . . . . . . . 130
10.6 Example circuit . . . . . . . . . . . . . . . . . . . 130
10.7 My favorite OTA . . . . . . . . . . . . . . . . . . 131
10.8 Want to learn more? . . . . . . . . . . . . . . . . 133

11 Switched-Capacitor Circuits 135

11.1 Active-RC . . . . . . . . . . . . . . . . . . . . . . 135
11.2 Gm-C . . . . . . . . . . . . . . . . . . . . . . . . 137
11.3 Switched capacitor . . . . . . . . . . . . . . . . . 137
11.3.1 An example SC circuit . . . . . . . . . . . 140
11.4 Discrete-Time Signals . . . . . . . . . . . . . . . 142
11.4.1 The mathematics . . . . . . . . . . . . . . 143
11.4.2 Python discrete time example . . . . . . . 144
11.4.3 Aliasing, bandwidth and sample rate theory 145
11.4.4 Z-transform . . . . . . . . . . . . . . . . . 147
11.4.5 Pole-Zero plots . . . . . . . . . . . . . . . 148
11.4.6 Z-domain . . . . . . . . . . . . . . . . . . 148
11.4.7 First order filter . . . . . . . . . . . . . . . 149
11.4.8 Finite-impulse response(FIR) . . . . . . . 151
11.5 Switched-Capacitor . . . . . . . . . . . . . . . . . 152
11.5.1 Switched capacitor gain circuit . . . . . . 154
11.5.2 Switched capacitor integrator . . . . . . . 155
11.5.3 Noise . . . . . . . . . . . . . . . . . . . . . 156
11.5.4 Sub-circuits for SC-circuits . . . . . . . . . 158
11.5.5 Example . . . . . . . . . . . . . . . . . . . 161
11.6 Want to learn more? . . . . . . . . . . . . . . . . 162

12 Oversampling and Sigma-Delta ADCs 163

12.1 ADC state-of-the-art . . . . . . . . . . . . . . . . 163
12.1.1 What makes a state-of-the-art ADC . . . . 164
12.1.2 High resolution FOM . . . . . . . . . . . 170
 12.2 Quantization . . . . . . . . . . . . . . . . . . . . 171
12.2.1 Signal to Quantization noise ratio . . . . . 175
12.2.2 Understanding quantization . . . . . . . . 175
12.2.3 Why you should care about quantization
noise . . . . . . . . . . . . . . . . . . . . . 177
12.3 Oversampling . . . . . . . . . . . . . . . . . . . . 178
12.3.1 Noise power . . . . . . . . . . . . . . . . . 178
12.3.2 Signal power . . . . . . . . . . . . . . . . 179
12.3.3 Signal to Noise Ratio . . . . . . . . . . . . 179
12.3.4 Signal to Quantization Noise Ratio . . . . 179
12.3.5 Python oversample . . . . . . . . . . . . . 180
12.4 Noise Shaping . . . . . . . . . . . . . . . . . . . . 181
12.4.1 The magic of feedback . . . . . . . . . . . 181
12.4.2 Sigma-delta principle . . . . . . . . . . . 182
12.4.3 Signal transfer function . . . . . . . . . . 184
12.4.4 Noise transfer function . . . . . . . . . . . 184
12.4.5 Combined transfer function . . . . . . . . 185
12.5 First-Order Noise-Shaping . . . . . . . . . . . . . 185
12.5.1 SQNR and ENOB . . . . . . . . . . . . . . 187
12.6 Examples . . . . . . . . . . . . . . . . . . . . . . 187
12.6.1 Python noise-shaping . . . . . . . . . . . 187
12.6.2 The wonderful world of SD modulators . 189
12.7 Want to learn more? . . . . . . . . . . . . . . . . 193

13 Voltage regulation 195

13.1 Voltage source . . . . . . . . . . . . . . . . . . . 195
13.1.1 Core voltage . . . . . . . . . . . . . . . . . 199
13.1.2 IO voltage . . . . . . . . . . . . . . . . . . 199
13.1.3 Supply planning . . . . . . . . . . . . . . 200
13.2 Linear Regulators . . . . . . . . . . . . . . . . . . 201
13.2.1 PMOS pass-fet . . . . . . . . . . . . . . . 201
13.2.2 NMOS pass-fet . . . . . . . . . . . . . . . 202
13.2.3 Control of pass-fet . . . . . . . . . . . . . 203
13.3 Switched Regulators . . . . . . . . . . . . . . . . 204
13.3.1 Principles of switched regulators . . . . . 205
13.3.2 Inductive DC/DC converter details . . . . 208
13.3.3 Pulse width modulation (PWM) . . . . . 209
13.3.4 Real world use . . . . . . . . . . . . . . . 212
13.3.5 Pulsed Frequency Mode (PFM) . . . . . . 212
13.4 Want to learn more? . . . . . . . . . . . . . . . . 214
13.4.1 Linear regulators . . . . . . . . . . . . . . 215
13.4.2 DC-DC converters . . . . . . . . . . . . . 215

14 Clocks and PLLs 217

14.1 Why clocks? . . . . . . . . . . . . . . . . . . . . . 217
14.1.1 A customer story . . . . . . . . . . . . . . 217
14.1.2 Frequency . . . . . . . . . . . . . . . . . . 219
14.1.3 Noise . . . . . . . . . . . . . . . . . . . . . 219
14.1.4 Stability . . . . . . . . . . . . . . . . . . . 219
14.1.5 Conclusion . . . . . . . . . . . . . . . . . 219
 14.2 A typical System-On-Chip clock system . . . . . 220
14.2.1 32 MHz crystal . . . . . . . . . . . . . . . 220
14.2.2 32 KiHz crystal . . . . . . . . . . . . . . . 221
14.2.3 PCB antenna . . . . . . . . . . . . . . . . 221
14.2.4 DC/DC inductor . . . . . . . . . . . . . . 221
14.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 223
14.3.1 Integer PLL . . . . . . . . . . . . . . . . . 224
14.3.2 Fractional PLL . . . . . . . . . . . . . . . 224
14.3.3 Modulation in PLLs . . . . . . . . . . . . 225
14.4 PLL Example . . . . . . . . . . . . . . . . . . . . 226
14.4.1 Loop gain . . . . . . . . . . . . . . . . . . 227
14.4.2 Controlled oscillator . . . . . . . . . . . . 227
14.4.3 Phase detector and charge pump . . . . . 229
14.4.4 Loop filter . . . . . . . . . . . . . . . . . . 230
14.4.5 Divider . . . . . . . . . . . . . . . . . . . 230
14.4.6 Loop transfer function . . . . . . . . . . . 231
14.5 Want to learn more? . . . . . . . . . . . . . . . . 233

15 Oscillators 235
15.1 Atomic clocks . . . . . . . . . . . . . . . . . . . . 235
15.1.1 Microchip 5071B Cesium Primary Time and
Frequency Standard . . . . . . . . . . . . 235
15.1.2 Rubidium standard . . . . . . . . . . . . . 236
15.2 Crystal oscillators . . . . . . . . . . . . . . . . . . 238
15.2.1 Impedance . . . . . . . . . . . . . . . . . 239
15.2.2 Circuit . . . . . . . . . . . . . . . . . . . . 241
15.2.3 Temperature behavior . . . . . . . . . . . 243
15.3 Controlled Oscillators . . . . . . . . . . . . . . . 244
15.3.1 Ring oscillator . . . . . . . . . . . . . . . . 244
15.3.2 Capacitive load . . . . . . . . . . . . . . . 245
15.3.3 Realistic . . . . . . . . . . . . . . . . . . . 246
15.3.4 Digitally controlled oscillator . . . . . . . 248
15.3.5 Differential . . . . . . . . . . . . . . . . . 248
15.3.6 LC oscillator . . . . . . . . . . . . . . . . . 249
15.4 Relaxation oscillators . . . . . . . . . . . . . . . . 251
15.5 Want to learn more? . . . . . . . . . . . . . . . . 251
15.5.1 Crystal oscillators . . . . . . . . . . . . . . 251
15.5.2 CMOS oscillators . . . . . . . . . . . . . . 252

16 Low Power Radio 253

16.1 Data Rate . . . . . . . . . . . . . . . . . . . . . . 253
16.1.1 Data . . . . . . . . . . . . . . . . . . . . . 253
16.1.2 Rate . . . . . . . . . . . . . . . . . . . . . 254
16.1.3 Data Rate . . . . . . . . . . . . . . . . . . 254
16.2 Carrier Frequency & Range . . . . . . . . . . . . 254
16.2.1 ISM (industrial, scientific and medical) bands 254
16.2.2 Antenna . . . . . . . . . . . . . . . . . . . 255
16.2.3 Range (Friis) . . . . . . . . . . . . . . . . . 256
16.2.4 Range (Free space) . . . . . . . . . . . . . 256
16.2.5 Range (Real world) . . . . . . . . . . . . . 257
 16.3 Power supply . . . . . . . . . . . . . . . . . . . . 257
16.3.1 Battery . . . . . . . . . . . . . . . . . . . . 258
16.4 Decisions . . . . . . . . . . . . . . . . . . . . . . 258
16.4.1 Modulation . . . . . . . . . . . . . . . . . 258
16.4.2 BPSK . . . . . . . . . . . . . . . . . . . . . 259
16.4.3 Single carrier, or multi carrier? . . . . . . 265
16.4.4 Use a Software Defined Radio . . . . . . . 266
16.5 Bluetooth . . . . . . . . . . . . . . . . . . . . . . 267
16.5.1 Bluetooth Basic Rate/Extended Data rate 268
16.5.2 Bluetooth Low Energy . . . . . . . . . . . 268
16.6 Algorithm to design state-of-the-art LE radio . . 269
16.6.1 LNTA . . . . . . . . . . . . . . . . . . . . 270
16.6.2 MIXER . . . . . . . . . . . . . . . . . . . . 271
16.6.3 AAF . . . . . . . . . . . . . . . . . . . . . 273
16.6.4 ADC . . . . . . . . . . . . . . . . . . . . . 273
16.6.5 AD-PLL . . . . . . . . . . . . . . . . . . . 275
16.6.6 Baseband . . . . . . . . . . . . . . . . . . 275
16.7 What do we really want, in the end? . . . . . . . 276
16.8 Want to learn more? . . . . . . . . . . . . . . . . 277

17 Energy Sources 279

17.1 Thermoelectric . . . . . . . . . . . . . . . . . . . 281
17.1.1 Radioisotope Thermoelectric generator . 285
17.1.2 Thermoelectric generators . . . . . . . . . 285
17.2 Photovoltaic . . . . . . . . . . . . . . . . . . . . . 286
17.3 Piezoelectric . . . . . . . . . . . . . . . . . . . . . 289
17.4 Electromagnetic . . . . . . . . . . . . . . . . . . . 291
17.4.1 “Near field” harvesting . . . . . . . . . . 291
17.4.2 Ambient RF Harvesting . . . . . . . . . . 292
17.5 Triboelectric generator . . . . . . . . . . . . . . . 293
17.6 Comparison . . . . . . . . . . . . . . . . . . . . . 296
17.7 Want to learn more? . . . . . . . . . . . . . . . . 297

18 Analog SystemVerilog 299

18.1 Digital simulation . . . . . . . . . . . . . . . . . 300
18.2 Transient analog simulation . . . . . . . . . . . . 303
18.3 Mixed signal simulation . . . . . . . . . . . . . . 304
18.4 Analog SystemVerilog Example . . . . . . . . . . 306
18.4.1 TinyTapeout TT06_SAR . . . . . . . . . . 306
18.4.2 SAR operation . . . . . . . . . . . . . . . 306
18.5 Want to learn more? . . . . . . . . . . . . . . . . 309

19 How to write a project report 311

19.1 Why . . . . . . . . . . . . . . . . . . . . . . . . . 311
19.2 On writing English . . . . . . . . . . . . . . . . . 311
19.2.1 Shorter is better . . . . . . . . . . . . . . . 311
19.2.2 Be careful with adjectives . . . . . . . . . 312
19.2.3 Use paragraphs . . . . . . . . . . . . . . . 312
19.2.4 Don’t be afraid of I . . . . . . . . . . . . . 312
19.2.5 Transitions are important . . . . . . . . . 312
19.2.6 However, is not a start of a sentence . . . 313
 19.3 Report Structure . . . . . . . . . . . . . . . . . . 313
19.3.1 Introduction . . . . . . . . . . . . . . . . . 313
19.3.2 Theory . . . . . . . . . . . . . . . . . . . . 313
19.3.3 Implementation . . . . . . . . . . . . . . . 314
19.3.4 Result . . . . . . . . . . . . . . . . . . . . 314
19.3.5 Discussion . . . . . . . . . . . . . . . . . . 314
19.3.6 Future work . . . . . . . . . . . . . . . . . 314
19.3.7 Conclusion . . . . . . . . . . . . . . . . . 314
19.3.8 Appendix . . . . . . . . . . . . . . . . . . 315
19.4 Checklist . . . . . . . . . . . . . . . . . . . . . . . 315

20 Layout Generation 317

20.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . 317
20.2 Setup . . . . . . . . . . . . . . . . . . . . . . . . . 317
20.3 CICPY . . . . . . . . . . . . . . . . . . . . . . . . 317
20.4 Placement . . . . . . . . . . . . . . . . . . . . . . 317

21 MOSFETs 321
21.1 Metal Oxide Semiconductor . . . . . . . . . . . . 321
21.2 Field Effect . . . . . . . . . . . . . . . . . . . . . 323
21.3 Analog transistors in the books . . . . . . . . . . 327
21.4 Transistors in weak inversion . . . . . . . . . . . 329
21.5 Transistors in strong inversion . . . . . . . . . . . 332
21.6 How should I size my transistor? . . . . . . . . . 335
21.7 Introduction to behavior . . . . . . . . . . . . . . 336
21.7.1 Drain Source Current . . . . . . . . . . . 336
21.7.2 Gate-source voltage . . . . . . . . . . . . 337
21.7.3 Inversion level . . . . . . . . . . . . . . . 337
21.7.4 Drain source voltage . . . . . . . . . . . . 339
21.7.5 Strong inversion . . . . . . . . . . . . . . 340
21.7.6 Low frequency model . . . . . . . . . . . 342
21.7.7 Transconductance . . . . . . . . . . . . . 342
21.7.8 Intrinsic gain . . . . . . . . . . . . . . . . 343
21.7.9 High frequency model . . . . . . . . . . . 344
21.7.10 Be careful with Cgd (blame Miller) . . . . 346
21.8 Weak inversion . . . . . . . . . . . . . . . . . . . 347
21.9 Velocity saturation . . . . . . . . . . . . . . . . . 348
21.9.1 Square law model . . . . . . . . . . . . . 349
21.9.2 Mobility Degradation . . . . . . . . . . . 349
21.9.3 What about holes (PMOS) . . . . . . . . . 350
21.10 OTHER . . . . . . . . . . . . . . . . . . . . . . . 350
21.10.1 Drain induced barrier lowering (DIBL) . . 351
21.10.2 Well Proximity Effect (WPE) . . . . . . . . 352
21.10.3 Stress effects . . . . . . . . . . . . . . . . . 352
21.10.4 Gate current . . . . . . . . . . . . . . . . . 353
21.10.5 Hot carrier injection . . . . . . . . . . . . 353
21.10.6 Channel initiated secondary-electron
(CHISEL) . . . . . . . . . . . . . . . . . . 354
21.11 Variability . . . . . . . . . . . . . . . . . . . . . . 354
21.11.1 Voltage variation . . . . . . . . . . . . . . 355
21.11.2 Systematic variations . . . . . . . . . . . . 355
 21.11.3 Process variations . . . . . . . . . . . . . 356
21.11.4 Process corners . . . . . . . . . . . . . . . 356
21.11.5 Fix process variation . . . . . . . . . . . . 357
21.11.6 Temperature variation . . . . . . . . . . . 357
21.11.7 It depends on

𝑉𝐷𝐷

. . . . . . . . . . . . . . . . . . . . . . . . 358
21.11.8 How do we fix temperature variation? . . 358
21.11.9 Random Variation . . . . . . . . . . . . . 358
21.11.10 Pelgrom’s law . . . . . . . . . . . . . . . . 359
21.11.11 Transistors with same

𝑉𝐺𝑆

. . . . . . . . . . . . . . . . . . . . . . . . 359
21.11.12 What else can we do? . . . . . . . . . . . . 360
21.11.13 Transistor Noise . . . . . . . . . . . . . . . 361

22 Circuits 363
22.1 Current Mirrors . . . . . . . . . . . . . . . . . . . 363
22.1.1 Normal current mirror . . . . . . . . . . . 363
22.1.2 Source degeneration . . . . . . . . . . . . 366
22.1.3 Output resistance . . . . . . . . . . . . . . 367
22.2 Amplifiers . . . . . . . . . . . . . . . . . . . . . . 370
22.3 Source follower . . . . . . . . . . . . . . . . . . . 370
22.3.1 Output resistance . . . . . . . . . . . . . . 370
22.3.2 Why use a source follower? . . . . . . . . 371
22.4 Common gate . . . . . . . . . . . . . . . . . . . . 372
22.4.1 Input resistance . . . . . . . . . . . . . . . 373
22.4.2 Output resistance . . . . . . . . . . . . . . 373
22.4.3 Gain . . . . . . . . . . . . . . . . . . . . . 373
22.5 Common source . . . . . . . . . . . . . . . . . . 374
22.5.1 Gain . . . . . . . . . . . . . . . . . . . . . 375
22.5.2 Why common source? . . . . . . . . . . . 376
22.6 Differential pair . . . . . . . . . . . . . . . . . . . 376
22.6.1 Diff pairs are cool . . . . . . . . . . . . . . 377

23 Integrated Passives 379

23.1 Metal in ICs is not wire in schematic . . . . . . . 379
23.2 Resistors . . . . . . . . . . . . . . . . . . . . . . . 380
23.2.1 Polysilicon . . . . . . . . . . . . . . . . . . 380
23.2.2 Diffusion . . . . . . . . . . . . . . . . . . 381
23.2.3 Metal . . . . . . . . . . . . . . . . . . . . . 381
23.3 Capacitors . . . . . . . . . . . . . . . . . . . . . . 382
23.3.1 What is S, M, L, XL on a chip? . . . . . . . 382
23.3.2 Metal-Oxide-Metal finger capacitors . . . 382
23.3.3 MOS capacitors . . . . . . . . . . . . . . . 383
23.3.4 Varactors . . . . . . . . . . . . . . . . . . 384
23.4 Inductors . . . . . . . . . . . . . . . . . . . . . . 384
23.5 Variation in passives . . . . . . . . . . . . . . . . 385
 23.6 Relative precision . . . . . . . . . . . . . . . . . . 385
23.7 Diodes . . . . . . . . . . . . . . . . . . . . . . . . 387

24 SPICE 389
24.1 SPICE . . . . . . . . . . . . . . . . . . . . . . . . 389
24.2 Simulation Program with Integrated Circuit Em-
phasis . . . . . . . . . . . . . . . . . . . . . . . . 389
24.2.1 Today . . . . . . . . . . . . . . . . . . . . 389
24.2.2 But . . . . . . . . . . . . . . . . . . . . . . 390
24.2.3 Sources . . . . . . . . . . . . . . . . . . . 391
24.2.4 Passives . . . . . . . . . . . . . . . . . . . 392
24.2.5 Transistor Models . . . . . . . . . . . . . . 392
24.2.6 Transistors . . . . . . . . . . . . . . . . . . 394
24.2.7 Foundries . . . . . . . . . . . . . . . . . . 394
24.3 Find right transistor sizes . . . . . . . . . . . . . 394
24.3.1 Use unit size transistors for analog design 395
24.3.2 What about gm/Id ? . . . . . . . . . . . . 395
24.3.3 Characterize the transistors . . . . . . . . 396
24.4 More information . . . . . . . . . . . . . . . . . . 396
24.5 Analog Design . . . . . . . . . . . . . . . . . . . 396
24.6 Demo . . . . . . . . . . . . . . . . . . . . . . . . 396

25 CMOS Logic 397

25.1 CMOS Logic . . . . . . . . . . . . . . . . . . . . . 397
25.2 Analog transistor to digital transistor . . . . . . . 397
25.3 CMOS static logic assumptions . . . . . . . . . . 399
25.4 Don’t break rules unless you know exactly why it
will be OK . . . . . . . . . . . . . . . . . . . . . . 401
25.5 Logic cells . . . . . . . . . . . . . . . . . . . . . . 401
25.5.1 CMOS static logic is inverting . . . . . . . 401
25.5.2 Rules for inverting logic . . . . . . . . . . 404
25.6 SR-Latch . . . . . . . . . . . . . . . . . . . . . . . 408
25.7 D-Latch (16 transistors) . . . . . . . . . . . . . . . 409
25.8 Other logic cells . . . . . . . . . . . . . . . . . . . 409
25.9 AOI22: and or invert . . . . . . . . . . . . . . . . 410
25.10 Tristate inverter . . . . . . . . . . . . . . . . . . . 411
25.11 Mux . . . . . . . . . . . . . . . . . . . . . . . . . 411
25.12 There are other types of logic . . . . . . . . . . . 413
25.13 Speed . . . . . . . . . . . . . . . . . . . . . . . . 414
25.14 Flip-flops and speed . . . . . . . . . . . . . . . . 414
25.15 Timing analysis . . . . . . . . . . . . . . . . . . . 415
25.16 Timing analysis tools . . . . . . . . . . . . . . . . 416
25.17 Every gate must be simulated to provide behavior
over input transition and load capacitance . . . . 419
25.18 All analog blocks must have associated liberty
file to describe behavior and timing paths If you
integrate analog into digital top flow . . . . . . . 419
25.19 Gate Delay . . . . . . . . . . . . . . . . . . . . . . 419
25.20 Delay estimation . . . . . . . . . . . . . . . . . . 419
25.21 Elmore Delay . . . . . . . . . . . . . . . . . . . . 420
25.22 Delay components . . . . . . . . . . . . . . . . . 420
 25.23 Modern IC timing analysis requires computers
with advanced programs . . . . . . . . . . . . . 422
25.24 Best number of stages . . . . . . . . . . . . . . . 422
25.25 Which has shortest delay? . . . . . . . . . . . . . 422
25.26 Trends . . . . . . . . . . . . . . . . . . . . . . . . 423
25.27 Attack vector . . . . . . . . . . . . . . . . . . . . 424
25.28 Pick two . . . . . . . . . . . . . . . . . . . . . . . 428
25.29 Power . . . . . . . . . . . . . . . . . . . . . . . . 428
25.30 What is power? . . . . . . . . . . . . . . . . . . . 428
25.31 Power dissipated in a resistor . . . . . . . . . . . 429
25.32 Charging a capacitor to VDD . . . . . . . . . . . 429
25.33 Energy to charge a capacitor to a voltage VDD . 429
25.34 Discharging a capacitor to 0 . . . . . . . . . . . . 430
25.35 Power consumption of digital circuits . . . . . . 430
25.36 Sources of power dissipation in CMOS logic . . . 430
25.37 Switching Power in logic gates . . . . . . . . . . 431
25.38 Switching probability . . . . . . . . . . . . . . . 431
25.39 Strategies to reduce dynamic power . . . . . . . 433
25.39.1 Stop clock . . . . . . . . . . . . . . . . . . 434
25.39.2 Stop activity . . . . . . . . . . . . . . . . . 434
25.39.3 Reduce frequency . . . . . . . . . . . . . . 435
25.39.4 Turn off power supply . . . . . . . . . . . 435
25.40 Wires . . . . . . . . . . . . . . . . . . . . . . . . . 436
25.41 Wire geometry . . . . . . . . . . . . . . . . . . . 436
25.42 Metal stack . . . . . . . . . . . . . . . . . . . . . 436
25.43 Metal routing rules on IC . . . . . . . . . . . . . 437
25.44 Modeling Interconnect . . . . . . . . . . . . . . . 437
25.45 Lumped model . . . . . . . . . . . . . . . . . . . 437
25.46 Wire resistance . . . . . . . . . . . . . . . . . . . 438
25.47 Most wires: Copper . . . . . . . . . . . . . . . . . 438
25.48 Contacts . . . . . . . . . . . . . . . . . . . . . . . 439
25.49 Wire Capacitance . . . . . . . . . . . . . . . . . . 439
25.50 FSM . . . . . . . . . . . . . . . . . . . . . . . . . 439
25.51 Mealy machine . . . . . . . . . . . . . . . . . . . 439
25.52 Moore machine . . . . . . . . . . . . . . . . . . . 440
25.53 Mealy versus Moore . . . . . . . . . . . . . . . . 440
25.53.1 dicex/sim/counter_sv/counter.v . . . . . 440
25.54 Battery charger FSM . . . . . . . . . . . . . . . . 441
25.54.1 Li-Ion batteries . . . . . . . . . . . . . . . 441
25.54.2 Battery charger - Inputs . . . . . . . . . . 442
25.54.3 Battery charger - States . . . . . . . . . . . 442

26 Mixed Signal Simulation in NGSPICE 447

26.1 Mixed Signal Simulation in ngspice . . . . . . . 447
26.2 Digital simulation . . . . . . . . . . . . . . . . . 447
26.3 Transient analog simulation . . . . . . . . . . . . 448
26.4 Demo . . . . . . . . . . . . . . . . . . . . . . . . 449
26.5 The circuit . . . . . . . . . . . . . . . . . . . . . . 450
26.6 The digital code . . . . . . . . . . . . . . . . . . . 450
26.7 Compile RTL . . . . . . . . . . . . . . . . . . . . 451
26.8 Import object into SPICE file . . . . . . . . . . . . 451
 26.9 Import in testbench . . . . . . . . . . . . . . . . . 452
26.10 Override default digital output voltage . . . . . 452
26.11 Running . . . . . . . . . . . . . . . . . . . . . . . 452

27 Analog Neural Networks and Translinear Circuits 453

27.0.1 Kirchoff’s voltage law . . . . . . . . . . . 455
27.0.2 Kirchoff’s current law . . . . . . . . . . . 456
27.0.3 Charge concervation . . . . . . . . . . . . 457
27.1 Multiplication . . . . . . . . . . . . . . . . . . . . 458
27.1.1 Digital capacitance . . . . . . . . . . . . . 458
27.1.2 Mixing . . . . . . . . . . . . . . . . . . . . 458
27.1.3 Translinear principle . . . . . . . . . . . . 459
27.2 Want to learn more? . . . . . . . . . . . . . . . . 461
 Background 1
In the spring of 2025 I lectured Advanced Integrated Circuits for
the fourth time. I have an inherent need to make things better, and
the course is no different.

In 2022 I noticed that little of what I had on slides, or said in

lectures, made it into the student brain. That annoyed me, and I
realized that probably a few things needed to change.

In 2023 I moved to complete open source project, and the project

was without grade. There should have been a grade on the
project.

I feel the lectures have gotten better. I did not take attendance in
2023, but there were 19 students that took the exam in 2024. I don’t
have all the dates, but an average attendance of 76 %.

Date Attendance
2024-02-02 19
2024-02-09 17
2024-02-16 16
2024-03-01 14
2024-03-07 14
2024-03-15 12
2024-03-22 13
2024-04-12 16
2024-04-19 10

In 2025 there were 23 students that took the exam, however, 26

different students showed up to the lectures (more than a few
times). The average attendance was around 80 %.

Wk Attendance
2 21
3 21
4 23
5 20
6 22
7 24
9 20
9 24
11 20
12 17
14 16
15 14

In 2024 I finally felt I achieved a balance. I spent Thursday’s

preparing for the lecture, writing these notes, making a YouTube
video (so I’ll remember next year what I wanted to talk about). I
passed 1k subscribers on Youtube. Friday’s I had the lecture and
the group work.
2 1 Background

For the group work I forced students into groups, and I forced that
they for the first 5-10 minutes do a check-in. That I need to do next
year too.
For the check in, they had go around in the group and answer one
of the following questions:

▶ What is one thing that is going on in your life (personal or

professional)?
▶ What is one thing that you’re grateful for right now?
▶ What is something funny that happened?

The check-in led to excellent team work for those students that
showed up.
In 2025 I made a few tweaks. One change was the grading of the
project, I used github actions to do the GDS,DRC,LVS,SIM and
docs. The grading did not really work that well, although, it was a
good way to get students to get the designs correct on github. The
first milestones with the sim and the doc did not work. The last
milestone actions worked well.
For 2026 I should do the following changes:

▶ Wait until after M0 for group selection

▶ Talk about layout early. Force full M0 tutorial
▶ Make them do TR layout early
▶ Re-introduce milestone 3
▶ Write a detailed project description and milestone and ex-
pectation description
▶ Reduce time for milestone 1. Maybe make a ready schematic
hierarchy to force names? ideal OTA?
▶ Find a good sigma delta intro circuit
▶ Add to analog systemverilog

I love programming and automation. Not much makes me more

happy than using the same source (the slide markdowns), to
generate the lecture notes, to translate into the book your looking
at right now.
If you find an error in what I’ve made, then fork aic2024, fix ,
commit, push and create a pull request. That way, we use the
global brain power most efficiently, and avoid multiple humans
spending time on discovering the same error.
 Introduction 2
2.1 Who . . . . . . . . . . . 3
2.1 Who
2.2 How I see our roles . . 3
2.3 I want you to learn
My name is the skills necessary to
make your own ICs . . 4
Carsten Wulff carstenw@[Link] 2.4 There will always be
analog circuits, be-
I finished my Masters in 2002, and did a Ph.D on analog-to-digital cause the real world is
converters finished in 2008. analog . . . . . . . . . . 5
2.4.1 Will you tape-out an
Since that time, I’ve had a three axis in my work/hobby life. IC? . . . . . . . . . . . . 6
2.4.2 What the team needs to
I work at Nordic Semiconductor where I’ve been since 2008. The know to design ICs . . 6
first 7 years I did analog design (ADCs, DC/DCs, GPIO). The next 2.4.3 Zen of IC design (stolen
7 years I was the Wireless Group Manager. The Wireless group from Zen of Python) . 7
make most of the analog and RF designs for Nordic’s short-range 2.4.4 IC design mantra . . . 8
products. Now I’m the IC Scientist, and focus on technical issues 2.4.5 Analog Design Process 8
with our integrated circuits that occur before we go into volume 2.5 My Goal . . . . . . . . . 8
production. 2.6 Syllabus . . . . . . . . . 9
2.7 JNW (2025) . . . . . . . 10
I work at NTNU where I did a part time postdoc from 2014 - 2017. 2.7.1 Grading . . . . . . . . . 12
From 2020 I’ve been working on and teaching Advanced Integrated 2.7.2 Group dynamics . . . . 12
Circuits 2.8 Software . . . . . . . . 13

I have a hobby trying to figure out how to make a new analog

circuit design paradigm. The one we have today with schemat-
ic/simulation/layout/verification/simulation is too slow
Summer intern First book University
Mom died chapter
NTNU of
Toronto
Started NTNU First paper, 2. dan ITF
Bought first Started Taekwon-do Compiled
Aruba
book on 1. dan ITF Met ex wife Nordic ADC,
electronics Senior R & D Wireless ESSCIRC16
Taekwon-do
Finished group
A year in Master Started Ph.D engineer
manager
Army, HTV Ph.D [Link]
Australia Got [Link] End
Son Twins Start Rando Associate
Born First PC Married Divorced
born born Professor IC Scientist
6a

1976 1986 1991 1996 2001 2006 2011 2016 2021 2026
Compiled
RX_ADC, ADC,JSSC
nRF52 SAADC,
ADC, nRF52 DC/DC Bluetooth
nRF51 DC/DC, nRF91 SIG CSWG
nRF52

2.2 How I see our roles

Professors: Guide students on what is impossible, possible, and

hints on what might be possible

Ph.D students: Venture into the unknown and make something

(more) possible

Master students: Learn all that is currently possible

Bachelor students: Learn how to make complicated into easy

4 2 Introduction

Industry: Take what is possible, and/or complicated, and make it

easy

2.3 I want you to learn the skills necessary to

make your own ICs

In 2020 the global integrated circuit market was 437.7 billion

dollars! The market is expected to grow to 1136 billion in 2028.

Integrated circuits enable pretty much all technologies.

I will be dead in approximately 50 years, and will retire in approx-

imately 20 years. Everything I know will be gone (except for the
small pieces I’ve left behind in videos or written word)

Someone must take over, and to do that, they need to know most
of what I know, and hopefully a bit more.

That’s were some of you come in. Some of you will find integrated
circuits interesting to make, and in addition, you have the stamina,
patience, and brain necessary to learn some of the hardest topics
in the world.

Making integrated circuits (that work reliably) is not

rocket science, it’s much harder.

In this course, we’ll focus on analog ICs, because the real world is
analog, and all ICs must have some analog components, otherwise
they won’t work.
 2.4 There will always be analog circuits, because the real world is analog 5

2.4 There will always be analog circuits,

because the real world is analog

Status Abstraction Design Layout Why

:construction: Chip SystemVerilogdigital Complex connections, few analog
interfaces
:construction: Module SystemVerilogdigital Large amount of digital signals, few
analog signals
:warning: Block Schematic programmatic
Large amount of critical analog
interfaces, few digital
:white_- Cell Netlist/JSONcompiled Few analog interfaces, few digital
check_- interfaces
mark:
:white_- Device JSON compiled Polygon pushing
check_-
mark:
:white_- Technology JSON/Rules compiled Custom for each technology
check_-
mark:

[Link]
-world-is-analog/

The steps to make integrated circuits is split in two. We have an

analog flow, and a digital flow.

It’s rare to find a single human that do both flows well. Usually
people choose, and I think it’s based on what they like and their
personality.

If you like the world to be ordered, with definite answers, then it’s
likely that you’ll find the digital flow interesting.
6 2 Introduction

If you’re comfortable with not knowing, and an insatiable desire

to understand how the world really works at a fundamental level,
then it’s likely that you’ll find analog flow interesting.

Idea

Analog Design
Xschem

Analog Model Analog Simulation

SystemVerilog ngspice

Digital Design Analog Layout

SystemVerilog Magic

Digital Simulation LVS

iverilog/vpp/verilator/gtkwave netgen

Parasitics
GDSII
Magic

RTL to GDSII
OpenLane

Tapeout

2.4.1 Will you tape-out an IC?

Something that would make me really happy is if someone is able

to tapeout an IC in this course.

It’s now possible without signing an NDA or buying expensive

software licenses.

In 2020 Google and Skywater joined forces to release a 130 nm

process design kit to the public. In addition, they have fueled a
renaissance of open source software tools.

Together with Efabless there are cheap alternatives, like tinytapeout,

which makes it possible for a private citizen to tape-out their own
integrated circuit.

2.4.2 What the team needs to know to design ICs

There are a multitude of tools and skills needed to design pro-

fessional ICs. It’s not likely that you’ll find all the skills in one
human, and even if you could, one human does not have suffi-
cient bandwidth to design ICs with all it’s aspects in a reasonable
timeline

That is, unless we can find a way to make ICs easier.

 2.4 There will always be analog circuits, because the real world is analog 7

The skills needed are

▶ Project flow support: Confluence, JIRA, risk management

(DFMEA), failure analysis (8D)
▶ Language: English, Writing English (Latex, Word, Email)
▶ Psychology: Personalities, convincing people, presentations
(Powerpoint, Deckset), stress management (what makes
your brain turn off?)
▶ DevOps: Linux, bulid systems (CMake, make, ninja), con-
tinuous integration (bamboo, jenkins), version control (git),
containers (docker), container orchestration (swarm, kuber-
netes)
▶ Programming: Python, C, C++, Matlab Since 1999 I’ve pro-
grammed in Python, Go, Visual BASIC, PHP, Ruby, Perl, C#,
SKILL, Ocean, Verilog-A, C++, BASH, AWK, VHDL, SPICE,
MATLAB, ASP, Java, C, SystemC, Verilog, Assembler, and
probably a few I’ve forgotten.
▶ Firmware: signal processing, algorithms, software architec-
ture, security
▶ Infrastructure: Power management, reset, bias, clocks
▶ Domains: CPUs, peripherals, memories, bus systems
▶ Sub-systems: Radio’s, analog-to-digital converters, compara-
tors
▶ Blocks: Analog Radio, Digital radio baseband
▶ Modules: Transmitter, receiver, de-modulator, timing recov-
ery, state machines
▶ Designs: Opamps, amplifiers, current-mirrors, adders, ran-
dom access memory blocks, standard cells
▶ Tools: schematic, layout, parasitic extraction, synthesis, place-
and-route, simulation, (System)Verilog, netlist
▶ Physics: transistor, pn junctions, quantum mechanics

2.4.3 Zen of IC design (stolen from Zen of Python)

When you learn something new, it’s good to listen to someone that
has done whatever it is before.
Here is some guiding principles that you’ll likely forget.

▶ Beautiful is better than ugly.

▶ Explicit is better than implicit.
▶ Simple is better than complex.
▶ Complex is better than complicated.
▶ Readability counts (especially schematics).
▶ Special cases aren’t special enough to break the rules.
▶ Although practicality beats purity.
▶ In the face of ambiguity, refuse the temptation to guess.
▶ There should be one and preferably only one obvious way
to do it.
▶ Now is better than never.
▶ Although never is often better than right now.
8 2 Introduction

▶ If the implementation is hard to explain, it’s a bad idea.

▶ If the implementation is easy to explain, it may be a good
idea.

2.4.4 IC design mantra

To copy an old mantra I have on learning programming

Find a problem that you really want to solve, and learn

programming to solve it. There is no point in saying
“I want to learn programming”, then sit down with a
book to read about programming, and expect that you
will learn programming that way. It will not happen.
The only way to learn programming is to do it, a lot. –
Carsten Wulff

And run the perl program

s/programming/analog design/ig

2.4.5 Analog Design Process

▶ Define the problem, what are you trying to solve?

▶ Find a circuit that can solve the problem (papers, books)
▶ Find right transistor sizes. What transistors should be weak
inversion, strong inversion, or don’t care?
▶ Write a verification plan. Plan to simulate everything that
could go wrong.
▶ Check operating region of transistors (.op)
▶ Check key parameters (.dc, .ac, .tran)
▶ Check function. Exercise all inputs. Check all control signals
▶ Check key parameters in all corners. Check mismatch (Monte-
Carlo simulation)
▶ Do layout, and check it’s error free. Run design rule checks
(DRC). Check layout versus schematic (LVS)
▶ Extract parasitics from layout. Resistance, capacitance, and
inductance if necessary.
▶ On extracted parasitic netlist, check key parameters in all
corners and mismatch (if possible).
▶ If everything works, then your done.

On failure, go back as far as necessary

2.5 My Goal

Don’t expect that I’ll magically take information and put it inside
your head, and you’ll suddenly understand everything about
making ICs.
 2.6 Syllabus 9

You are the one that must teach yourself everything.

I consider my role as a guide, similar to a mountain guide. I can’t

carry you up the mountain, you need to walk up the mountain ,
but I know the safe path to take and increase the likelihood that
you’ll come back alive.

I want to:

▶ Enable you to read the books on integrated circuits

▶ Enable you to read papers (latest research)
▶ Correct misunderstandings on the topic
▶ Answer any questions you have on the chapters

I’m not a mind reader, I can’t see inside your head. That means,
you must ask questions, only by your questions can I start to
understand what pieces of information is missing from your head,
or maybe somehow to correct your understanding.

At the same time, and similar to a mountain guide, you should not
assume I’m always right. I’m human, and I will make mistakes.
And maybe you can correct my understanding of something. All I
care about is to really understand how the world works, so if you
think my understanding is wrong, then I’ll happily discuss.

2.6 Syllabus

The syllabus will be from Analog Integrated Circuit Design (CJM)

and Circuits for all seasons.

These lecture notes are a supplement to the book. I try to give some
background, and how to think about electronics. It’s not my goal
to repeat information that you can find in the book.

Buy a hard-copy of the book if you don’t have that. Don’t expect to
understand the book by reading the PDF.
10 2 Introduction

2.7 JNW (2025)

“You can use logic to justify almost anything. That’s its power.
And its flaw.” - Kathryn Janeway, Star Trek Voyager: Prime Fac-
tors

The project for 2025 is to

Design a integrated temperature sensor with digital read-out

An outline of the plan is shown below.

At the end of the project you will have a function that converts
temperature to a digital value.

𝐷 = 𝑓0 (𝑇)

I’ve broken down the challenge into three steps, first convert
Temperature into a current

𝐼 = 𝑓1 (𝑇)

Then convert current into a time

𝑡 = 𝑓2 (𝐼)

then time to digital

 2.7 JNW (2025) 11

𝐷 = 𝑓3 (𝑡) = 𝑓3 ( 𝑓2 ( 𝑓1 (𝑇))) = 𝑓0 (𝑇)

The third milestone is the layout, while the fourth milestone is the
report.

You can find an example of last years designs at cnr_gr02_-

sky130nm

You will be using a repository on github for all your design data.
In that repository I’ve made it possible to run github actions, or
github workflows. For each of the milestones there are associated
workflows (SIM/DOCS/GDS/DRC/LVS).

MI MY
RESET
I Emmet Report PDF
Pursue b
put 1414
Anna i
µ
REPO
Layout

M3

Milestone 0: The zero milestone is not really part of the project, but
it does introduce you too how you will work with the files in the
project. It’s important that you do this right away. To complete the
milestone, upload a link to blackboard with your github repository
for the tutorial Skywater 130 nm Tutorial

Milestone 1: The first milestone is to make a circuit that can convert

from a temperature, to a current that is proportional to temperature.
You will run a simulation on github that demonstrates that the
circuit works. That is the SIM workflow.

Milestone 2: In the second milestone you will complete the

schematic design of the circuit, and possibly also do some Sys-
temVerilog to demonstrate that you get a digital value out that
is proportional to temperature. Here, the simulations on github
may be too long, so it’s sufficient to describe the circuit, and how it
works in detail in the documentation. This is the DOC workflow.

Milestone 3: The third milestone, making the layout, is optional,

however, it will be impossible to get an A without getting some
points from the layout milestone. Once the layout is complete, I
expect that the design rule checks (DRC), Layout versus Schematic
(LVS), and GDS (stream out to a GDSII file) is passing on github.

Milestone 4: I will force you to work in groups. As such, it may be

that some contribute more than others. To ensure that the grading
is fair, the report will be individual. It’s OK to share figures, tables,
and so on, but the PDF shall be written by you and you alone.
12 2 Introduction

2.7.1 Grading

Condition for more Possible

Milestone What does it mean than 0 points Points
M1 Circuit that can convert a temperature SIM passing 10
I=f(T) into a current
M2 Circuit that can convert from DOC passing 20
D=f(T) temperature into a digital value
M3 Layout of your circuit DRC/LVS/GDS 20
Lay- passing
out
M4 Individual report Uploaded to 48
Re- blackboard
port
Coolness Extra points that I may choose to award 10
Total 108

2.7.2 Group dynamics

How you work together is important. No-one can do everything by

them self. I know from experience it can be magical when bright
brains come together. The collective brain can be smarter, better,
faster, than anyone in the group.

That’s why I think it’s important not to just work in groups, but
also focus on how we work in groups.

A group shall be maximum 4 members. There must be at least 3

that don’t know each-other that well.

The group will meet once per week in the exercise hours.

[Link] Check-in

All group session must start with a Check-in (10 minutes)

Some example questions could be

▶ Share one thing that is going on in your life (personal or

professional.)
▶ What is one thing that you are grateful for right now?
▶ What is something funny that happened?

Some examples answers could be: - My dog died yesterday, so

I’m not feeling great today. - I woke up early, had an omelet, and
went running, so I feel motivated and fantastic. - I feel blaaah today,
motivation is lacking. - I went running yesterday and did not
discover before I got home that I’d forgotten to put my pants on,
even though it was -10 C.

The point of this exercise is to get to know each other a bit, and
attempt to create psychological safety in the group.
 2.8 Software 13

2.8 Software

We’ll use professional Open source software (xschem, ngspice,

sky130A PDK, Magic VLSI, netgen)
I’ve made a rather detailed (at least I think so myself) tutorial on
how to make a current mirror with the open source tools. I strongly
recommend you start with that first.
Skywater 130 nm Tutorial
I’ve also made some more complex examples, that can be found at
the link below. There are digital logic cells, standard transistors,
and few other blocks.
aicex
 A Refresher 3
3.1 There are standard units of measurement 3.1 There are standard
units of measurement 15
3.2 Electrons . . . . . . . . . 16
All known physical quantities are derived from 7 base units (SI 3.3 Probability . . . . . . . 16
units) 3.4 Uncertainty principle . 17
▶ second (s) : time 3.5 States as a function of
time and space . . . . . 17
▶ meter (m) : space
3.6 Allowed energy levels
▶ kg (kilogram) : weight
in atoms . . . . . . . . . 18
▶ ampere (A) : current
3.7 Allowed energy levels
▶ kelvin (K) : temperature
in solids . . . . . . . . . 18
▶ candela (cd) : luminous intensity
3.8 Silicon Unit Cell . . . . 19
All other units (for example volts), are derived from the base 3.9 Band structure . . . . . 20
units. 3.10 Valence band and
Conduction band . . . 21
I don’t go around remembering all of them, they are easily available 3.11 Fermi level . . . . . . . 21
online. When you forget the equation for charge (Q), voltage (V) 3.12 Metals . . . . . . . . . . 22
and capacitance (C), look at the units below, and you can see it’s
3.13 Insulators . . . . . . . . 22
𝑄 = 𝐶𝑉 ‗
3.14 Semiconductors . . . . 23
3.15 Band diagrams . . . . . 23
3.16 Density of electrons/-
holes . . . . . . . . . . . 23
3.17 Fields . . . . . . . . . . . 24
3.18 Permittivity and Per-
meability . . . . . . . . 24
3.19 Quantum electrody-
namics . . . . . . . . . . 25
3.20 Voltage . . . . . . . . . . 25
3.21 Current . . . . . . . . . 25
3.22 Drift current . . . . . . 26
3.23 Diffusion current . . . 27
3.24 Why are there two
currents? . . . . . . . . . 27
3.25 Currents in a semicon-
ductor . . . . . . . . . . 27
3.26 Resistors . . . . . . . . . 28
3.27 Capacitors . . . . . . . . 28
3.28 Inductors . . . . . . . . 28

Figure 1: Si base units, from [Link]

etric-si/si-units
‗ Although you do have to keep your symbols straight. We use “C” for Capacitance,

but C can also mean Columbs. Context matters.

16 3 A Refresher

3.2 Electrons

Electrons are fundamental, they cannot (as far as we know), be

divided into smaller parts. Explained further in the standard model
of particle physics

Standard Model of Elementary Particles

three generations of matter interactions / force carriers
(fermions) (bosons)
I II III
mass ≈2.2 MeV/c² ≈1.28 GeV/c² ≈173.1 GeV/c² 0 ≈125.11 GeV/c²
charge ⅔ ⅔ ⅔ 0 0
spin ½ u ½ c ½ t 1 g 0 H
up charm top gluon higgs

SCALAR BOSONS
QUARKS

≈4.7 MeV/c² ≈96 MeV/c² ≈4.18 GeV/c² 0

γ
−⅓ −⅓ −⅓ 0
½ d ½ s ½ b 1

down strange bottom photon

≈0.511 MeV/c² ≈105.66 MeV/c² ≈1.7768 GeV/c² ≈91.19 GeV/c²

GAUGE BOSONS
μ τ
−1 −1 −1 0
½ e ½ ½ 1 Z
electron muon tau Z boson

VECTOR BOSONS
LEPTONS

<1.0 eV/c² <0.17 MeV/c² <18.2 MeV/c² ≈80.360 GeV/c²

0
½ νe 0
½ νμ 0
½ ντ ±1
1 W
electron muon tau
neutrino neutrino neutrino
W boson

Figure 2: Standard model of particle physics, Wikipedia

Electrons have a negative charge of 𝑞 ≈ 1.602 × 10−19 . The proton

a positive charge. The two charges balance exactly! If you have
a trillion electrons and a trillion protons inside a volume, the
net external charge will be 0 (assuming we measure from some
distance away). I find this fact absolutely incredible. There must be
a fundamental connection between the charge of the proton and
electron. It’s insane that the charges balance out so exactly.

All electrons are the same, although the quantum state can be
different.

An electron cannot occupy the same quantum state as another.

This rule that applies to all Fermions (particles with spin of 1/2)

The quantum state of an electron is fully described by it’s spin,

momentum (p) and position in space (r).

3.3 Probability

The probability of finding an electron in a state as a function of

space and time is
 3.4 Uncertainty principle 17

𝑃 = |𝜓(𝑟, 𝑡)|2

, where 𝜓 is named the probability amplitude, and is a complex

function of space and time. In some special cases, it’s

𝜓(𝑟, 𝑡) = 𝐴𝑒 𝑖(𝑘𝑟−𝜔𝑡)

, where A is complex number, k is the wave number, r is the position

vector from some origin, 𝜔 is the frequency and 𝑡 is time.
The energy is 𝐸 = ℏ𝜔 , where ℏ = ℎ/2𝜋 and ℎ is Planck Constant
and the momentum is 𝑝 = ℏ𝑘
The probability amplitude is also called the wave function. Type
of wave function depends on the scenario, and does not have to
take on the solution above. The possible wave functions are those
equations that fits with the time evolution of quantum states given
by the Schrodinger equation.

3.4 Uncertainty principle

We cannot, with ultimate precision, determine both the position

and the momentum of a particle, the precision is

ℏ
𝜎𝑥 𝜎𝑝 ≥
2

From the uncertainty (Unschärfe) principle we can actually estimate

the size of the atom

3.5 States as a function of time and space

The time-evolution of the probability amplitude is

𝑑
𝑖ℏ 𝜓(𝑟, 𝑡) = 𝐻𝜓(𝑟, 𝑡)
𝑑𝑡

, where H is named the Hamiltonian matrix, or the energy matrix or

(if I understand correctly) the amplitude matrix of the probability
amplitude to change from one state to another.
For example, if we have a system with two states, a simplified
version of two electrons shared between two atoms, as in 𝐻2 , or
hydrogen gas, or co-valent bonds, then the Hamiltonian is a 2 x 2
matrix. And the 𝜓 is a vector of [𝜓1 , 𝜓2 ]
Computing the solution to the Schrodinger Equation can be tricky,
because you must know the number of relevant states to know the
18 3 A Refresher

vector size of 𝜓 and the matrix size of 𝐻 . In addition, the 𝐻 can be

a function of time and space (I think).

Compared to the equations of electric fields, however, Schrodinger

is easy, it’s a set of linear differential equations.

3.6 Allowed energy levels in atoms

Solutions to Schrodinger result in quantized energy levels for an

electron bound to an atom.

Take hydrogen, the electron bound to the proton can only exists
in quantized energy levels. The lowest energy state can have two
electrons, one with spin up, and one with spin down.

From Schrodinger you can compute the energy levels, which most
of us did at some-point, although now, I can’t remember how it
was done. That’s not important. The important is to internalize
that the energy levels in bound electrons are discrete.

Electrons can transition from one energy level to another by external

influence, i.e temperature, light, or other.

The probability of a state transition (change in energy) can be

determined from the probability amplitude and Schrodinger.

3.7 Allowed energy levels in solids

If I have two silicon atoms spaced far apart, then the electrons can
have the same spin and same momentum around their respective
nuclei. As I bring the atoms closer, however, the probability am-
plitudes start to interact (or the dimensions of the Hamiltonian
matrix grow), and there can be state transitions between the two
electrons.

The allowed energy levels will split. If I only had two states
interacting, the Hamiltonian could be

𝐴 0
 
𝐻=
0 −𝐴

and the new energy levels could be

𝐸1 = 𝐸0 + 𝐴

and

𝐸2 = 𝐸0 − 𝐴
 3.8 Silicon Unit Cell 19

In a silicon crystal we can have trillions of atoms, and those that

are close, have states that interact. That’s why crystals stay solids.
All chemical bonds are states of electrons interacting! Some are
strong (co-valent bonds), some are weaker (ionic bonds), but it’s
all quantum states interacting.

The discrete energy levels of the electron transition into bands of

allowed energy states.

Figure 3: Electronic band structure, Wikipedia

For a crystal, the allowed energy bands is captured in the band

structure

3.8 Silicon Unit Cell

A silicon crystal unit cell is a diamond faced cubic with 8 atoms in

the corners spaced at 0.543 nm, 6 at the center of the faces, and 4
atoms inside the unit cell at a nearest neighbor distance of 0.235
nm.
20 3 A Refresher

Figure 4: Silicon, Wikipedia

3.9 Band structure

The full band structure of a silicon unit cell is complicated, it’s a 3

dimensional concept

Figure 5: Silicon Band Structure

 3.10 Valence band and Conduction band 21

3.10 Valence band and Conduction band

For bulk silicon we simplify, and we think of two bands, the

conduction band, and valence band
In the conduction band (𝐸𝐶 ) is the lowest energy where electrons
are free (not bound to atoms). The valence band (𝐸𝑉 ) is the highest
band where electrons are bound to silicon atoms.
The difference between 𝐸𝐶 and 𝐸𝑉 is a property of the material
we’ve named the band gap.

𝐸𝐺 = 𝐸𝐶 − 𝐸𝑉

3.11 Fermi level

From Wikipedia’s Fermi level

In band structure theory, used in solid state physics to

analyze the energy levels in a solid, the Fermi level can
be considered to be a hypothetical energy level of an
electron, such that at thermodynamic equilibrium this
energy level would have a 50% probability of being
occupied at any given time

The Fermi level is closely linked to the Fermi-Dirac distribution

1
𝑓 (𝐸) =
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 +1

If the energy of the state is more than a few kT away from the
Fermi-level, then

𝑓 (𝐸) ≈ 𝑒 (𝐸𝐹 −𝐸)/𝑘𝑇

The equation above is one of the reasons the structure 𝑒 𝐸/𝑘𝑇 or

𝑒 𝑞𝑉/𝑘𝑇 shows up all over the place. You’ll see it in the equations
for current in a diode, 𝐼𝐷 = 𝐼 𝑠 (𝑒 𝑞𝑉𝐷 /𝑛 𝑘𝑇 − 1), the subthreshold
conduction of a mosfet 𝐼𝐷 ∝ 𝑒 𝑞𝑉𝑔𝑠 /𝑛 𝑘𝑇 and even the Arrhenius
Equation 𝑘 = 𝐴𝑒 −𝐸 𝑎 /𝑘𝑇 .
It seems like any time you have something related to chemical
reactions (state transitions of electrons, breaking bonds, forming
bonds), or current in solids, there is a relation to the equation
above. To me, that makes sense.
The Fermi-Dirac function also explains why there are more free
carriers, and reaction rates increase, at high temperature. The
part of the equation that is 𝑒 −𝐸/𝑘𝑇 will approach one at high
temperatures.
22 3 A Refresher

3.12 Metals

In metals, the band splitting of the energy levels causes the valence
band and conduction band to overlap.

Figure 6: Band splitting in materials. Electronic Band Structure,

Wikipedia

Electrons can easily transition between bound state and free state.
As such, electrons in metals are shared over large distances, and
there are many electrons readily available to move under an applied
field, or difference in electron density. That’s why metals conduct
well.

3.13 Insulators

In insulating materials the difference between the conduction band

and the valence band is large. As a result, it takes a large energy to
excite electrons to a state where they can freely move.

That’s why glass is transparent to optical frequencies. Visible light

does not have sufficient energy to excite electrons from a bound
state.

That’s also why glass is opaque to ultra-violet, which has enough

energy to excite electrons out of a bound state.

Based on these two pieces of information you could estimate the

bandgap of glass.

from scipy import constants

#- We must use the "correct" units for planck's constant to get energy in eV
h = constants.physical_constants["Planck constant in eV/Hz"][0]
c = constants.physical_constants["speed of light in vacuum"][0]

lambda_optical = 450e-9
e_optical = h * c/lambda_optical

lambda_ultra = 380e-9
e_ultra = h * c/lambda_ultra

print("Bandgap of glass is above %.2f eV, maybe around %.2f eV " %(e_optical,e_ultra))
 3.14 Semiconductors 23

3.14 Semiconductors

In silicon the bandgap is lower than an insulator, approximately

𝐸𝐺 = 1.12 𝑒𝑉

At room temperature, that allows a small number of electrons to

be excited into the conduction band, leaving behind a “hole” in
the valence band.

3.15 Band diagrams

A band diagram or energy level diagrams shows the conduction

band energy and valence band energy as a function of distance in
the material.

Figure 7: Band diagram of a PN junction, Wikipedia

The horizontal axis is the distance in the material, the vertical axis
is the energy.

3.16 Density of electrons/holes

There are two components needed to determine how many elec-

trons are in the conduction band. The density of available states,
and the probability of an electron to be in that quantum state.

The probability is the Fermi-Dirac distribution. The density of

available states is a complicated calculation from the band-structure
of silicon.

For details see the Diodes chapter.

∫ ∞
𝑛𝑒 = 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸
𝐸𝐶

The Fermi level is assumed to be independent of energy level, so

we can write
24 3 A Refresher

∫ ∞
𝐸𝐹 /𝑘𝑇
𝑛𝑒 = 𝑒 𝑁(𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶

for the density of electrons in the conduction band.

3.17 Fields

There are equations that relate electric field, magnetic field, charge
density and current density to each-other.

∮ ∭
1
E · 𝑑S = 𝜌 · 𝑑𝑉
𝜕Ω 𝜖0 𝑉

,relates net electric flux to net enclosed electric charge

∮
B · 𝑑S = 0
𝜕Ω

,relates net magnetic flux to net enclosed magnetic charge

𝑑
∮ ∬
E · 𝑑ℓ = − B · 𝑑S
𝜕Σ 𝑑𝑡 Σ

,relates induced electric field to changing magnetic flux

𝑑
∮ ∬ ∬ 
B · 𝑑ℓ = 𝜇0 J · 𝑑S + 𝜖0 E · 𝑑S
𝜕Σ Σ 𝑑𝑡 Σ

,relates induced magnetic field to changing electric flux and to

current

These are the Maxwell Equations, and are non-linear time depen-
dent differential equations.

Under the best of circumstances they are fantastically hard to solve!

But it’s how the real world works.

3.18 Permittivity and Permeability

The permittivity of free space is defined as

1
𝜖0 =
𝜇0 𝑐 2

, where 𝑐 is the speed of light, and 𝜇0 is the vacuum permeability,

which, in SI units, is now
 3.19 Quantum electrodynamics 25

2𝛼 ℎ
𝜇0 =
𝑞2 𝑐

, where 𝛼 is the fine structure constant.

3.19 Quantum electrodynamics

The quantum electrodynamics (QED) is a full description of in-

teractions between light and matter. The equations describe both
quantum mechanical effects, electromagnetism and is in agreement
with special relativity.

The equations are rather complicated, but it’s based on Lagrangian

physics. Maxwell’s equations actually fall out of the QED La-
grangian when one assumes local phase symmetry.

The QED Lagrangian is

¯
L = 𝜓[𝑖ℏ𝑐𝛾 𝜇 ¯ 𝜇 𝜓]𝐴𝜇 − 1 𝐹𝜇𝜈 𝐹 𝜇𝜈
𝜕𝜇 − 𝑚𝑐 2 ]𝜓 − 𝑞[𝜓𝛾
16𝜋

For more information, have a look at Electromagnetism as a Gauge

Theory

3.20 Voltage

The electric field has units voltage per meter, so the electric field is
the derivative of the voltage as a function of space.

𝑑𝑉
𝐸=
𝑑𝑥

3.21 Current

Current has unit 𝐴 and charge 𝐶 has unit 𝐴𝑠 , so the current is the
number of charges passing through a volume per second.

The current density 𝐽 has units 𝐴/𝑚 2 and is often used, since we
can multiply by the surface area of a conductor, if the current
density is uniform.

𝐼 = Area × 𝐽
26 3 A Refresher

3.22 Drift current

Charge carriers (electrons, holes, ions) in an electric field will give

rise to a drift current.

We know from Newtons laws that force equals mass times acceler-
ation

𝐹® = 𝑚®𝑎

If we assume a zero, or constant magnetic field, the force on a

particle is

𝐹® = 𝑞 𝐸®

The current density is then

®𝐽 = 𝑞 𝐸® × 𝑛 × 𝜇

where 𝑛 is the charge density, and 𝜇 is the mobility (how easily the
charges move) and has units 𝑚 2 /𝑉 𝑠

Assuming

𝐸 = 𝑉/𝑚

, we could write

𝐶 𝑉 𝑚2 𝐶
𝐽= = 𝑚 −2
𝑚 𝑚 𝑉𝑠
3 𝑠

So multiplying by an area A with unit meters squared

𝐼 = 𝑞𝑛𝜇𝐴𝑉

and we can see that the conductance

𝐺 = 𝑞𝑛𝜇𝐴

, and since

𝐺 = 1/𝑅

, where R is the resistance, we have

𝐼 = 𝐺𝑉 ⇒ 𝑉 = 𝑅𝐼
 3.23 Diffusion current 27

Or Ohms law

3.23 Diffusion current

A difference in charge density will give rise to a diffusion current.

The current density is

𝑑𝜌
𝐽 = −𝑞𝐷𝑛
𝑑𝑥

,where 𝐷𝑛 is a diffusion constant, and 𝜌 is the charge density.

3.24 Why are there two currents?

I struggled with the concepts diffusion current and drift current

for a long time. Why are there two types of current? It was when I
read The Schrödinger Equation in a Classical Context: A Seminar
on Superconductivity I realized that the two types of current come
directly from the Schrodinger equation, there is one component
related to the electric field (potential energy) and a component
related to the momentum (kinetic energy).

In the absence of an electric field electrons will still jump from

state to state set by the probabilities of the Hamiltonian. If there
are more electrons in an area, then it will seem like there is an
average movement of charges away from that area. That’s how I
think about drift and diffusion currents. We can kinda see it from
the Schrödinger equation below.

ℏ2 𝜕 2 𝜕
− 𝜓(𝑥, 𝑡) + 𝑉(𝑥)𝜓(𝑥, 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡)
2𝑚 𝜕 𝑥
2 𝜕𝑡

3.25 Currents in a semiconductor

Both electrons, and holes will contribute to current.

Electrons move in the conduction band, and holes move in the

valence band.

Both holes and electrons can only move if there are available
quantum states.

For example, if the valence band is completely filled (all states

filled), then there can be no current.

To compute the total current in a semiconductor one must com-

pute
28 3 A Refresher

𝐼 = 𝐼𝑛 𝑑𝑟𝑖 𝑓 𝑡 + 𝐼𝑛 𝑑𝑖 𝑓 𝑓 𝑢𝑠𝑖𝑜𝑛 + 𝐼 𝑝 𝑑𝑟𝑖 𝑓 𝑡 + 𝐼 𝑝 𝑑𝑖 𝑓 𝑓 𝑢𝑠𝑖𝑜𝑛

where 𝑛 denotes electrons, and 𝑝 denote holes.

3.26 Resistors

We can make resistors with many materials. The behavior of the

charge carrier may be different between materials.
In metal the dominant carrier depends on the metal, but it’s usually
electrons. As such, one can often ignore the hole current.
In a semiconductor the dominant carrier depends on the Fermi
level in relation to the conduction band and valence band.
If the Fermi level is close to the valence band the dominant carrier
will be holes. If the Fermi level is close to the conduction band, the
dominant carrier will be electrons.
That’s why we often talk about “majority carriers” and “minority
carriers”, both are important in semiconductors.

3.27 Capacitors

A capacitor resists a change in voltage

𝑑𝑉
𝐼=𝐶
𝑑𝑡

and store energy in an electric field between two conductors with

an insulator between.

3.28 Inductors

An inductor resist a change in current

𝑑𝐼
𝑉=𝐿
𝑑𝑡

and store energy in the magnetic fields in a loop of a conductor.

 Diodes 4
4.1 Why 4.1 Why . . . . . . . . . . . 29
4.2 Silicon . . . . . . . . . . 29
4.3 Intrinsic carrier con-
Diodes are a magical ‗ semiconductor device that conduct current centration . . . . . . . . 31
in one direction. It’s one of the fundamental electronics components, 4.4 It’s all quantum . . . . 32
and it’s a good idea to understand how they work. 4.4.1 Density of states . . . . 34
4.4.2 How to think about
If you don’t understand diodes, then you won’t understand tran-
electrons (and holes) . 36
sistors, neither bipolar, or field effect transistors.
4.5 Doping . . . . . . . . . 37
A useful feature of the diode is the exponential relationship between 4.6 PN junctions . . . . . . 38
the forward current, and the voltage across the device. 4.6.1 Built-in voltage . . . . . 38
4.6.2 Current . . . . . . . . . 39
To understand why a diode works it’s necessary to understand the 4.6.3 Forward voltage tem-
physics behind semiconductors. perature dependence . 41
4.6.4 Current proportional to
This paper attempts to explain in the simplest possible terms how temperature . . . . . . . 42
a diode works † 4.7 Equations aren’t real . 43

4.2 Silicon

Integrated circuits use single crystalline silicon. The silicon crystal

is grown with the Czochralski method which forms a ingot that is
cut into wafers. The wafer is a regular silicon crystal, although, it
is not perfect.
A silicon crystal unit cell, as seen in Figure 1 is a diamond faced
cubic with 8 atoms in the corners spaced at 0.543 nm, 6 at the
center of the faces, and 4 atoms inside the unit cell at a nearest
neighbor distance of 0.235 nm.

‗ It doesn’t stop being magic just because you know how it works. Terry Pratchett,

The Wee Free Men

† Simplify
as much as possible, but no more. Einstein
30 4 Diodes

Figure 1: Silicon crystal unit cell

As you hopefully know, the energy levels of an electron around

a positive nucleus are quantized, and we call them orbitals (or
shells). For an atom far away from any others, these orbitals, and
energy levels are distinct. As we bring atoms closer together, the
orbitals start to interact, and in a crystal, the distinct orbital energies
split into bands of allowed energy states. No two electrons, or any
Fermion (spin of 1/2), can occupy the same quantum state. We call
the outermost “shared” orbitial, or band, in a crystal the valence
band. Hence covalent bonds.

If we assume the crystal is perfect, then at 0 Kelvin all electrons

will be part of covalent bonds. Each silicon atom share 4 electrons
with its neighbors. What we really mean when we say “share 4
electrons” is that the wave-functions of the outer orbitals interact,
and we can no longer think of the orbitals as belonging to either of
the silicon nuclei. All the neighbors atoms “share” electrons, and
nowhere is there an vacant state, or a hole, in the valence band.

If such a crystal were to exist, where there were no holes in

the valence band, and a net neutral charge, the crystal could
not conduct any drift current. Electrons would move around
continuously, swapping states, but there could be no net drift of
charge carriers.

In an atom, or a crystal, there are also higher energy states where

the carriers are “free” to move. We call these energy levels, or bands
of energy levels, conduction bands. In singular form “conduction
band”, refers to the lowest available energy level where the electrons
are free to move.
 4.3 Intrinsic carrier concentration 31

Due to imperfectness of the silicon crystal, and non-zero temper-

ature, there will be some electrons that achieve sufficient energy
to jump to the conduction band. The electrons in the conduction
band leave vacant states, or holes, in the valence band.

Electrons can move both in the conduction band, as free electrons,

and in the valence band, as a positive particle, or hole. Both bands
can support drift and diffusion currents.

4.3 Intrinsic carrier concentration

The intrinsic carrier concentration of silicon, or the density of free

electrons and holes at a given temperature, is given by

𝑁𝑐 𝑁𝑣 𝑒 −𝐸 𝑔 /(2 𝑘𝑇)
p
𝑛𝑖 = (1)

where 𝐸 𝑔 is the bandgap energy of silicon (approx 1.12 eV), 𝑘 is

Boltzmann’s constant, 𝑇 is the temperature in Kelvin, 𝑁𝑐 is the
density of states in conduction band, and 𝑁𝑣 is the density of states
in the valence band.

The density of states are

 3/2
2𝜋𝑘𝑇𝑚 𝑝∗
 3/2
2𝜋𝑘𝑇𝑚𝑛∗
 
𝑁𝑐 = 2 𝑁𝑣 = 2
ℎ2 ℎ2

where ℎ is Planck’s constant, 𝑚𝑛∗ is the effective mass of electrons,

and 𝑚 𝑝∗ is the effective mass of holes.

Leave it to engineers to simplify equations beyond understanding.

Equation (1) is complicated, and the density of states includes the
effective mass of electrons and holes, which is a parameter that
depends on the curvature of the band structure. To engineers, this
is too complicated, and 𝑛 𝑖 has been simplified so it “works” in
daily calculation.

Through engineering simplification, however, physics understand-

ing is lost.

In [1] they claim the intrinsic carrier concentration is a constant,

although they do mention 𝑛 𝑖 doubles every 11 degrees Kelvin.

In BSIM 4.8 [2] the intrinsic carrier concentration is

r
𝑇𝑁 𝑂 𝑀 𝑇 𝐸𝑔
𝑛 𝑖 = 1.45𝑒 10 exp21.5565981− 2𝑘𝑇
300.15 300.15

Comparing the three models in Figure 2, we see the shape of BSIM

and the full equation is almost the same, while the “doubling every
11 degrees” is just wrong.
32 4 Diodes

13
10
Advanced
Simple
12
10 BSIM 4.8

11
10

ni [1/cm3]
10
10

9
10

8
10

7
10
25 0 25 50 75 100 125

Figure 2: Intrinsic carrier concentration versus temperature

At room temperature the intrinsic carrier consentration is approxi-

mately 𝑛 𝑖 = 1 × 1016 carriers/m3 .

That may sound like a big number, however, if we calculate the

1016
electrons per 𝑢𝑚 3 it’s 𝑛 𝑖 = (11××10 6 )3 carriers/𝜇m < 1, so there are
3

really not that many free carriers in intrinsic silicon.

From Figure 2 we can see that 𝑛 𝑖 changes greatly as a function

of temperature, but the understanding “why” is not easy to get
from “doubling every 11 degrees”. To understand the temperature
behavior of diodes, we must understand Eq (1).

So where does Eq (1) come from? I find it unsatisfying if I don’t

understand where things come from. I like to understand why
there is an exponential, or effective mass, or Planck’s constant. If
you’re like me, then read the next section. If you don’t care, and
just want to memorize the equations, or indeed the number of
intrinsic carrier concentration number at room temperature, then
skip the next section.

4.4 It’s all quantum

There are two components needed to determine how many elec-

trons are in the conduction band. The density of available states,
and the probability of an electron to be in that quantum state.

For the density of states we must turn to quantum mechanics. The

probability amplitude of a particle can be described as

𝜓 = 𝐴𝑒 𝑖(𝑘 r−𝜔𝑡)
 4.4 It’s all quantum 33

where 𝑘 is the wave number, and 𝜔 is the angular frequency, and r

is a spatial vector.

In one dimension we could write 𝜓(𝑥, 𝑡) = 𝐴𝑒 𝑖(𝑘𝑥−𝜔𝑡)

In classical physics we described the Energy of the system as

1 2
𝑝 +𝑉 = 𝐸
2𝑚
where 𝑝 = 𝑚𝑣 , 𝑚 is the mass, 𝑣 is the velocity and 𝑉 is the
potential.

In the quantum realm we must use the Schrodinger equation to

compute the time evolution of the Energy, in one space dimension

ℏ2 𝜕 2 𝜕
− 𝜓(𝑥, 𝑡) + 𝑉(𝑥)𝜓(𝑥, 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡)
2𝑚 𝜕 𝑥
2 𝜕𝑡

where 𝑚 is the mass, 𝑉 is the potential, ℏ = ℎ/2𝜋.

We could rewrite the equation above as

𝜕
𝐻𝜓(𝑥,
b 𝑡) = 𝑖ℏ 𝜓(𝑥, 𝑡) = 𝐸𝜓(𝑥,
b 𝑡)
𝜕𝑡

where 𝐻b is sometimes called the Hamiltonian and is an operator, or

something that act on the wave-function. In Feynman’s Lectures
on Physics Feynman called the Hamiltonian the Energy Matrix of a
system. I like that better. The 𝐸
b is the energy operator, something
that operates on the wave-function to give the Energy.

We could re-arrange

[𝐻
b − 𝐸]𝜓(𝑟,
b 𝑡) = 0

This is an equation with at least 5 unknowns, the space vector in

three dimensions, time, and the energy matrix 𝐻b.

The dimensions of the energy matrix depends on the system. The

energy matrix further up is for one free electron. For an atom, the
energy matrix will have more dimensions to describe the possible
quantum states.

I consider all energy matricies as infinite dimensions, but most

state transitions are so unlikely that they can be safely ignored.

I was watching Quantum computing in the 21st Century and David

Jamison mentioned that the largest system we could today compute
would be a system with about 30 electrons.

We know exactly how the equations of quantum mechanics appear

to be, and they’ve proven extremely successful, we must make
simplifications before we can predict how electrons behave in
34 4 Diodes

complicated systems like the silicon lattice with approximately

0.7 trillion electrons per cube micro meter. You can check the
calculation

3
1 𝜇m

× 8 atoms per unit cell × 14 electrons per atom
0.543 nm

4.4.1 Density of states

To compute “how many Energy states are there per unit volume in
the conduction band”, or the “density of states”, we start with the
three dimensional Schrodinger equation for a free electron

ℏ2 2
− ∇ 𝜓 = 𝐸𝜓
2𝑚

I’m not going to repeat the computation here, but rather paraphrase
the steps. You can find the full derivation in Solid State Electronic
Devices.

The derivation starts by computing the density of states in the

k-space, or momentum space,

2
𝑁(𝑑𝑘) = 𝑑𝑘
(2𝜋)𝑝

Where 𝑝 is the number of dimensions (in our case 3).

The band structure 𝐸(𝑘) is used to convert to the density of states

to a function of energy 𝑁(𝐸). The simplest band structure, and an
approxmiation of the lowest conduction band is

ℏ2 𝑘 2
𝐸(𝑘) =
2𝑚 ∗

where 𝑚 ∗ is the effective mass of the particle. It is within this

effective mass that we “hide” the complexity of the actual three-
dimensional crystal structure of silicon.

The effective mass when we compute the density of states is

ℏ2
𝑚∗ =
𝑑2 𝐸
𝑑𝑘 2

as such, the effective mass depends on the localized band structure

of the silicon unit cell, and depends on direction of movement,
strain of the silicon lattice, and probably other things.
 4.4 It’s all quantum 35

In 3D, once we use the above equations, one can compute that the
density of states per unit energy is

2 𝑚 ∗ 3/2 1/2
𝑁(𝐸)𝑑𝐸 = 𝐸 𝑑𝐸
𝜋2 ℏ2

In order to find the number of electrons, we need the probability

of an electron being in a quantum state, which is given by the
Fermi-Dirac distribution

1
𝑓 (𝐸) = (2)
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 +1

where 𝐸 is the energy of the electron, 𝐸𝐹 is the Fermi level or checmi-

cal potential, 𝑘 is Boltzmann’s constant, and 𝑇 is the temperature
in Kelvin.

Fun fact, the Fermi level difference between two points is what you
measure with a voltmeter.

If the 𝐸 − 𝐸𝐹 > 𝑘𝑇 , then we can start to ignore the +1 and the

probability reduces to

1
𝑓 (𝐸) = = 𝑒 (𝐸𝐹 −𝐸)/𝑘𝑇
𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇

A few observiation on the Fermi-Dirac distribution. If the Energy

of a state is at the Fermi level, then 𝑓 (𝐸) = 21 , or a 50 % probability
of being occupied.

In a metal, the Fermi level lies within a band, as the conduction

band and valence band overlap. As a result, there are a bunch of
free electrons that can move around. Metal does not have the same
type of covalent bonds as silicon, but electrons are shared between
a large part of the metal structure. I would also assume that the
location of the Fermi level within the band structure explains the
difference in conductivity of metals, as it would determined how
many electrons are free to move.

In an insulator, the Fermi level lies in the bandgap between valence

band and conduction band, and usually, the bandgap is large, so
there is a low probability of finding electrons in the conduction
band.

In a semiconductor we also have a bandgap, but much lower energy

than an insulator. If we have thermal equilibrium, no external forces,
and we have an un-doped (intrinsic) silicon semiconductor, then
the fermi level 𝐸𝐹 lies half way between the conduction band edge
𝐸𝐶 and the valence band edge 𝐸𝑉 .
The bandgap is defined as the 𝐸𝐶 − 𝐸𝑉 = 𝐸 𝑔 , and we can use that
to get 𝐸𝐹 − 𝐸𝐶 = 𝐸𝐶 − 𝐸 𝑔 /2 − 𝐸𝐶 = −𝐸 𝑔 /2. This is why the bandgap
of silicon keeps showing up in our diode equations.
36 4 Diodes

The number of electrons per delta energy will then be given by

𝑁𝑒 𝑑𝐸 = 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸

, which can be integrated to get

 3/2
2𝜋𝑚 ∗ 𝑘𝑇

𝑛𝑒 = 2 𝑒 (𝐸𝐹 −𝐸𝐶 )/𝑘𝑇
ℎ2

For intrinsic silicon at thermal equlibrium, we could write

 3/2
2𝜋𝑚 ∗ 𝑘𝑇

𝑛0 = 2 𝑒 −𝐸 𝑔 /(2 𝑘𝑇) (3)
ℎ2

As we can see, Equation (3) has the same coefficients and form as
the computation in Equation (1). The difference is that we also have
to account for holes. At thermal equilibrium and intrinsic silicon
𝑛 𝑖2 = 𝑛0 𝑝 0

4.4.2 How to think about electrons (and holes)

I’ve come to the realization that to imagine electrons as balls

moving around in the silicon crystal is a bad mental image.

For example, for a metal-oxide-semiconductor field effect transistor

(MOSFET) it is not the case that the electrons that form the inversion
layer under strong inversion come from somewhere else. They
are already at the silicon surface, but they are bound in covalent
bonds (there are literaly trillions of bound electrons in a typical
transistor).

What happens is that the applied voltage at the gate shifts the
energy bands close to the surface (or bends the bands in relation
to the Fermi level), and the density of carriers in the conduction
band in that location changes, according to the type of derivations
above.

Once the electrons are in the conduction band, then they follow the
same equations as diffusion of a gas, Fick’s law of diffusion. Any
charge density concentration difference will give rise to a diffusion
current given by

𝜕𝜌
𝐽diffusion = −𝑞𝐷𝑛 (4)
𝜕𝑥

where 𝐽 is the current density, 𝑞 is the charge, 𝜌 is the charge

density, and 𝐷 is a diffusion coefficient that through the Einstein
relation can be expressed as 𝐷 = 𝜇𝑘𝑇 , where mobility 𝜇 = 𝑣 𝑑 /𝐹 is
the ratio of drift velocity 𝑣 𝑑 to an applied force 𝐹 .
 4.5 Doping 37

To make matters more complicated, an inversion layer of a MOSFET

is not in three dimensions, but rather a two dimensional electron
gas, as the density of states is confined close to the silicon surface.
As such, we should not expect the mobility of bulk silicon to be
the same as the mobility of a MOSFET transistor.

4.5 Doping

We can change the property of silicon by introducing other ele-

ments, something we’ve called doping. Phosphor has one more
electron than silicon, Boron has one less electron. Injecting these
elements into the silicon crystal lattice changes the number of free
electron/holes.

These days, we usually dope with ion implantation, while in

the olden days, most doping was done by diffusion. You’d paint
something containing Boron on the silicon, and then heat it in a
furnace to “diffuse” the Boron atoms into the silicon.

If we have an element with more electrons we call it a donor, and

the donor concentration 𝑁𝐷 .

The main effect of doping is that it changes the location of the

Fermi level at thermal equilibirum. For donors, the Fermi level will
shift closer to the conduction band, and increase the probabilty of
free electrons, as determined by Equation (2).

Since the crystal now has an abundance of free electrons, which

have negative charge, we call it n-type.

If the element has less electrons we call it an acceptor, and the

acceptor concentration 𝑁𝐴 . Since the crystal now has an abundance
of free holes, we call it p-type.

The doped material does not have a net charge, however, as it’s the
same number of electrons and protons, so even though we dope
silicon, it does remain neutral.

The doping concentrations are larger than the intrinsic carrier

concentration, from maybe 1021 to 1027 carriers/m3 . To separate
between these concentrations we use 𝑝−, 𝑝, 𝑝+ or 𝑛−, 𝑛, 𝑛+.

The number of electrons and holes in a n-type material is

𝑛 𝑖2
𝑛 𝑛 = 𝑁𝐷 , 𝑝 𝑛 =
𝑁𝐷

and in a p-type material

𝑛 𝑖2
𝑝 𝑝 = 𝑁𝐴 , 𝑛 𝑝 =
𝑁𝐴
38 4 Diodes

In a p-type crystal there is a majority of holes, and a minority of

electrons. Thus we name holes majority carriers, and electrons
minority carriers. For n-type it’s opposite.

4.6 PN junctions

Imagine an n-type material, and a p-type material, both are neutral

in charge, because they have the same number of electrons and
protons. Within both materials there are free electrons, and free
holes which move around constantly.

Now imagine we bring the two materials together, and we call

where they meet the junction. Some of the electrons in the n-type
will wander across the junction to the p-type material, and visa
versa. On the opposite side of the junction they might find an
opposite charge, and might get locked in place. They will become
stuck.

After a while, the diffusion of charges across the junction creates

a depletion region with immobile charges. Where as the two
materials used to be neutrally charged, there will now be a build
up of negative charge on the p-side, and positive charge on the
n-side.

4.6.1 Built-in voltage

The charge difference will create a field, and a built-in voltage will
develop across the depletion region.

The density of free electrons in the conduction band is

∫ ∞
𝑛= 𝑁(𝐸) 𝑓 (𝐸)𝑑𝐸
𝐸𝐶

, where 𝑁(𝐸) is the density of states, and 𝑓 (𝐸) is a probability of a

electron being in that state (Equation (2)).

We could write the density of electrons on the n-side as

∫ ∞
𝐸𝐹𝑛 /𝑘𝑇
𝑛𝑛 = 𝑒 𝑁𝑛 (𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶

since the Fermi level is independent of the energy state of the

electrons (I think).

The density of electrons on the p-side could be written as

∫ ∞
𝐸𝐹𝑝 /𝑘𝑇
𝑛𝑝 = 𝑒 𝑁𝑝 (𝐸)𝑒 −𝐸/𝑘𝑇 𝑑𝐸
𝐸𝐶
 4.6 PN junctions 39

If we assume that the density of states, 𝑁𝑛 (𝐸) and 𝑁𝑝 (𝐸) are the
same, and the temperature is the same, then

𝑛𝑛 𝑒 𝐸𝐹𝑛 /𝑘𝑇
= 𝐸 /𝑘𝑇 = 𝑒 (𝐸𝐹𝑛 −𝐸𝐹𝑝 )/𝑘𝑇
𝑛𝑝 𝑒 𝐹𝑝

The difference in Fermi levels is the built-in voltage multiplied by

the unit charge.

𝐸𝐹𝑛 − 𝐸𝐹𝑝 = 𝑞Φ

and by substituting for the minority carrier concentration on the

p-side we get

𝑁𝐴 𝑁𝐷
= 𝑒 𝑞Φ0 /𝑘𝑇
𝑛 𝑖2

or rearranged to

!
𝑘𝑇 𝑁𝐴 𝑁𝐷
Φ0 = 𝑙𝑛
𝑞 𝑛 𝑖2

4.6.2 Current

The derivation of current is a bit involved, but let’s try.

The hole concentration on the p-side and n-side could be written
as

𝑝𝑝
= 𝑒 −𝑞Φ0 /𝑘𝑇
𝑝𝑛

The negative sign is because the built in voltage is positive on the

n-type side
Asssume that −𝑥 𝑝 0 is the start of the junction on the p-side, and
𝑥 𝑛 0 is the start of the junction on the n-side.
Assume that we lift the p-side by a voltage 𝑞𝑉
Then the hole concentration would change to

𝑝(−𝑥 𝑝 0 )
= 𝑒 𝑞(𝑉−Φ0 )/𝑘𝑇
𝑝(𝑥 𝑛 0 )

while on the n-side the hole concentration would be

𝑝(𝑥 𝑛 0 )
= 𝑒 𝑞𝑉/𝑘𝑇
𝑝𝑛
40 4 Diodes

So the excess hole concentration on the n-side due to an increase

of 𝑉 would be

 
Δ𝑝 𝑛 = 𝑝(𝑥 𝑛 0 ) − 𝑝 𝑛 = 𝑝 𝑛 𝑒 𝑞𝑉/𝑘𝑇 − 1

The diffusion current density, given by Equation (4) states

𝜕𝜌
𝐽(𝑥 𝑛 ) = −𝑞𝐷𝑝
𝜕𝑥

Thus we need to know the charge density as a function of 𝑥 . I’m

not sure why, but apparently it’s

𝜕𝜌(𝑥 𝑛 ) = Δ𝑝 𝑛 𝑒 −𝑥 𝑛 /𝐿𝑝

where 𝐿 𝑝 is a diffusion length. I think the equation above, the

exponential decay as a function of length, is related to the probabilty
of electron/hole recombination, and how the rate of recombination
must be related to the exceess hole concentration, as such related
to Exponential decay.

Anyhow, we can now compute the current density, and need only
compute it for 𝑥 𝑛 = 0, so you can show it’s

𝐷𝑝  
𝐽(0) = 𝑞 𝑝 𝑛 𝑒 𝑞𝑉/𝑘𝑇 − 1
𝐿𝑝

which start’s to look like the normal diode equation. The 𝑝 𝑛 is the
minority concentration of holes on the n-side, which we’ve before
𝑛 𝑖2
estimated as 𝑝 𝑛 = 𝑁𝐷

We’ve only computed for holes, but there will be electron transport
from the p-side to the n-side also.

We also need to multiply by the area of the diode to get current

from current density. The full equation thus becomes

1 𝐷𝑛 1 𝐷𝑝  𝑞𝑉/𝑘𝑇
 
𝐼= 𝑞𝐴𝑛 𝑖2 𝑒

+ −1
𝑁𝐴 𝐿 𝑛 𝑁𝐷 𝐿 𝑝

where 𝐴 is the area of the diode, 𝐷𝑛 ,𝐷𝑝 is the diffusion coefficient

of electrons and holes and 𝐿𝑛 ,𝐿 𝑝 is the diffusion length of electrons
and holes.

Which we usually write as

𝑉𝐷
𝐼𝐷 = 𝐼𝑆 (𝑒 𝑉𝑇 − 1), where 𝑉𝑇 = 𝑘𝑇/𝑞
 4.6 PN junctions 41

4.6.3 Forward voltage temperature dependence

We can rearrange 𝐼𝐷 equation to get

𝐼𝐷
 
𝑉𝐷 = 𝑉𝑇 ln
𝐼𝑆

and at first glance, it appears like 𝑉𝐷 has a positive temperature

coefficient. That is, however, wrong.
First rewrite

𝑉𝐷 = 𝑉𝑇 ln 𝐼𝐷 − 𝑉𝑇 ln 𝐼𝑆

𝐷𝑛 𝐷𝑝
 
ln 𝐼𝑆 = 2 ln 𝑛 𝑖 + ln 𝐴𝑞 +
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷

Assume that diffusion coefficient ‡ , and diffusion lengths are

independent of temperature.
That leaves 𝑛 𝑖 that varies with temperature.

p −𝐸 𝑔
𝑛𝑖 = 𝐵 𝑐 𝐵𝑣 𝑇 3/2 𝑒 2𝑘𝑇

where

 3/2
2𝜋𝑘𝑚 𝑝∗
 3/2
2𝜋𝑘𝑚𝑛∗
 
𝐵𝑐 = 2 𝐵𝑣 = 2
ℎ2 ℎ2

p 𝑉𝐺
2 ln 𝑛 𝑖 = 2 ln 𝐵 𝑐 𝐵𝑣 + 3 ln 𝑇 −
𝑉𝑇

with 𝑉𝐺 = 𝐸𝐺 /𝑞 and inserting back into equation for 𝑉𝐷

𝑘𝑇
𝑉𝐷 = (ℓ − 3 ln 𝑇) + 𝑉𝐺
𝑞

Where ℓ is temperature independent, and given by

𝐷𝑛 𝐷𝑝
 p 
ℓ = ln 𝐼𝐷 − ln 𝐴𝑞 + − 2 ln 𝐵 𝑐 𝐵𝑣
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷

‡ From the Einstein relation 𝐷 = 𝜇𝑘𝑇 it does appear that the diffusion coefficient
increases with temperature, however, the mobility decreases with temperature.
I’m unsure of whether the mobility decreases with the same rate though.
42 4 Diodes

From equations above we can see that at 0 K, we expect the diode

voltage to be equal to the bandgap of silicon. Diodes don’t work at
0 K though.

Although it’s not trivial to see that the diode voltage has a negative
temperature coefficient, if you do compute it as in [Link], then
you’ll see it decreases.

The slope of the diode voltage can be seen to depend on the area,
the current, doping, diffusion constant, diffusion length and the
effective masses.

Figure 3 shows the 𝑉𝐷 and the deviation of 𝑉𝐷 from a straight line.

The non-linear component of 𝑉𝐷 is only a few mV. If we could
combine 𝑉𝐷 with a voltage that increased with temperature, then
we could get a stable voltage across temperature to within a few
mV.

0.95
Diode voltage [V]

0.90

0.85

25 0 25 50 75 100 125
Non-linear component (mV)

2
25 0 25 50 75 100 125
Temperature [C]

Figure 3: Diode forward voltage as a function of temperature

4.6.4 Current proportional to temperature

Assume we have a circuit like Figure 4.

Here we have two diodes, biased at different current densities. The

voltage on the left diode 𝑉𝐷 1 is equal to the sum of the voltage on
the right diode 𝑉𝐷 2 and voltage across the resistor 𝑅 1 . The current
in the two diodes are the same due to the current mirror. A such,
we have that

𝑞𝑉𝐷 1 𝑞𝑉𝐷 2
𝐼𝑆 𝑒 𝑘𝑇 = 𝑁 𝐼𝑆 𝑒 𝑘𝑇

Taking logarithm of both sides, and rearranging, we see that

 4.7 Equations aren’t real 43

𝑘𝑇
𝑉𝐷 1 − 𝑉𝐷 2 = ln 𝑁
𝑞

Or that the difference between two diode voltages biased at different

current densities is proportional to absolute temperature.
In the circuit above, this Δ𝑉𝐷 is across the resistor 𝑅 1 , as such,
the 𝐼𝐷 = Δ𝑉𝐷 /𝑅 1 . We have a current that is proportional to
temperature.
If we copied the current, and sent it into a series combination of a
resistor 𝑅 2 and a diode, we could scale the 𝑅 2 value to give us the
exactly right slope to compensate for the negative slope of the 𝑉𝐷
voltage.
The voltage across the resistor and diode would be constant over
temperature, with the small exception of the non-linear component
of 𝑉𝐷 .

TN

Figure 4: Circuit to generate a current proportional to kT

4.7 Equations aren’t real

Nature does not care about equations. It just is.

We know, at the fundamental level, nature appears to obey the

mathematics on quantum mechanics, however, due to the com-
plexity of nature, it’s not possible today (which is not the same as
impossible), to compute exactly how the current in a diode works.
44 4 Diodes

We can get close, by measuring a diode we know well, and hope

that the next time we make the same diode, the behavior will be
the same.
As such, I want to warn you about the “lies” or “simplifications”
we tell you. Take the diode equation above, some parts, like the
intrinsic carrier concentration 𝑛 𝑖 has roots directly from quantum
mechanics, with few simplifications, which means it’s likely solid
truth, at least for a single unit cell.
But there is no reason nature should make all unit cells the same,
and infact, we know they are not the same, we put in dopants. As
we scale down to a few nano-meter transistors the simplification
that “all unit cells of silicon are the same, and extend to infinity” is
no longer true, and must be taken into account in how we describe
reality.
Other parts, like the exact value of the bandgap 𝐸 𝑔 , the diffusion
constant 𝐷𝑝 or diffusion length 𝐿 𝑝 are macroscopic phenomena,
we can’t expect them to be 100 % true. The values would be based
on measurement, but not always exact, and maybe, if you rotate
your diode 90 degrees on the integrated circuit, the values could
be different.
You should realize that the consequence of our imperfection is that
the equations in electronics should always be taken with a grain of
salt.
Nature does not care about your equations. Nature will easily have
the superposition of trillions of electrons, and they don’t have to
agree with your equations.
But most of the time, the behavior is similar.

References

[1] T. C. Carusone, D. Johns, and K. Martin, Analog integrated

circuit design. Wiley, 2011 [Online]. Available: [Link]
[Link]/books?id=1OIJZzLvVhcC
[2] Berkeley, “Berkeley short-channel IGFET model.” [Online].
Available: [Link]
 Noise 5
5.1 Noise . . . . . . . . . . 45
5.1 Noise 5.2 Statistics . . . . . . . . 45
5.3 Average Power . . . . 46
5.4 Noise Spectrum . . . 47
Noise is a phenomena that occurs in all electronic circuits. It places
5.5 Probability Distribu-
a lower limit on the smallest signal we can use. Many now have tion . . . . . . . . . . . 48
super audio compact disc (SACD) players with 24bit converters,
5.6 PSD of a white noise
24 bits is around 224 = 16.78 Million different levels. If 5V is the source . . . . . . . . . . 49
maximum voltage, the minimum would have to be 25𝑉 24 ≈ 298 𝑛𝑉 .
5.7 Summing noise
That level is roughly equivalent to the noise in a 50 Ohm resistor sources . . . . . . . . . 49
with a bandwith of 96kHz. There exist an equation that relates 5.8 Signal to Noise Ratios 50
number of bits to signal to noise ratio 1, the equation specifies
5.9 Noise figure and Friis
that 𝑆𝑁 𝑅 = 6.02 ∗ 𝐵𝑖𝑡𝑠 + 1.76 = 146.24 𝑑𝐵. As of 12.2005 the best formula . . . . . . . . 51
digital to analog converter (DAC) that Analog Devices (a very 5.10 Spectral Density . . . 51
big semiconductor company) has is a DAC with 120dB SNR, that 5.10.1 Definition of Spectral
equals around 𝐵𝑖𝑡𝑠 = (120 − 1.76)/6.02 = 19.64. In other words, Density . . . . . . . . . 52
the last four bits of your SACD player is probably noise! 5.10.2 Sources of Confusion 52
5.10.3 Example: Thermal
Noise . . . . . . . . . . 54
5.10.4 Einstein: The source . 54
5.2 Statistics

The mean of a signal x(t) is defined as

∫ +𝑇/2
1
𝑥(𝑡) = lim 𝑥(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

The mean square of x(t) defined as

∫ +𝑇/2
1
𝑥 2 (𝑡) = lim 𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

The variance of x(t) defined as

2
𝜎2 = 𝑥 2 (𝑡) − 𝑥(𝑡)
For a signals with a mean of zero the variance is equal to the mean
square. The auto-correlation of x(t) is defined as

𝑅 𝑥 (𝜏) = 𝑥(𝑡)𝑥(𝑡 + 𝜏)
∫ +𝑇/2
1
= lim 𝑥(𝑡)𝑥(𝑡 + 𝜏)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
46 5 Noise

5.3 Average Power

Average power is defined for a continuous system as ([eq:powcont])

and for discrete samples it can be defined as ([eq:powsamp]).

𝑃𝑎𝑣 usually has the unit 𝐴2 or 𝑉 2 , so we have to multiply/devide by

the impedance to get the power in Watts. To get Volts and Amperes
we
√ use the root-mean-square (RMS) value which is defined as
𝑃𝑎𝑣 .

∫ +𝑇/2
1
𝑃𝑎𝑣 = lim 𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

𝑁
1 X
𝑃𝑎𝑣 = 𝑥 2 (𝑖)
𝑁 𝑖=0

If x(t) has a mean of zero then, according to ([eq:var]), 𝑃𝑎𝑣 is equal

to the variance of x(t).

Many different notations are used to denote average power and

RMS value of voltage or current, some of them are listed in Table
[t:avgpow] and Table 2. Notation can be a confusing thing, it
changes from book to book and makes expressions look different.

It is important to realize that it does not matter how you write

average power and RMS value. If you want you can invent your
own notation for average power and RMS value. However, if you
are presenting your calculations to other people it is convenient if
they understand what you have written. In the remainder of this
paper we will use 𝑒 𝑛2 for average power when we talk about voltage
noise source and 𝑖 𝑛2 for average power when we talk about current
noise source. The n subscript is used to identify different sources
and can be whatever.

Voltage Current
𝑉𝑟𝑚𝑠
2 𝐼𝑟𝑚𝑠
2

𝑉𝑛2 𝐼𝑛2
𝑣 𝑛2 𝑖 𝑛2

Voltage Current
𝑉
q𝑟𝑚𝑠 𝐼𝑟𝑚𝑠
q
𝑉2 𝐼𝑛2
q 𝑛 q
𝑣 𝑛2 𝑖 𝑛2
 5.4 Noise Spectrum 47

5.4 Noise Spectrum

With random noise it is useful to relate the average power to

frequency. We call this Power Spectral Density (PSD). A PSD plots
how much power a signal carries at each frequency. In literature
𝑆 𝑥 ( 𝑓 ) is often used to denote the PSD. In the same way that we use
𝑉2
𝑉 2 as unit of average power, the unit of the PSD is 𝐻𝑧 for voltage
𝐴2 p
and 𝐻𝑧 current. The root spectral density is defined as 𝑆 𝑥 ( 𝑓 ) and
has unit √𝑉 for voltage and √ 𝐼 for current.
𝐻𝑧 𝐻𝑧

The power spectral density is defined as two times the Fourier

transform of the auto-correlation function 2

∫ ∞
𝑆𝑥 ( 𝑓 ) = 2 𝑅 𝑥 (𝜏)𝑒 −𝑗 2𝜋 𝑓 𝜏 𝑑𝜏
−∞
This can also be written as

∫ ∞ ∫ ∞ 
𝑆𝑥 ( 𝑓 ) = 2 𝑅 𝑥 (𝜏) cos(𝜔𝜏)𝑑𝜏 − 𝑅 𝑥 (𝜏)𝑗 sin(𝜔𝜏)𝑑𝜏
−∞ −∞
∫ 0 ∫ ∞ 
= 2 𝑅 𝑥 (𝜏) cos(𝜔𝜏)𝑑𝜏 + 𝑅 𝑥 (𝜏) cos(𝜔𝜏)𝑑𝜏
−∞ 0
∫ 0 ∫ ∞ 
− 2𝑗 𝑅 𝑥 (𝜏) sin(𝜔𝜏)𝑑𝜏 + 𝑅 𝑥 (𝜏) sin(𝜔𝜏)𝑑𝜏
−∞ 0
∫ ∞
= 4 𝑅 𝑥 (𝜏) cos(𝜔𝜏)𝑑𝜏
0
 ∫ ∞ ∫ ∞ 
− 2𝑗 − 𝑅 𝑥 (𝜏) sin(𝜔𝜏)𝑑𝜏 + 𝑅 𝑥 (𝜏) sin(𝜔𝜏)𝑑𝜏
0 0
∫ ∞
= 4 𝑅 𝑥 (𝜏) cos(𝜔𝜏)𝑑𝜏
0

, since 𝑒 −𝑗𝜔𝜏 = cos(𝜔𝜏) − 𝑗 sin(𝜔𝜏), 𝑅 𝑥 (𝜏) and cos(𝜔𝜏) are sym-

metric around 𝜏 = 0 while sin(𝜔𝜏) is asymmetric around 𝜏 = 0.

The inverse of power spectral density is defined as

∫ ∞ ∫ ∞
1 𝑗 2𝜋 𝑓 𝜏
𝑅 𝑥 (𝜏) = 𝑆 𝑥 ( 𝑓 )𝑒 𝑑𝑓 = 𝑆 𝑥 ( 𝑓 ) cos(𝜔𝜏)𝑑 𝑓
2 −∞ 0

If we set 𝜏 = 0 we get

∫ ∞
𝑥 2 (𝑡) = 𝑆 𝑥 ( 𝑓 )𝑑 𝑓
0
which means we can easily calculate the average power if we know
the power spectral density. As we will see later it is common to
express noise sources in PSD form.
48 5 Noise

Another very useful theorem when working with noise in the

frequency domain is this

𝑆 𝑦 ( 𝑓 ) = 𝑆 𝑥 ( 𝑓 )|𝐻( 𝑓 )|2
, where 𝑆 𝑦 ( 𝑓 ) is the output power spectral density, 𝑆 𝑥 ( 𝑓 ) is the
input power spectral density and 𝐻( 𝑓 ) is the transfer function of a
time-invariant linear system.
If we insert ([eq:psd_hf]) into ([eq:ms_psd]), with 𝑆 𝑥 ( 𝑓 ) =
𝑎 𝑐𝑜𝑛𝑠𝑡 𝑎𝑛𝑡 = 𝐷𝑣 we get
∫ ∫
𝑥 2 (𝑡) = 𝑆 𝑦 ( 𝑓 )𝑑 𝑓 = 𝐷𝑣 |𝐻( 𝑓 )|2 𝑑 𝑓 = 𝐷𝑣 𝑓𝑥

, where 𝑓𝑥 is what we call the noise bandwidth. For a single time

constant RC network the noise bandwidth is equal to

𝜋 𝑓0 1
=𝑓𝑥 =
2 4𝑅𝐶
where 𝑓𝑥 is the noise bandwidth and 𝑓0 is the 3dB frequency.
We haven’t told you this yet, but thermal noise is white and white
means that the power spectral density is flat (constant over all
frequencies). If 𝑆 𝑥 ( 𝑓 ) is our thermal noise source and 𝐻( 𝑓 ) is a
standard low pass filter, then equation ([eq:psd_hf]) tells us that
the output spectral density will be shaped by 𝐻( 𝑓 ). At frequencies
above the 𝑓𝑥 in 𝐻( 𝑓 ) we expect the root power spectral density to
fall by 20dB per decade.

5.5 Probability Distribution

Theorem 1 (Central limit theorem). The sum of 𝑛 independent random

variables subjected to the same distribution will always approach a normal
distribution curve as 𝑛 increases.
This is a neat theorem, it explains why many noise sources we
encounter in the real world are white.‗ Take thermal noise for
example, it is generated by random motion of carriers in materials.
If we look at a single electron moving through the material the
probability distribution might not be Gaussian. But summing
probability distribution of the random movments with a large
number of electrons will give us a Gaussian distribution, thus
thermal noise is white.

‗ Gaussian distribution = normal distribution. Noise sources with Gaussian

distribution are called white
 5.6 PSD of a white noise source 49

5.6 PSD of a white noise source

If we have a true random process with Gaussian distribution we

know that the autocorrelation function only has a value for 𝜏 = 0.
From equation ([eq:autocor]) we have that

∫ +𝑇/2
1
𝑅 𝑥 (𝜏) = lim 𝑥(𝑡)𝑥(𝑡 − 𝜏)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
" #
∫ +𝑇/2
1
= lim 𝑥 2 (𝑡)𝑑𝑡 𝛿(𝜏)
𝑇→∞ 𝑇 −𝑇/2

= 𝑥 2 (𝑡)𝛿(𝜏)

The reason being that in a true random process 𝑥(𝑡) is uncorrelated

with 𝑥(𝑡 + 𝜏) where 𝜏 is an integer. If we use equation ([eq:psd])
we see that

∫ ∞
𝑆𝑥 ( 𝑓 ) = 2 𝑥 2 (𝑡)𝛿(𝜏)𝑒 −𝑗 2𝜋 𝑓 𝜏 𝑑𝜏
−∞
∫ ∞
= 2 𝑥 2 (𝑡) 𝛿(𝜏)𝑒 −𝑗 2𝜋 𝑓 𝜏 𝑑𝜏
−∞
= 2 𝑥 2 (𝑡)

, since

∫
𝛿(𝜏)𝑒 −𝑗 2𝜋 𝑓 𝜏 𝑑𝜏 = 𝑒 0 = 1

This means that the power spectral density of a white noise source
is flat, or in other words, the same for all frequencies.

5.7 Summing noise sources

Summing noise sources is usually trivial, but we need to know

why and when it is not. We if we write the time dependant noise
signals as

𝑣 𝑡𝑜𝑡
2
(𝑡) = (𝑣 1 (𝑡) + 𝑣 2 (𝑡))2 = 𝑣 12 (𝑡) + 2𝑣 1 (𝑡)𝑣2 (𝑡) + 𝑣 22 (𝑡)
The average power is defined as
50 5 Noise

∫ +𝑇/2
1
𝑒𝑡𝑜𝑡
2
= lim 𝑣 𝑡𝑜𝑡
2
(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
∫ +𝑇/2
1
= lim 𝑣 12 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
∫ +𝑇/2
1
+ lim 𝑣 22 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
∫ +𝑇/2
1
+ lim 2𝑣 1 (𝑡)𝑣 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2
∫ +𝑇/2
1
= 𝑒12 + 𝑒22 + lim 2𝑣 1 (𝑡)𝑣 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

If 𝑒12 and 𝑒22 are uncorrelated noise sources we can skip the last
term in ([eq:noisesum]) and just write

𝑒𝑡𝑜𝑡
2
= 𝑒12 + 𝑒22
Most natural noise sources are uncorrelated.

5.8 Signal to Noise Ratios

Signal to Noise Ratio (SNR) is a common method to specify the

relation between signal power and noise power in linear systems.
It is defined as

𝑆𝑖 𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟
 
𝑆𝑁 𝑅 = 10 log
𝑁 𝑜𝑖𝑠𝑒 𝑝𝑜𝑤𝑒𝑟

© 𝑣 𝑠𝑖 𝑔 ª
2

= 10 log ­ ®
𝑒
« 𝑛 ¬
2

© 𝑣 𝑟𝑚𝑠 ª
= 20 log ­­ q ®®
« 𝑒𝑛 ¬
2

Another useful ratio is Signal to Noise and Distortion (SNDR),

since most real systems exibit non-linearities it is useful to include
distortion in the ratio. One can calculate SNR and SNDR in many
ways. If we don’t know the expression for 𝑒 𝑛2 we can do a FFT of
our output signal. From this FFT we sum spectral components
except at the signal frequency to get noise and distortion. SNR is
normally calculated as

𝑆𝑖 𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟
 
𝑆𝑁 𝑅 = 10 log
𝑁 𝑜𝑖𝑠𝑒 𝑝𝑜𝑤𝑒𝑟 − 6 𝑓 𝑖𝑟𝑠𝑡 ℎ𝑎𝑟𝑚𝑜𝑛𝑖𝑐𝑠
 5.9 Noise figure and Friis formula 51

And SNDR is calculated as

𝑆𝑖 𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟
 
𝑆𝑁 𝐷𝑅 = 10 log
𝑁 𝑜𝑖𝑠𝑒 𝑝𝑜𝑤𝑒𝑟

5.9 Noise figure and Friis formula

Noise factor is a measure on the noise performance of a system. It

is defined as

𝑣 2𝑜
𝐹=
𝑠𝑜𝑢𝑟𝑐𝑒 𝑐𝑜𝑛𝑡𝑟𝑖𝑏𝑢𝑡𝑖𝑜𝑛 𝑡𝑜 𝑣 2𝑜

where 𝑣 2𝑜 is the total output noise.

The noise figure is defined as (noise factor in dB)

𝑁 𝐹 = 10 log(𝐹)
The noise factor can also be defined as

𝑆𝑁 𝑅 𝑖𝑛𝑝𝑢𝑡
𝐹=
𝑆𝑁 𝑅 𝑜𝑢𝑡𝑝𝑢𝑡

This brings us right into what is known as Friis formula. If we have

a multistage system, for example several amplifiers in cascade, the
total noise figure of the system is defined as

𝐹2 − 1 𝐹3 − 1
𝐹 = 1 + 𝐹1 − 1 + + + ....
𝐺1 𝐺1 𝐺2
Here 𝐹𝑖 is the noise figures of the individual stages and 𝐺 𝑖 is the
available gain of each stage. This can be rewritten as

𝑁
X 𝐹𝑖+1 − 1
𝐹 = 𝐹1 + Q𝑖−1
𝑖=1 𝑘=1
𝐺𝑖

Friiss formula tells us that it is the noise in the first stage that is the
most important if 𝐺1 is large. We could say that in a system it is
important to amplify the noise as early as possible!

5.10 Spectral Density

Warning: This is not an introduction to spectral density. If the

subject is completely unfamiliar I’d advise reading another source.
For example chapter 4 in 1 or chapter 7 in 3.
52 5 Noise

5.10.1 Definition of Spectral Density

There are two different definitions of spectral density used in the

literature. They differ by a factor of two. The one used in signal
processing books, like 4, is

∫ ∞
𝑆𝑥1 ( 𝑓 ) = 𝑅 𝑥 1 (𝜏)𝑒 −𝑗𝜔𝜏 𝑑𝜏
−∞
And the one often used in books about noise, like 2, is

∫ ∞
𝑆𝑥2 ( 𝑓 ) = 2 𝑅 𝑥 2 (𝜏)𝑒 −𝑗𝜔𝜏 𝑑𝜏
−∞
In both cases 𝑅 𝑥𝑖 (𝜏) is the auto-correlation function defined as

𝑅 𝑥𝑖 (𝜏) = 𝑥 𝑖 (𝑡)𝑥 𝑖 (𝑡 + 𝜏)
As we can plainly see

𝑆𝑥1 ( 𝑓 ) ≠ 𝑆𝑥2 ( 𝑓 )
, there is no way these two can be made equal if

𝑅 𝑥 1 (𝜏) = 𝑅 𝑥 2 (𝜏)
This is ok, there is no problem having two different definitions for
two different functions. In reality 𝑆 𝑥 1 ( 𝑓 ) and 𝑆 𝑥 2 ( 𝑓 ) are different
functions of frequency, and we could say that

𝑆 𝑥 2 ( 𝑓 ) = 2𝑆 𝑥 1 ( 𝑓 )
if ([eq:rxequal]) is true.

5.10.2 Sources of Confusion

The problem with spectral density arises when reading literature

from different communities, for example 4 and 2 where 𝑆 𝑥 ( 𝑓 )
is used for both 𝑆 𝑥 1 ( 𝑓 ) and 𝑆 𝑥 2 ( 𝑓 ). When I started investigating
spectral densities this lead me to believe that different sources
defined the same measure “spectral density” in two different ways.
The more sources I investigated the more unsure I was about which
of the two definitions that was correct. After months of searching
(not actively, but sporadicly) I eventually found the original source
of the definition of spectral density 5. Having the original source
helped, but I still don’t know when the original definition split into
([eq:psd1]) and ([eq:psd2]). However, I’m pretty sure the it’s just a
matter of convenience. To see why ([eq:psd2]) is the most common
among sources concerning noise we look at the inverse Fourier
Transform. By the way, if you had not noticed yet, ([eq:psd1]) says
 5.10 Spectral Density 53

that Spectral density is the Fourier Transform of the Auto-Correlation

function. The inverse Fourier Transform of ([eq:psd1]) is

∫ ∞ ∫ ∞
1
𝑅 𝑥 1 (𝜏) = 𝑆 𝑥 1 ( 𝑓 )𝑒 𝑗𝜔𝜏 𝑑𝑤 = 𝑆 𝑥 1 ( 𝑓 )𝑒 𝑗𝜔𝜏 𝑑 𝑓
2𝜋 −∞ −∞
,since 𝑑𝑤 = 𝑑 𝑓 𝑑𝑤/𝑑 𝑓 = 2𝜋𝑑 𝑓 . And for ([eq:psd2])

∫ ∞
1
𝑅 𝑥 2 (𝜏) = 𝑆 𝑥 2 ( 𝑓 )𝑒 𝑗𝑤𝜏 𝑑 𝑓
2 −∞

Before we proceed lets get rid of the 𝑒 ’s. We know that 𝑒 𝑗𝛼 =

cos 𝛼 + 𝑗 sin 𝛼 . So we could rewrite ([eq:psd1]) as

∫ ∞
𝑆𝑥1 ( 𝑓 ) = 𝑅 𝑥 1 (𝜏)[cos(𝜔𝜏) + 𝑗 sin(𝜔𝜏)]𝑑𝜏
−∞
and it turns out that since 𝑅 𝑥 1 (𝜏) is an even function we can drop
the 𝑗 sin 𝜔𝜏 term. 𝑆 𝑥 1 ( 𝑓 ) is also an even function since the Fourier
Transform of an even function is even.

The definitions then become

∫ ∞
𝑆𝑥1 ( 𝑓 ) = 𝑅 𝑥 1 (𝜏) cos(𝜔𝜏)𝑑𝜏
∫−∞∞
𝑅 𝑥 1 (𝜏) = 𝑆 𝑥 1 ( 𝑓 ) cos(𝜔𝜏)𝑑 𝑓
−∞

and

∫ ∞
𝑆𝑥2 ( 𝑓 ) = 2 𝑅 𝑥 2 (𝜏) cos(𝜔𝜏)𝑑𝜏
∫−∞∞
1
𝑅 𝑥 2 (𝜏) = 𝑆 𝑥 2 ( 𝑓 ) cos(𝜔𝜏)𝑑 𝑓
2 −∞

We can rewrite 𝑅 𝑥 2 (𝜏) as

∫ ∞
𝑅 𝑥 2 (𝜏) = 𝑥 2 (𝑡)𝑥 2 (𝑡 + 𝜏) = 𝑆 𝑥 2 ( 𝑓 ) cos(𝜔𝜏)𝑑 𝑓
0
and if 𝜏 = 0

∫ ∞
𝑥 22 (𝑡) = 𝑆 𝑥 2 ( 𝑓 )𝑑 𝑓
0
So using spectral density definition ([eq:psd2]) we see that average
power (mean square value of 𝑥 2 (𝑡)) is equal to the integral from
0 to infinity of the spectral density. If we use ([eq:psd1]) average
power would be
54 5 Noise

∫ ∞
𝑥 12 (𝑡) =2 𝑆 𝑥 1 ( 𝑓 )𝑑 𝑓
0

But if 𝑅 𝑥 1 (𝜏) = 𝑅 𝑥 2 (𝜏) then

𝑥22 (𝑡) = 𝑥 12 (𝑡)

even though 𝑆 𝑥 1 ( 𝑓 ) ≠ 𝑆 𝑥 2 ( 𝑓 ).
Definition ([eq:psd1]) is called the two-sided spectral density and
([eq:psd2]) is called the one-sided spectral density.

5.10.3 Example: Thermal Noise

The spectral density of thermal noise in electronic circuit should be

known to anyone that has studied analog electronics. We normally
define the voltage spectral density of thermal noise as

𝑆𝑡 ℎ ( 𝑓 ) = 4 𝑘𝑇𝑅
where k is Boltzmann’s constant, T the temperature in Kelvin and
R the resistance. But ([eq:othermal]) is the spectral density when it
is defined as in ([eq:psd2]). If we were to use ([eq:psd1]) then the
spectral density of thermal noise would be

𝑆𝑡 ℎ ( 𝑓 ) = 2 𝑘𝑇𝑅
Both these spectral densities would give the same average power
value if we use the inverse Fourier Transform of ([eq:psd1]) and
([eq:psd2]).†

5.10.4 Einstein: The source

In his 1914 paper 5 Albert Einstein described, supposedly for the

first time, the auto-correlation function and what we have come
to know as the spectral density. He defined the auto-correlation
function as

𝔐(Δ) = 𝐹(𝑡)𝐹(𝑡 + Δ)
and the intensity (spectral density) as

∫ 𝑇
Δ
𝐼(𝜃) = 𝔐(Δ) cos(𝜋 )𝑑Δ
0 𝜃

† Notethat if you calculate the average power of 𝑆𝑡 ℎ ( 𝑓 ) you’ll get infinity. You
have to include the bandwidth of the circuit you are considering for average
power to have a finite value.
 5.10 Spectral Density 55

,where the period 𝜃 = 𝑇/𝑛 and 𝑇 is a very large value. The paper is
very short, only 1 page, but it is worth reading. Note that ([eq:psd1])
is often referred to as the Wiener-Khintchine theorem.
 Sky130nm tutorial 6
6.1 Tools . . . . . . . . . . 57
6.1 Tools 6.1.1 Setup WSL (Appli-
cable for Windows
I would strongly recommend that you install all tools locally on users) . . . . . . . . . . 57
your system. 6.1.2 Setup public key
towards github . . . . 57
For the analog toolchain we need some tools, and a process design 6.1.3 Provide git with
kit (PDK). author identity . . . . 58
6.1.4 Get AICEX and setup
your shell . . . . . . . 58
▶ Skywater 130nm PDK. I use open_pdks to install the PDK
6.1.5 On systems with
▶ Magic VLSI for layout python3 > 3.12 . . . . 58
▶ ngspice for simulation 6.1.6 Install Tools . . . . . . 59
▶ netgen for LVS 6.1.7 Install cicconf . . . . . 59
▶ xschem 6.1.8 Install cicsim . . . . . 60
▶ python > 3.10 6.1.9 Setup your ngspice
settings . . . . . . . . . 60
The tools are not that big, but the PDK is huge, so you need to have 6.2 Check that magic and
about 50 GB disk space available. xschem works . . . . . 60
6.3 Design tutorial . . . . 60
6.3.1 Create the IP . . . . . . 60
6.1.1 Setup WSL (Applicable for Windows users) 6.3.2 The file structure . . . 60
6.3.3 Github setup . . . . . 62
6.3.4 Start working . . . . . 63
Install a Linux distribution such as Ubuntu 24.04 LTS by running 6.3.5 Draw Schematic . . . 63
the following command in PowerShell on Windows and follow the 6.3.6 Typical corner SPICE
instructions. simulation . . . . . . . 64
6.3.7 All corners SPICE
wsl --install -d Ubuntu-24.04
simulations . . . . . . 67
6.3.8 Draw Layout . . . . . 69
When you have installed the Linux distribution and signed into it, 6.3.9 Layout verification . 74
install make 6.3.10 Extract layout para-
sitics . . . . . . . . . . 74
sudo apt install make
6.3.11 Simulate with layout
parasitics . . . . . . . 75
6.3.12 Make documentation 75
6.1.2 Setup public key towards github 6.3.13 Edit [Link] . . . . . 76
6.3.14 Setup github pages . . 76
Do 6.3.15 Frequency asked
questions . . . . . . . . 76
ssh-keygen -t rsa

And press “enter” on most things, or if you’re paranoid, add a

passphrase

Then
cat ~/.ssh/id_rsa.pub

And add the public key to your github account. Settings - SSH and
GPG keys
58 6 Sky130nm tutorial

6.1.3 Provide git with author identity

There are interactions with git that require an author identity. You
are supposed to use one of these interactions a lot during the
project, namely, git commit. What you need to provide is an email
address and a name. If you would like to keep your real email
address private/secret, read what it says on GitHub at your user
settings page under emails. Use the below commands to provide
the author identity information to git.

git config --global [Link] "you@[Link]"

git config --global [Link] "Your Name"

6.1.4 Get AICEX and setup your shell

You don’t have to put aicex in $HOME/pro, but if you don’t know
where to put it, chose that directory.

cd
mkdir pro
cd pro
git clone --recursive [Link]

You need to add the following to your ~/.bashrc (note that

~ refers to your home directory $HOME/.bashrc also works, or
$HOME/.bash_profile on some newer macs)

export PDK_ROOT=/opt/pdk/share/pdk
export LD_LIBRARY_PATH=/opt/eda/lib
export PATH=/opt/eda/bin:$HOME/.local/bin:$PATH

6.1.5 On systems with python3 > 3.12

On newer systems it’s not trivial to install python packages because

python is externally managed. As such, we need to install a python
environment.

#- Find a package similar to name below

sudo apt-get update
sudo apt install python3.12-venv
sudo mkdir /opt
sudo mkdir /opt/eda
sudo mkdir /opt/eda/python3
sudo chown -R $USER:$USER /opt/eda/python3/
python3 -m venv /opt/eda/python3

Modify the ~/.bashrc to include the python environment

export PATH=/opt/eda/bin:/opt/eda/python3/bin:$HOME/.local/bin:$PATH
 6.1 Tools 59

6.1.6 Install Tools

Make sure you load the settings before you proceed

source ~/.bashrc

Hopefully the commands below work, if not, then try again, or try
to understand what fails. There is no point in continuing if one
command fails.
cd aicex/tests/
make requirements
make tt

On a mac, you probably need to add bison to the path

export PATH="/opt/homebrew/opt/bison/bin:$PATH"

I’ve split the install of each of the tools. It’s possible to run the
commented out lines instead, but they often fail
#make eda_compile
#sudo make eda_install
make magic_compile magic_install
make netgen_compile netgen_install
make xschem_compile xschem_install
make iverilog_compile iverilog_install
make ngspice_compile # Sometimes fails
make ngspice_compile ngspice_install

On Mac, do
brew install yosys verilator

On Linux, do
make yosys_compile yosys_install

On all, do
python3 -m ensurepip --default-pip

python3 -m pip install matplotlib numpy click svgwrite \

pyyaml pandas tabulate wheel setuptools tikzplotlib
source install_open_pdk.sh

6.1.7 Install cicconf

cIcConf is used for configuration. How the IPs are connected, and
what version of IPs to get.
cd
cd pro/aicex/ip/cicconf
git checkout main
git pull
python3 -m pip install -e .
cd ../

Update IPs
cicconf clone --https
cd ../..
60 6 Sky130nm tutorial

6.1.8 Install cicsim

cIcSim is used for simulation orchestration.

cd aicex/ip/cicsim
python3 -m pip install -e .
cd ../..

6.1.9 Setup your ngspice settings

Edit ~/.spiceinit and add

set ngbehavior=hsa ; set compatibility for PDK libs

set ng_nomodcheck ; don't check the model parameters
set num_threads=8 ; CPU hardware threads available
set skywaterpdk
option noinit ; don't print operating point data
option klu
optran 0 0 0 100p 2n 0 ; don't use dc operating point,
option opts

6.2 Check that magic and xschem works

To check that magic and xschem works

cd ~/pro/aicex/ip/sun_sar9b_sky130nm/work
magic ../design/SUN_SAR9B_SKY130NM/SUNSAR_SAR9B_CV.mag &
xschem -b ../design/SUN_SAR9B_SKY130NM/SUNSAR_SAR9B_CV.sch &

6.3 Design tutorial

6.3.1 Create the IP

I’ve made some scripts to automatically generate the IP.

To see what files are generated, see tech_sky130A/cicconf/ip_-

[Link]

cd aicex/ip
cicconf newip ex

6.3.2 The file structure

It matters how you name files, and store files. I would be surprised
if you had a good method already, as such, I won’t allow you
to make your own folder structure and names for things. I also
control the filenames and folder structure because there are many
scripts to make your life easier (yes, really) that rely on an exact
structure. Don’t mess with it.
 6.3 Design tutorial 61

[Link] Github workflows

On github it’s possible use something called workflows to run

things every time you push a new version. It’s really nice, since it
can then check that your design is valid.
The grading of the milestones is determined by passing github
workflows.
We will also check that you have not cheated, and modified the
workflows just to get them passing.
The workflows are defined below.
.github
workflows
[Link] # Generate a github page
[Link] # Run Design Rule Checks
[Link] # Generate a GDS file from layout
[Link] # Run Layout Versus Schematic
# and Layout Parasitic Extraction
[Link] # Run a simulation

[Link] Configuration files

Each IP has a few files that define the setup, you’ll need to modify
at least the [Link] and the [Link].
.gitignore # files that are ignored by git
[Link] # Frontpage documentation
[Link] # What libraries are used. Used by cicconf
[Link] # Setup names, authors etc
media # Where you should store images for documentation
tech -> ../tech_sky130A # The technology library

[Link] Design files

A “cell” in the open source EDA world should consists of the

following files

▶ Schematic (.sch)
▶ Layout (.mag)
▶ Documenation (.md)

The files must have the same name, and must be stored in
design/<LIB>/ as shown below.

Note there are also two symbolic links to other libraries. These two
libraries contain standard cells and standard analog transistors
(ATR) that you should be using.
design
JNW_EX_SKY130A
JNW_EX.sch
JNW_ATR_SKY130A -> ../../jnw_atr_sky130a/design/JNW_ATR_SKY130A
JNW_TR_SKY130A -> ../../jnw_tr_sky130a/design/JNW_TR_SKY130A

For example, if the cell name was JNW_EX, then you would have
62 6 Sky130nm tutorial

▶ design/JNW_EX_SKY130A/JNW_EX.sch: Schematic (xschem)

▶ design/JNW_EX_SKY130A/JNW_EX.sym: Schematic (xschem)
▶ design/JNW_EX_SKY130A/JNW_EX.mag: Layout (Magic)
▶ design/JNW_EX_SKY130A/JNW_EX.md : Markdown docu-
mentation (any text editor)

All these files are text files, so you can edit them in a text editor,
but mostly you shouldn’t (except for the Markdown)

[Link] Simulations

All simulations shall be stored in sim. Once you have a Schematic

ready for simulation, then

cd sim
make cell CELL=JNW_EX

This will make a simulation folder for you. Repeat for all your
cells.

sim
Makefile
[Link] -> ../tech/cicsim/[Link]

[Link] The work

All commands (except for simulation), shall be run in the work

folder.

In the work/ folder there are startup files for Xschem (xschemrc)
and Magic (.magicrc). They tell the tools where to find the process
design kit, symbols, etc. At some point you probably need to learn
those also, but I’d wait until you feel a bit more comfortable.

work
.magicrc
Makefile
[Link] -> ../tech/magic/[Link]
[Link] -> ../tech/magic/[Link]
xschemrc

6.3.3 Github setup

Create a repository on github. The name of the repository that you

make on GitHub has to be the same as what is written after <your
username> in the last command below. In this example, that is
jnw_ex_sky130a.

cd jnw_ex_sky130a
git remote add origin \
git@[Link]:<your username>/jnw_ex_sky130a.git
 6.3 Design tutorial 63

6.3.4 Start working

[Link] Edit [Link]

Open [Link] in your favorite text editor and make necessary

changes.

[Link] Familiarize yourself with the Makefile and make

I write all commands I do into a Makefile. There is nothing special

with a Makefile, it’s just what I choose to use 20 years ago. I’m not
sure I’d choose something different now.
cd work
make

Take a look inside the file called Makefile.

6.3.5 Draw Schematic

The block we’ll make is a current mirror with a 1 to 4 scaling.

A schematic is how we describe the connectivity, and the types of

devices in an analog circuit. The open source schematic editor we
will use is XSchem.

Open the schematic:

xschem -b ../design/JNW_EX_SKY130A/JNW_EX.sch &

[Link] Add Ports

Add IBPS_5U and IBNS_20U ports, the P and N in the name

signifies what transistor the current comes from. So IBPS must go
into a diode connected NMOS, and N will be our output, and go
into a diode connected PMOS somewhere else.

[Link] Add transistors

Use ‘I’ or ‘Shift+i’ (note the letter case) to open the library manager.
Click the jnw_ex_sky130A/design path, then JNW_ATR_SKY130A
and select JNWATR_NCH_4C5F0.sym

The naming convention for these transistors is <number of

contacts on drain/source>C<times minimum gate length>F,
so the number before the C is the width, and the number
before/after the F is the length. The absolute size does not matter
for now. Just think “4C5F0 is a 4 contact wide long transistor”,
while a “4C1F2 is a 4 contact wide, short transistor”.
64 6 Sky130nm tutorial

Select the transistor and press ‘c’ to copy it, while dragging, press
‘shift-f’ to flip the transistor so our current mirror looks nice. ‘shift-r’
rotates the transistor, but we don’t want that now.

Press ESC to deselect everything

Select the input transistor, and change the name to ‘xi’

Select the output transistor, and change the name to ‘xo[3:0]’. Using
bus notation on the name will create 4 transistors

Select ports, and use ‘m’ to move the ports close to the transistors.

Press ‘w’ to route wires.

Use ‘shift-z’ and z, to zoom in and out

Use ‘f’ to zoom full screen

Remember to save the schematic

[Link] Netlist schematic

Check that the netlist looks OK

In work/

make xsch CELL=JNW_EX

cat xsch/JNW_EX.spice

6.3.6 Typical corner SPICE simulation

I’ve made cicsim that I use to run simulations (ngspice) and extract
results
 6.3 Design tutorial 65

[Link] Setup simulation environment

Navigate to the jnw_ex_sky130a/sim/ directory.

Make a new simulation folder

cicsim simcell JNW_EX_SKY130A JNW_EX \

../tech/cicsim/cell_spice/[Link]

I would recommend you have a look at simcell_template.yaml file

to understand what happens.

[Link] Familiarize yourself with the simulation folder

I’ve added quite a few options to cicsim, and it might be confusing.

For reference, these are what the files are used for

File Description
Makefile Simulation commands
[Link] Setup for cicsim
[Link] Generate a README with simulation results
[Link] Measurement to be done after simulation
[Link] Optional python script to run for each simulation
[Link] Transient testbench
[Link] What measurements to summarize

The default setup should run, so

cd JNW_EX
make typical

[Link] Modify default testbench ([Link])

Delete the VDD source

Add a current source of 5uA, and a voltage source of 1V to IBNS_-

20U

IBP 0 IBPS_5U dc 5u
V0 IBNS_20U 0 dc 1

Save the current in V0 by adding i(V0) to the save statement in the

testbench

Save the voltage by adding v(IBPS_5U) to the save statement

.save i(V0) v(IBPS_5U)

66 6 Sky130nm tutorial

[Link] Modify measurements ([Link])

Add measurement of the current and VGS. It must be added

between the “MEAS_START” and “MEAS_END” lines.
let ibn = -i(v0)
meas tran ibns_20u find ibn at=5n
meas tran vgs_m1 find v(ibps_5u) at=5n

Run simulation
make typical

and check that the output looks okish.

Try to run the simulation again

make typical

If everything works, then the simulation now should not be run.

Every time cicsim runs (provided the sha: True option is set in
[Link]) cicsim will compute a SHA hash of all files (stored
in output_tran/.sha) that is referenced in the [Link]. Next time
cicsim is run, it checks the hash’s and does not re-run if there is no
need (no files changed).

Sometimes you want to force running, and you can do that by

make typical OPT="--no-sha"

Often, it’s the measurement that I get wrong, so instead of rerun-

ning simulation every time I’ve added a “–no-run” option to cicsim.
For example
make typical OPT="--no-run"

will skip the simulation, and rerun only the measurement. This is
why you should split the testbench and the measurement. Simula-
tions can run for days, but measurement takes seconds.

[Link] Modify result specification ([Link])

Add the result specifications, for example

ibn:
src:
- ibns_20u
name: Output current
min: -20%
typ: 20
max: 20%
scale: 1e6
digits: 3
unit: uA

vgs:
src:
- vgs_m1
name: Gate-Source voltage
typ: 0.6
 6.3 Design tutorial 67

min: 0.3
max: 0.7
scale: 1
digits: 3
unit: V

Re-run the measurement and result generation

make typical OPT="--no-run"

Open result/tran_Sch_typical.html

[Link] Check waveforms

You can either use ngspice, or you can use cicsim, or you can use
something I don’t know about

Open the raw file with

cicsim wave output_tran/tran_SchGtKttTtVt.raw

Load the results, and try to look at the plots. There might not be
that much interesting happening

6.3.7 All corners SPICE simulations

Analog circuits must be simulated for all physical conditions,

we call them corners. We must check high and low temperature,
high and low voltage, all process corners, and device-to-device
mismatch.

For the current mirror we don’t need to vary voltage, since we

don’t have a VDD.

[Link] Remove Vh and Vl corners (Makefile)

Open Makefile in your favorite text editor.

Change all instances of “Vt,Vl,Vh” and “Vl,Vh” to Vt

[Link] Run all corners

To simulate all corners do

make typical etc mc

where etc is extreme test condition and mc is monte-carlo.

Wait for simulations to complete.

68 6 Sky130nm tutorial

[Link] Get creative with python

Open [Link] in your favorite editor, try to read and understand

it.

The name parameter is the corner currently running, for example

tran_SchGtAmcttTtVt.

The measured outputs from ngspice will be added to tran_-

[Link]

Delete the “return” line.

Add the following lines (they automatically plot the current and
gate voltage)

import cicsim as cs
fname = name +".png"
print(f"Saving {fname}")
[Link](name + ".raw","time","v(ibps_5u),i(v0)" \
,ptype="",fname=fname)

Re-run measurements to check the python code

make typical etc mc OPT="--no-run"

You’ll see that cicsim writes all the png’s. Check with ls -l
output_tran/*.png.

You’ll also notice it will slow down the simulation, so maybe

remove the lines from [Link] again ;-)

[Link] Generate simulation summary

Run

make summary

Install pandoc if you don’t have it

Run

pandoc -s -t slidy [Link] -o [Link]

to generate a HTML slideshow that you can open in browser. Open

the HTML file.
 6.3 Design tutorial 69

[Link] Viewing results without GUI browser

If your on a system without a browser, or indeed a GUI, then it’s

possible to view the results in the terminal.

Check if lynx is installed, if it’s not installed, then

On linux

sudo apt-get install lynx

On Mac

brew install lynx

Then

lynx [Link]

[Link] Think about the results

From the corner and mismatch simulation, we can observe a few

things.

▶ The typical value is not 20 uA. This is likely because we have

a M2 VDS of 1 V, which is not the same as the VDS of M1. As
such, the current will not be the same.
▶ The statistics from 30 corners show that when we add or
subtract 3 standard deviation from the mean, the resulting
current is outside our specification of +- 20 %. I’ll leave it up
to you to fix it.

6.3.8 Draw Layout

A foundry (the factory that makes integrated circuits) needs to

know how we want them to create our circuit. So we need to provide
them with a “layout”, the recipe, or instruction, for how to make
the circuit. Although the layout contains the same components as
the schematic, the layout contains the physical locations, and how
to actually instruct the foundry on how to make the transistors we
want.

Open Magic VLSI

cd work
magic ../design/JNW_EX_SKY130A/JNW_EX.mag

Now brace yourself, Magic VLSI was created in the 1980’s. For
it’s time it was extremely modern, however, today it seems dated.
However, it is free, so we use it.
70 6 Sky130nm tutorial

[Link] Magic VLSI

Try google for most questions, and there are youtube videos that
give an intro.

▶ Magic Tutorial 1
▶ Magic Tutorial 2
▶ Magic Tutorial 3
▶ Magic command reference
▶ Magic Documentation

Default magic start with the BOX tool. Mouse left-click to select
bottom corner, left-click to select top corner.

Press “space” to select another tool (WIRING, NETLIST, PICK).

Type “macro help” in the command window to see all shortcuts

Hotkey Function
v View all
shift-z zoom out
z zoom in
x look inside box (expand)
shift-x don’t look inside box (unexpand)
u undo
d delete
s select
Shift-Up Move cell up
Shift-Down Move cell down
Shift-Left Move cell left
Shift-Right Move cell right

[Link] Add transistors

Open Cell -> Place Instance. Navigate to the right transistor.

Place it. Hover over the transistor and select it with ‘s’. Now comes
a bit of tedious thing. Select again, and copy. It’s possible to align
the transistors on-top of eachother, but it’s a bit finicky.

Place all transistors on top of each other.

 6.3 Design tutorial 71

[Link] Add Ground

In the command window, type

see no *
see viali
see locali
see m1
see via1
see m2

Change to the ‘wire tool’ with spacebar. Press the top transistor ‘S’
and draw all the way down to connect all of the transistors’ source
terminals.

Change grid to 0.5 um.

Select a 0.5 um box below the transistors and paint the rectangle
with locali (middle click on locali)

Connect guard rings to ground. Use the ‘wire tool’

Connect the sources to ground. Use the ‘wire tool’. Use ‘shift-right
click’ to change layer down
72 6 Sky130nm tutorial

[Link] Route Gates

Press “space” to enter wire mode. Left click to start a wire, and
right click to end the wire.

The drain of M1 transistor needs a connection from gate to drain.

We do that for the middle transistor.

Start the route, press ‘shift-left click’ to go up one layer, route over
to drain, and ‘shift-right click’ to go down.
 6.3 Design tutorial 73

[Link] Drain of M2

Use the wire tool to draw connections for the drains.

To add vias you can do “shift-left click” to move up a metal, and

“shift-right click” to go down.
74 6 Sky130nm tutorial

[Link] Add labels

Select a box on a metal, and use “Edit->Text” to add labels for the
ports. Select the port button.

6.3.9 Layout verification

The DRC can be seen directly in Magic VLSI as you draw.

To check layout versus schematic navigate to work/ and do

make cdl lvs

If you’ve routed correctly, then the LVS should be correct.

6.3.10 Extract layout parasitics

With the layout complete, we can extract parasitic capacitance.

make lpe

Check the generated netlist

cat lpe/JNW_EX_lpe.spi
 6.3 Design tutorial 75

6.3.11 Simulate with layout parasitics

Navigate to sim/JNW_EX. We now want to simulate the layout.

The default [Link] should already have support for that.

Open the Makefile, and change

VIEW=Sch

to

VIEW=Lay

[Link] Typical simuation

Run

make typical

[Link] Corners

Navigate to sim/JNW_EX. Run all corners again

make all

[Link] Simulation summary

Open [Link] and add the layout files.

- name: Lay_typ
src: results/tran_Lay_typical
method: typical
- name: Lay_etc
src: results/tran_Lay_etc
method: minmax
- name: Lay_3std
src: results/tran_Lay_mc
method: 3std

Run summary again

make summary
pandoc -s -t slidy [Link] -o [Link]

Open the [Link] and have a look a the results. The layout
should be close to the schematic simulation.

6.3.12 Make documentation

Make a file (or it may exists) design/JNW_EX_SKY130A/JNW_EX.md

and add some docs.
76 6 Sky130nm tutorial

6.3.13 Edit [Link]

Finally, let’s setup the [Link] so that all the github workflows
run correctly.
Mine will look like this.
You need to setup the url (probably something like <your
username>.[Link]) to what is correct for you.

I’ve added the doc section such that the workflows will generate
the docs.
The sim is to run a typical simulation.
library: JNW_EX_SKY130A
cell: JNW_EX
author: Carsten Wulff
github: wulffern
tagline: The answer is 42
email: carsten@[Link]
url: [Link]
doc:
libraries:
JNW_EX_SKY130A:
- JNW_EX
sim:
JNW_EX: make typical

6.3.14 Setup github pages

Go to your GitHub repository (repo). Press Settings. Press Pages.

Choose source under Build and Deployment -> GitHub Actions
Wait for the workflows to build. And check your github pages.
Mine is [Link]

6.3.15 Frequency asked questions

Q: My GDS/LVS/DRC action fails, even though it works locally.

Sometimes the reference to the transistors in the magic file might
be wrong. Open the .mag file in a text editor and check. The correct
way is
use JNWATR_NCH_4C5F0 JNWATR_NCH_4C5F0_0 ../JNW_ATR_SKY130A

It’s the last ../JNW_ATR_SKY130A that sometimes is missing.

 Analog Design 7
7.1 Checklist 7.1 Checklist . . . . . . . . 77
7.1.1 Specification . . . . . . 77
7.1.2 Design . . . . . . . . . . 78
There are roughly 3 phases of analog design. 7.1.3 Tapeout . . . . . . . . . 78
7.2 Schematic rules . . . . 78
▶ Specification 7.3 Layout rules . . . . . . 80
▶ Design
▶ Tapeout

The specification phase is where you think deeply through the

design.
Can the design meet the key parameters you need? How will I
verify the circuit? Do I know how to make the circuit?
These questions and more, are so common that most companies
will have checklists that we use when we review the specification,
design, and tapeout.
These checklists are closely guarded secrets, as the content contain
significant amount of knowledge accumulated over numerous
blunders, mistakes, failure to imagine, and physics teaching us a
lesson.
The design phase is where we make the schematic, and simulate
the schematic. We explore circuit architectures, fix problem corners,
check our design over temperature, voltage, process corners (slow
transistors, fast transistors, mismatch)
The tapeout phase is where we translate the schematic into layout,
check the design rules (DRC), do layout versus schematic (LVS)
and extract circuit parasitics to check layout parasitic effects (LPE).
And, of course, simulate most things again.
I’ve made a checklist below for the most common questions that
you need to ask yourself.

7.1.1 Specification

Item Description Yes Action

Functional Have you described what the IP shall do?
descrip-
tion
Key pa- Have you updated your key parameters in the README
rameters
Architecture Have you described the circuit architecture? How should it
work?
Realism Do you know how to do what you plan to do?
Verification Have you described exactly what you need to check? For
plan example, stability of OTAs, current consumption, key
parameters
78 7 Analog Design

Item Description Yes Action

Specification Have you added a specification for all parameters you intend
to check. For example, phase margin should always be larger
than 45 degrees.

7.1.2 Design

Item Description Yes Action

git Have you committed the schematics to the repository?
git push Are the schematics pushed to github? Are you sure?
git tag Is the current version tagged
Implementation Are all schematics described with their own markdown file?
Verification Are all items on the verification plan completed? If not,
plan have you described why it’s no longer relevant?
Electrical Are the electrical parameters updated with simulated
parameters results?
Spec Have you explained why the specification violations are not
violations an issue?
Simulation Are the required corners run (typical, slow, fast, mc)

7.1.3 Tapeout

Item Description Yes Action

git Are all schematics and layout committed? Are you sure?
git push Have you pushed to github?
git tag Is the latest version tagged?
LVS Is the LVS on github passing (green)?
DRC Is the DRC on github passing (green)?
LPE Is the LPE on github passing (green)?
Simulation Are the required corners re-run with layout parasitics
(typical, slow, fast, mc)

7.2 Schematic rules

Rules are nice. They reduce the cognitive load since a decision
already has been made. You may disagree with the rule, but
in analog design it’s not that important what the “rule” is, but
sometimes more important that the rule is followed.

Naming rules are one example. We can have a philosophical

discussion till the end of time of whether it’s best with uppercase
or lower case. CamelCase, however, is wrong in schematics and
SPICE, since SPICE is case-insensitive, so “vref” is the same as
“Vref**.

Below are the rules I like. You may disagree, but if you’re my
student, then you don’t have a choice. Follow them, or the grade
may suffer.
 7.2 Schematic rules 79

[Link] Only uppercase names allowed

Do: AVDD, Don’t: aVdd

Although editors can handle mix of upper case and lower case,
SPICE, cannot. SPICE is case insensitive. That means AVDD ==
aVdd in SPICE, but AVDD != aVdd in editors. A such mixing case
is a bad idea, so one must be picked, and uppercase the chosen
one. Why? Why not?

[Link] Use same net throughout hierarchy

Do: VDD -> VDD -> VDD, Don’t: VDD -> LOCALVDD -> CEL-
LVDD

Debugging becomes a lot simpler if a net keeps it’s name through-

out the schematic hierarchy. Especially bad are cases where a
net name is reused on multiple levels of hierarchy. Imagine the
following scenario

| (sub block) |
| |
VDD -|-LVDD---/ ---- VDD |
| |

Here the net name VDD is used on the top level, while LVDD is
used in the sub-block. In the sub-block there is a power switch
between LVDD and VDD. In this case VDD != VDD on top level,
which can lead to long debugging times. There are, however, a few
exceptions. For example, using VDD on standard cells (inverters,
ANDs etc) is ok, even though the power supply is not called VDD

[Link] Spend time on making schematics pretty

It matters how schematics look. Think of it like this. In 10 years,

you will be asked to port, re-simulate, fix a bug, on your design.
If you have spent some time adding comments, making things
look pretty, etc, then the job will be much, much easier. “A pretty
schematic is a love letter to your future self”.

PS: This applies to documentation, code, and every-

thing you make.
80 7 Analog Design

[Link] All digital nets must be “active high”” naming

Example: PWRUP_3V3, PWRUP_N_3V3

The PWRUP_3V3 should be understood as “When PWRUP_3V3

is high, then the block is powered up”

The PWRUP_N_3V3 should be understood as “When PWRUP_-

N_3V3 is high then the block is powered down”

[Link] Bias currents shall be named IB<device sending current

(P|N)>

Do: IBP_1U, Don’t: IBIAS_1U

The “P” post-fix tells us the current comes from a PMOS, so we

can put it into a NMOS diode connected transistor. On the IBIAS
we have no idea which way the current flows.

7.3 Layout rules

[Link] Limit the amount of transistor Width’s and Length’s that

you use

Do: W = 1.0 um, L = 180 nm, Use multiplier for other sizes

Don’t: W1 = 1 um, W2 = 1.1 um, W3 = 1.2 um, W4 = 2 um, W5 = 2.1

um

You want the layout to be relatively regulator. A bunch of different

Ls and Ws is a pain when you do layout

[Link] Use pre-defined transistors for regular layout

Do: Use JNW_ATR_SKY130A and JNW_TR_SKY130A

[Link] Always use two fingers for analog transistors

That way, you don’t have to worry about current direction in the
layout.

[Link] Always run gates in the same direction

Mobility of transistors (especially PMOS) is affected by strain, so if

you rotate a transistor it will not have the same current, and change
in current as a function of stress.

I’ve seen ICs have to be taped out again due to rotated transistors.
 7.3 Layout rules 81

[Link] Always have dummy poly gates

For large lengths (> 500 nm) the lithography effects are not that
severe, but the etching of the gate material will be asymmetric if
there are no poly dummies. Make sure the poly dummy is exactly
the same spacing on both sides.
For small lengths (< 200 nm) the lithography effects start to matter.
The light used in most litho is 193 nm. 193 nm is used all the way
down to about 7 nm.
Due to diffraction effects, it’s common to have extremely regular
poly spacing, an exact distance such that the interference from
neighboring poly’s align perfectly to the next poly.

[Link] Always place transistors away from well edge

Close to the N-well edge the donor consentration will be higher.

Ion implantation is used for the wells, and the ions will scatter of
the oxide wall, and increase the doping concentration close to the
edge. As such, the transistor threshold voltage will increase close
to a well edge.
Keep transistors about 3 um away from the N-well edge if threshold
voltage is important.
 IC and ESD 8
8.1 What blocks must our
Keywords: TempSense, Node Voltage, Ground, VDD, Clocks, Digi- IC include? . . . . . . 83
tal, Bias, RESET (POR), Package, Why ESD, CDM (Gauss, INV), 8.2 Electrostatic Dis-
HBM (01,10,02,20,12,21) , GGNMOS, Latch-up charge . . . . . . . . . 86
8.2.1 When do ESD events
Video is from 2024, so the plan might not be exactly the same. occur? . . . . . . . . . 87
In addition, we’re not using Caravel for the tapeout, but rather 8.2.2 Before/during PCB . 87
TinyTapeout. 8.2.3 After PCB . . . . . . . 87
8.2.4 Human body model
(HBM) . . . . . . . . . 88
8.2.5 Charged device model
(CDM) . . . . . . . . . 88
8.1 What blocks must our IC include? 8.3 An HBM ESD zap
example . . . . . . . . 90
8.4 Permutations . . . . . 91
The project is to design an integrated temperature sensor. 8.4.1 Why does this work? 93
8.5 But I just want a dig-
First, we need to have an idea of what comes in and out of the ital input, what do I
temperature sensor. Before we have made the temperature sensor, need? . . . . . . . . . 96
we need to think what the signal interface could be, and we need 8.5.1 Input buffer . . . . . . 97
to learn. 8.6 Latch-up . . . . . . . 98
8.6.1 How can current in
one place lead to a
Maybe we read Kofi Makinwa’s overview of temperature sensors current somewhere
and find one of the latest papers, else? . . . . . . . . . . 98
8.7 Want to learn more? 100
A BJT-based CMOS Temperature Sensor with Duty-cycle-
modulated Output and ±0.54 °C (3-sigma) Inaccuracy from -40 °C
to 125 °C.

At this point, you may struggle to understand the details of the

paper, but at least it should be possible to see what comes in and
out of the module. What I could find is in the table below, maybe
you can find more?

Pin Function in/out Value Unit

VDD_3V3 analog supply in 3.0 V
VDD_1V2 digital supply in 1.2 V
VSS ground in 0 V
CLK_1V2 clock in 20 MHz
RST_1V2 digital out 0 or 1.2 V
I_C bias in ? uA?
PHI1_1V2 digital out 0 or 1.2 V
PHI2_1V2 digital out 0 or 1.2 V
DCM_1V2 digital out 0 or 1.2 V

This list contains supplies, clocks, digital outputs, bias currents

and a ground. Let me explain what they are.
84 8 IC and ESD

[Link] Supply

The temperature sensor has two supplies, one analog (3.3 V) and
one digital (1.2 V), which must come from somewhere.

We’re using TinyTapeout

That has ability for both 3.3 V and 1.8 V I believe. An external low
dropout regulator (LDO) provide the digital supply (1.8 V).

See more at Analog Specs

[Link] Ground

Most ICs have a ground, a pin which is considered 0 V. It may

have multiple grounds. Remember that a voltage is only defined
between two points, so it’s actually not true to talk about a voltage
in a node (or on a wire). A voltage is always a differential to
something. We’ve (as in global electronics engineers) have just
agreed that it’s useful to have a “node” or “wire” we consider 0
V.

[Link] Clocks

Most digital need a clock, and TinyTapeout can provide a 50 MHz

clock which should suffice for most things. We could probably just
use that clock for our temperature sensor.

[Link] Digital

We need to read the digital outputs. We could either feed those off
chip, or use a on chip micro-controller. The TinyTapeout includes
options to do both. We could connect digital outputs to the logic
analyzer, and program the MCU to store the readings. Or we could
connect the digital output to the I/O and use an instrument in the
lab.

[Link] Bias

The TinyTapeout does not provide bias currents (that I found), so

that is something you will need to make.
 8.1 What blocks must our IC include? 85

[Link] Conclusion

Even a temperature sensor needs something else on the IC. We

need digital input/output, clock generation (PLL, oscillators),
bias current generators, and voltage regulators (which require a
constant reference voltage).

I would claim that any System-On-Chip will always need these

blocks!

I want you to pause, take a look at the

course plan

and now you might understand why I’ve selected the topics.

[Link] One more thing

There is one more function we need when we have digital logic

and a power supply. We need a “RESET” system.

Digital logic has a fundamental assumption that we can separate

between a “1” and a “0”, which is usually translated to for example
1.8 V (logic 1) and 0 V (logic 0). But if the power supply is at 0 V,
before we connect the battery, then that fundamental assumption
breaks.

When we connect the battery, how do we know the fundamental

assumption is OK? It’s certainly not OK at 30 mV supply. How
about 500 mV? or 1.0 V? How would we know?

Most ICs will have a special analog block that can keep the digital
logic, bias generators, clock generators, input/output and voltage
regulators in a safe state until the power supply is high enough
(for example 1.62 V).

One of the challenges with a POR is that we want to keep the

system in a reset state until we’re sure that the power is on. Another
challenge is that the POR should not consume current.

If we make a level triggered (triggers when VDD reaches a certain

level), then we need a reference, a comparator and maybe other
circuits. As a result, potentially high current.

If we make a delay based POR, then we need a long delay, which

means large resistors or capacitors. Accordingly, high cost.

Below is an idea for a Power-On-Reset (POR) I had way back when.

The POR uses a delay based on the tunneling current in a thin oxide
transistor (2), and uses a thick-oxide transistor (3) as a capacitor.
The output X would go to a Schmitt trigger (5).
86 8 IC and ESD

8.2 Electrostatic Discharge

If you make an IC, you must consider Electrostatic Discharge (ESD)

Protection circuits

ESD events are tricky. They are short (ns), high current (Amps)
and poorly modeled in the SPICE model.

Most SPICE models will not model correctly what happens to an

transistor during an ESD event. The SPICE models are not made to
model what happens during an ESD event, they are made to model
how the transistors behave at low fields and lower current.

But ESD design is a must, you have to think about ESD, otherwise
your IC will never work.

Consider a certain ESD specification, for example 1 kV human

body model, a requirement for an integrated circuit.

By requirement I mean if the 1 kV is not met, then the project will

be delayed until it is fixed. If it’s not fixed, then the project will be
infinitely delayed, or in other words, canceled.

Now imagine it’s your responsibility to ensure it meets the 1 kV

specification, what would you do? I would recommend you read
one of the few ESD books in existence, shown below, and rely on
you understanding of PN-junctions.
 8.2 Electrostatic Discharge 87

The industry has agreed on some common test criteria for elec-
trostatic discharge. Test that model what happens when a person
touches your IC, during soldering, and PCB mounting. If your
IC passes the test then it’s probably going to survive in volume
production
Standards for testing at JEDEC

8.2.1 When do ESD events occur?

8.2.2 Before/during PCB

Human body model (HBM)

Models a person touching a device with a finger.
Charged device model (CDM)
Models a device in an electric field where one pin is suddenly
connected

8.2.3 After PCB

Human body model (HBM)

System level ESD
Once mounted on the PCB, the ICs can be more protected against
ESD events, however, it depends on the PCB, and how that reacts
to a current.
88 8 IC and ESD

Take a look at your USB-A connector, you will notice that the outer
pins, the power and ground, are made such that they connect first,
The 𝐷+ and 𝐷− pins are a bit shorter, so they connect some 𝜇s
later. The reason is ESD. The power and ground usually have a
low impedance connection in decoupling capacitors and power
circuits, so those can handle a large ESD zap. The signals can go
directly to an IC, and thus be more sensitive.

We won’t go into details on System level ESD, as that is more a

PCB type of concern. The physics are the same, but the details are
different.

8.2.4 Human body model (HBM)

▶ Models a person touching a device with a finger

▶ Long duration (around 100 ns)
▶ Acts like a current source into a pin
▶ Can usually be handled in the I/O ring
▶ 4 kV HBM ESD is 2.67 A peak current

1.5 kOhm

100 pF

8.2.5 Charged device model (CDM)

An IC left alone for long enough will equalize the

Fermi potential across the whole IC.

Not entirely a true statement, but roughly true. One exception

is non-volatile memory, like flash, which uses Fowler-Norheim

100 k
1.5 k
 8.2 Electrostatic Discharge 89

tunneling to charge and discharge a capacitor that keeps it’s charge

for a very, very long time.
I’m pretty sure that if you leave an SSD hardrive to the heat death of
1056
the universe in maybe 1010 years, then the charges will equalize,
and the Fermi level will be the same across the whole IC, so it’s
just a matter of time.
Assume there is an equal number of electrons and protons on the
IC. According to Gauss’ law

∮ ∭
1
E · 𝑑S = 𝜌 · 𝑑𝑉
𝜕Ω 𝜖0 𝑉

So there is no external electric field from the IC.

If we place an IC in an electric field, the charges inside will
redistribute. Flip the IC on it’s back, place it on an metal plate with
an insulator in-between, and charge the metal plate to 1 kV.

Inside the integrated circuit, electrons and holes will redistribute

to compensate for the electric field. Closest to the metal plate there
will be a negative charge, and furthest away there will be a positive
charge.
This comes from the fact that if you leave a metal inside an electric
field for long enough the metal will not have any internal field. If
there was an internal field, the charges would move. Over time the
charges will be located at the ends of the metal.
Take a grounded wire, touch one of the pins on the IC. Since we
now have a metal connection between a pin and a low potential
the charges inside the IC will redistribute extremely quickly, on
the order of a few ns.
During this Charged Device Model event the internal fields in the
IC will be chaotic, but at any given point in time, the voltage across
sensitive devices must remain below where the device physically
breaks.
Take the MOSFET transistor. Between the gate and the source there
is an thin oxide, maybe a few nm. If the field strength between gate
90 8 IC and ESD

E and source is high enough, then the force felt by the electrons in
co-valent bonds will be 𝐹® = 𝑞 𝐸®. At some point the co-valent bonds
might break, and the oxide could be permanently damaged. Think
of a lighting bolt through the oxide, it’s a similar process.
Our job, as electronics engineers, is to ensure we put in additional

I
circuits to prevent the fields during a CDM event from causing
damage.
For example, let’s say I have two inverters powered by different
supply, VDD1 and VDD2. If I in my ESD test ground VDD1, and
not VDD2, I will quickly bring VDD1 to zero, while VDD2 might
react slower, and stay closer to 1 kV. The gate source of the PMOS
in the second inverter will see approximately 1 kV across the oxide,
and will break. How could I prevent that?

Assuming some luck, then VDD1 and VDD2 are separate, but
the same voltage, or at least close enough, I can take two diodes,
connected in opposite directions, between VDD1 and VDD2. As
such, when VDD1 is grounded, VDD2 will follow but maybe be
0.6 V higher. As a result, the PMOS gate never sees more than
approximately 0.6 V across the gate oxide, and everyone is happy.
Now imagine an IC will hundreds of supplies, and billions of
inverters. How can I make sure that everything is OK?
CDM is tricky, because there are so many details, and it’s easy to
miss one that makes your circuit break.

8.3 An HBM ESD zap example

Imagine a ESD zap between VSS and VDD. How can we protect
the device?
The positive current enters the VSS, and leaves via the VDD, so
our supplies are flipped up-side down. It’s a fair assumption that
none of the circuits inside will work as intended.
But the IC must not die, so we have to lead the current to ground
somehow
 8.4 Permutations 91

100 k
1.5 k

100 pF

8.4 Permutations

Let’s simplify and think of the possible permutations, shown in

the figure below. We don’t know where the current will enter
nor where it will leave our circuit, so we must make sure that all
combinations are covered.

DD
e

ON 1 vs euro

1 to vno vss
us a Pin
of 2 pin
pin a Uss 2
2 to
1 02 vase PIN
PIN a Vbs
2 A 1

Uss
O

When the current enters VSS and must leave via VDD, then it’s
simple, we can use a diode.

Under normal operation the diode will be reverse biased, and

although it will add some leakage, it will not affect the normal
operation of our IC.
92 8 IC and ESD

I un

PIN
2

on

O Uss

The same is true for current in on VSS and out on PIN. Here we
can also use a diode.

VDP
g

2 PIN

on or

O Uss

For a current in on VDD and out on VSS we have a challenge.

That’s the normal way for current to flow.

For those from Norway that have played a kids game Bjørnen sover,
that’s a apt mental image. We want a circuit that most of the time
sleeps, and does not affect our normal IC operation. But if a huge
current comes in on VDD, and the VDD voltage shoots up fast, the
circuit must wake up and bring the voltage down.

If the circuit triggers under normal operating condition, when your

watching a video on your phone, your battery will drain very fast,
and your phone might even catch fire.
 8.4 Permutations 93

As such, ESD design engineers have a “ESD design window”.

Never let the ESD circuit trigger when VDD < normal, but always
trigger the ESD circuit before VDD > breakdown of circuit.

A circuit that can sometimes be used, if the ESD design window is

not too small, is the Grounded-Gate-NMOS in the figure below.

V70
y or

on
1 NO PIN

É
or
2

Uss p
O

8.4.1 Why does this work?

2,6A

If you try the circuit above in with the normal BSIM spice model,
it will not work. The transistor model does not include that part of
the physics.
94 8 IC and ESD

We need to think about how electrons, holes PN-junctions and

bipolars work.

[Link] Quick refresh of solid-state physics

Electrons sticking to atoms (bound electrons), can only exist at

discrete energy levels. As we bring atoms closer to each-other the
discrete energy levels will split, as computed from Schrodinger,
into bands of allowed energy states. These bands of energy can
have lower energy than the discrete energy levels of the atom.
That’s why some atoms stick together and form molecules through
co-valent bonds, ionic bonds, or whatever the chemists like to call
it. It’s all the same thing, it’s lower energy states that make the
electrons happy, some are strong, some are weak.

For silicon the energy band structure is tricky to compute, so

we simplify to band diagrams that only show the lowest energy
conduction band and highest energy valence band.

Electrons can move freely in the conduction band (until they hit
something, or scatter), and electrons moving in the valence band
act like positive particles, nicknamed holes.

How many free charges there are in a band is given by Fermi-Dirac

distribution and the density of states (allowed energy levels).

If an electron, or a hole have sufficient energy (accelerated by a

field), they can free an electron/hole pair when they scatter off an
atom. If you break too many bonds between atoms, your material
will be damaged.

[Link] The grounded-gate NMOS

Assume a transistor like the one below. The gate, source and bulk
is connected to ground. The drain is connected to a high voltage.

I
ht 30
r
ht
Pto

P
 8.4 Permutations 95

[Link] Avalanche

The first thing that can happen is that the field in the depletion
zone between drain and bulk (1) is large, due to the high voltage
on drain, and the thin depletion region.

In the substrate (P-) there are mostly holes, but there are also
electrons. If an electron diffuses close to the drain region it will be
swept across to drain by the high field.

The high field might accelerate the electron to such an energy that
it can, when it scatters of the atoms in the depletion zone, knock
out an electron/hole pair.

The hole will go to the substrate (2), while the new electron will
continue towards drain. The new electron can also knock out a
new electron/hole pair (energy level is set by impact ionization of
the atom), so can the old one assuming it accelerates enough.

One electron turn into two, two to four, four to eight and so on.
The number of electrons can quickly become large, and we have an
avalanche condition. Same as a snow avalanche, where everything
was quiet and nice, now suddenly, there is a big trouble.

Usually the avalanche process does not damage anything, at least

initially, but it does increase the hole concentration in the bulk.
The number of holes in the bulk will be the same as the number of
electrons freed in the depletion region.

[Link] Forward bias of PN-junction

The extra holes underneath the transistor will increase the local
potential. If the substrate contact (5) is far away, then the local
potential close to the source/bulk PN-junction (3) might increase
enough to significantly increase the number of electrons injected
from source.

Some of the electrons will find a hole, and settle down, while others
will diffuse around. If some of the electrons gets close to the drain
region, and the field in the depletion zone, they will be accelerated
by the drain/bulk field, and can further increase the avalanche
condition.

[Link] Bad things can happen

For a normal transistor, not designed to survive, the electron flow

(4) can cause local damage to the drain. Normally there is nothing
that prevents the current from increasing, and the transistor will
eventually die.
96 8 IC and ESD

If we add a resistor to the drain region (unscilicided drain), however,

we will slow down the electron flow, and we can get a stable
condition, and design a transistor that survives.

[Link] What have we done

Turns out, that every single NMOS has a sleeping bear. A parasitic
bipolar. That’s exactly what this GGNMOS is, a bipolar transis-
tor, although a pretty bad one, that is designed to trigger when
avalanche condition sets in and is designed to survive.

A normal NMOS, however, can also trigger, and if you have not
thought about limiting the electron current, it can die, with IC
killing consequences. Specifically, the drain and source will be
shorted by likely the silicide on top of the drain, and instead of a
transistor with high output impedance, we’ll have a drain source
connection with a few kOhm output impedance.

Take a look at New Ballasting Layout Schemes to Improve ESD

Robustness of I/O Buffers in Fully Silicided CMOS Process for the
pretty pictures you’ll get when the drain/source breaks.

8.5 But I just want a digital input, what do I

need?

Even if it’s only a digital input, you still need to consider ESD
events.

Below is a complete digital input network.

Assuming we have a QFN package package there will be a bond-

wire from the package metal, to our die pad.

Right after the die pad, sometimes under, there will be a primary
ESD protection that can conduct, in all directions, between input,
supply and ground.

From the input it’s common to have a resistor to reduce the

probability of currents going towards the core area.

Before we get to a transistor gate oxide it’s common to have a set

of secondary protection circutis. A resistor further reduces the
current, and two local clamps (GGPMOS and GGNMOS) ensure
that the voltage across the transistor gate does not go to breakdown
levels.
 8.5 But I just want a digital input, what do I need? 97

8.5.1 Input buffer

An input buffer can be seen below. I like to include a RC low-pass

filter to filter out the RF frequencies (I don’t want my input to
toggle if a phone is on top of my circuit).
After the RC filter we need a Schmitt trigger, you can find a Schmitt
trigger at JNW_TR_SKY130A.
The Schmitt trigger must be with thick oxide gates and with IO
supply (for example 3.0 V).
The first inverter must also be a thick oxide inverter, however, the
supply of the inverter will be core supply (for example 1.2 V). The
thick oxide inverter provides a level-shift to core supply.
The last inverter is just to get the polarity of the TO_CORE signal
the same as the input. _
AV DD 1V 8 AV DD 1V 0 AV DD 1V 0
XC2
F ROM P AD 1V 8 T O CORE 1V 0

XC1 XA2 XA3 XA4

.SUBCKT DI_1V8_ST28N AVDD_1V0 AVDD_1V8

(a) + AVSS FROM_PAD_1V8 TO_CORE_1V0
XC1 FILT_O AVSS CAPX10_CV angle=180
XC2 FROM_PAD_1V8 FILT_O AVSS RPPO_S0
+ xoffset=25 yoffset=15
XA5 AVSS TAPCELL_EV xoffset=20
XA2 FILT_O SCHMITT_O AVDD_1V8 AVSS SCX1_EV
XA4
T O CORE 1V 0

XA5a AVSS TAPCELL_EV yoffset=20

XA3 SCHMITT_O INV_O AVDD_1V0 AVSS IVX1_EV
XC2
XA4 INV_O TO_CORE_1V0 AVDD_1V0 AVSS IVX8_CV
F ROM P AD 1V 8 + yoffset=15
XA6 AVSS TAPCELL_CV

XA3 .ENDS
(b)

{ "name" : "DI_1V8_ST28N",
XC1 "boundaryIgnoreRouting" : 0,
"composite" : 1, "noPowerRoute" : 1,
"schematic" : 0,
"class" : "Layout::LayoutDigitalCell",
XA2 "afterPlace" :{
"addPowerRings" :[
["M1","AVDD_1V0","t"],
["M1","AVSS","btrl"]
]
},
"beforeRoute" : {
"addPowerConnections" : [
["AVDD_1V0","XA","top"],
["AVSS","XC","left"],
["AVSS","XA4|XA2","bottom"]
],
"addConnectivityRoutes" : [
["M3","FILT_O","--|-","onTopR"],
["M2","SCHMITT_O","-|--"],
["M1","INV_O","-|--"]
]
}
}
OD CO PO M1 M2 M3 M4
(c) (d)
98 8 IC and ESD

8.6 Latch-up

8.6.1 How can current in one place lead to a current

somewhere else?
2,6A
Another fun physics problem can happen in digital logic that is
close to an electron source, like a connection to the real world, what
we call a pad. A pad is where you connect the bond-wire in a QFN
type of package with wire-bonding

Assume we have the circuit below.

Mt
lo too
O o

Toome tooma

We can draw a cross section of the inverter.

[Link] Electron injection

Assume that we have an electron source, for example a pad that

is below ground for a bit. This will inject electrons into the sub-
strate/bulk (1) and electrons will diffuse around.

If some of the electrons comes close to the N-well depletion region

(2) they will be swept across by the built-in field. As a result, the
potential of the N-well will decrease, and we can forward bias the
source or drain junction of a PMOS.
 8.6 Latch-up 99

[Link] Forward biased PMOS source or drain junction

With a forward biased source/bulk junction (2), holes will be

injected into the N-Well, but similarly to the GGNMOS, they might
not find a electron immediately.

Some of the holes can reach the depletion region towards our
NMOS, and be swept across the junction.

[Link] Forward biased NMOS source or drain junction

The increase in hole concentration underneath the NMOS can

forward bias the PN diode between source (or drain) and bulk.
If this happens, then we get electron injection into bulk. Some
of those electrons can reach the N-well depletion region, and be
swept across (3).

[Link] Positive-feedback

Now we have a condition where the process accellerates, and

locks-up. Once turned on, this circuit will not turn off until the
supply is low.

This is a phenomena called latch-up. Similar to ESD circuits, latch-

up can short the supply to ground, and make things burn.

That is why, when we have digital logic, we need to be extra careful

close to the connection to the real world. Latch-up is bad.

We can prevent latch-up if we ensure that the electrons that start

the process never reach the N-wells. We can also prevent latch-up
by separating the NMOS and PMOS by guard rings (connections
to ground, or indeed supply), to serve as places where all these
electrons and holes can go.

Maybe it seems like a rare event for latch-up to happen, but trust
me, it’s real, and it can happen in the strangest places. Similar to
ESD, it’s a problem that can kill an IC, and make us pay another X
million dollars for a new tapeout, in addition to the layout work
needed to fix it.

Latch-up is why you will find the design rule check complaining if
you don’t have enough substrate connections to ground, or N-well
connections to power close to your transistors.

Similar to the GGNMOS, this circuit, a thyristor can be a useful

circuit in ESD design. If we can trigger the thyristor when the VDD
shoots to high, then we can create a good ESD protection circuit.

See low-leakage ESD for a few examples.

A model with the parasitic bipolars can be seen below.

100 8 IC and ESD

You must always handle ESD on an IC

▶ Do everything yourself
▶ Use libraries from foundry
▶ Get help [Link]

8.7 Want to learn more?

ESD (Electrostatic Discharge) Protection Design for Nanoelectron-

ics in CMOS Technology
Overview on Latch-Up Prevention in CMOS Integrated Circuits
by Circuit Solutions
Overview on ESD Protection Designs of Low-Parasitic Capacitance
for RF ICs in CMOS Technologies
 References and bias 9
Keywords: VREF, IREF, VD, BGAP, LVBGAP, VI, GMCELL 9.1 Routing . . . . . . . . 101
9.2 Bandgap voltage
In our testbenches, and trial schematics, it’s common to include reference . . . . . . . 104
voltage sources and current sources. However, the ideal voltage 9.2.1 A voltage complemen-
source, or ideal current source does not exist in the real world. tary to temperature
There is no such thing. (CTAT) . . . . . . . . . 104
9.2.2 A current proportional
We can come close to creating a voltage source, a known voltage, to temperature (PTAT) 105
with a low source impedance, but not zero impedance. And it 9.2.3 How to combine a
won’t be infinitely fast either. If we suddenly decide to pull 1 kA CTAT with a PTAT ? 106
9.2.4 Brokaw reference . . 107
from a lab supply I promise you the voltage will drop.
9.2.5 Low voltage bandgap 109
So how do we create something that is a good enough voltage and 9.3 Bias . . . . . . . . . . 112
current source on an IC? 9.3.1 Voltage to current
conversion . . . . . . 112
9.3.2 GM Cell . . . . . . . . 113
9.4 Want to learn more? 115

9.1 Routing

Before we take a take a look at the voltage and current source,

I want you to think about how you would route a current, or a
voltage on an IC.

Assume we have a known voltage on our IC. How can we make

sure we can share that voltage across an IC?

A voltage is only defined between two points. There is no such

thing as the voltage at a point on a wire, nor voltage in a node. Yes,
102 9 References and bias

I know we say that, but it’s not right. What we forget is that by
voltage in a node we always, always mean voltage in a node referred to
ground.

We’ve invented this magical place called ground, the final resting
place of all electrons, and we have agreed that all voltages refer to
that point.

As such, when we say “Voltage in node A is 1V”, what we actually

mean is “Voltage in node A is 1 V referred to ground”.

Maybe you now understand why we can’t just route a voltage

across the IC, the other side might not have the same ground.
The other side might have a different impedance to ground, and
the impedance might be a function of time, voltage, frequency
temperature, pressure and presence of gremlins.

Most of the time, in order not to think about the ground impedance,
we choose to route a known quantity as a current instead of a
voltage. That means, however, we must convert from a voltage to a
current, but we can do that with a resistor (you’ll see later), and
as long as the resistor is the same on the other side of the IC, then
we’ll know what the voltage is.
 9.1 Routing 103

Resistors have finite matching across die, let’s say 2 % 3-sigma

variation. As a result, if we need a accurate voltage reference, then
we must distribute voltage.

But how can “It’s better to distribute a voltage as a current across

the IC, it’s more accurate” and “If you need something really
accurate, you must distribute voltage” both be true?

Imagine I have a 0.5 % 3-sigma accurate voltage reference at 1.22 V,

that’s a sigma of 2 mV. I need this reference voltage on a block on
the other side of the IC, I don’t want to distribute voltage, because
I don’t know that the ground is the same on the other side, at least
not to a precision of 2 mV. I convert the voltage into a current,
however, I know the R has a 2 % 3-sigma across die, so my error
budget immediately increases to 2.06%.

But what if I must have 0.5 % 3-sigma voltage in the block? For
example in a battery charger, where the 4.3 V termination voltage
must be 1 % accurate? I have no choice but to go with voltage
directly from the reference, but the key point, is then the receiving
block cannot be on the other side of the IC. The reference must be
right next to my block.

I could use two references on my IC, one for the ADC and one
for the battery charger. Ask yourself, “Why do we care if there is
two references?” And the answer is “Silicon area is expensive, to
make things cheep, we must make things small”, in other words,
we should not duplicate features unless we absolutely have to.
104 9 References and bias

9.2 Bandgap voltage reference

9.2.1 A voltage complementary to temperature (CTAT)

A diode connected bipolar transistor, or indeed a PN diode, assum-

ing a fixed current, will have a voltage across that is temperature
dependent

 𝑉𝐵𝐸
 𝑉𝐵𝐸
𝐼 𝐷 = 𝐼𝑆 𝑒 𝑉𝑇
− 1 + 𝐼 𝐵 ≈ 𝐼𝑆 𝑒 𝑉𝑇

As 𝐼𝑆 is much smaller that 𝐼𝐷 we can ignore the -1, and we assume

that the base current is much smaller than the drain current.

Re-arranging for 𝑉𝐵𝐸 and inserting for

𝑘𝑇
𝑉𝑇 =
𝑞

𝑘𝑇 𝐼𝐶
𝑉𝐵𝐸 = ln
𝑞 𝐼𝑆

𝐷𝑛 𝐷𝑝
 
𝐼𝑆 = 𝑞𝐴𝑛 𝑖2 +
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷

From this equation, it looks like the voltage 𝑉𝐵𝐸 is proportional to

temperature
 9.2 Bandgap voltage reference 105

However, it turns out that the 𝑉𝐵𝐸 decreases with temperature due
to the temperature dependence of 𝐼𝑆 .
The 𝑉𝐵𝐸 is linear with temperature with a property that if you
extrapolate the 𝑉𝐵𝐸 line to zero Kelvin, then all diode voltages
seem to meet at the bandgap voltage of silicon (approx 1.12 eV).
To see the temperature coefficient, I find it easier to re-arrange the
equation above.
Some algebra (see Diodes)

𝑘𝑇
𝑉𝐵𝐸 = (ℓ − 3 ln 𝑇) + 𝑉𝐺
𝑞

The ℓ is a temperature independent constant given by

𝐷𝑛 𝐷𝑝 2𝜋𝑘
 
3 3
ℓ = ln 𝐼𝐶 −ln 𝑞𝐴−ln + −2 ln 2− ln 𝑚𝑛∗ − ln 𝑚 𝑝∗ −3 ln 2
𝐿 𝑛 𝑁𝐴 𝐿 𝑝 𝑁𝐷 2 2 ℎ

And if we plot the diode voltage, we can see that the voltage
decreases as a function of temperature.

0.95
Diode voltage [V]

0.90

0.85

25 0 25 50 75 100 125
Non-linear component (mV)

2
25 0 25 50 75 100 125
Temperature [C]

9.2.2 A current proportional to temperature (PTAT)

If we take two diodes, or bipolars, biased at different current

densities, as shown in the figure below, then

𝐼𝐷
𝑉𝐷 1 = 𝑉𝑇 ln
𝐼𝑆1

𝐼𝐷
𝑉𝐷 2 = 𝑉𝑇 ln
𝐼𝑆2
106 9 References and bias

The OTA will force the voltage on top of the resistor to be equal to
𝑉𝐷 1 , thus the voltage across the resistor 𝑅 1 is

𝐼𝐷 𝐼𝐷 𝐼𝑆2
𝑉𝐷 1 − 𝑉𝐷 2 = 𝑉𝑇 ln − 𝑉𝑇 ln = 𝑉𝑇 ln = 𝑉𝑇 ln 𝑁
𝐼𝑆1 𝐼𝑆2 𝐼𝑆1

This is a remarkable result. The difference between two voltages is

only defined by boltzmann’s constant, temperature, charge, and a
know size difference.

This differential voltage can be used to read out directly the

temperature on an IC, provided we have a known voltage to
compare with.

We often call this voltage Δ𝑉𝐷 or Δ𝑉𝐵𝐸 , and we can clearly see it’s
proportional to absolute temperature.

We know that the 𝑉𝐷 decreases linearly with temperature, so if we

combined a multi-plum of the Δ𝑉𝐵𝐸 with a 𝑉𝐷 voltage, then we
should get a constant voltage.

ID

a verb in
R1 R
V02 V02
I N 1 N
D1 D2 D Dz

9.2.3 How to combine a CTAT with a PTAT ?

One method is the figure below. The voltage across resistor 𝑅 2

would compensate for the decrease in 𝑉𝐷 3 , as such, 𝑅 2 would be
bigger than 𝑅 1 .
VREE

R2 R2
 9.2 Bandgap voltage reference 107

ID VREE
b in
R RL VREE
a verb in
V02 V02
R1 R RL
1 N
D V02
Dz 03 V02 V02
I N 1 N
D1 D2 D Dz 03
Another method would be to stack the 𝑅 2 on top of 𝑅 1 as shown
below.

REE

VREE

R2 R2
Vn
R1
V02
I N
D1 D2

9.2.4 Brokaw reference

Paul Brokaw was a pioneer within reference circuits. Below is the

Brokaw reference, which I think was first published in A simple
108 9 References and bias

three-terminal IC bandgap reference.

I 1 DUBE V
Rz Ry
I Ia Va IRz

Q Q2 Ir

In
8
use
Ere
2
É V21 VBG VRtVBE
Ny 2
The opamp ensures the two bipolars have the same current. 𝑄 1 is
larger than 𝑄 2 . The Δ𝑉𝐵𝐸 is across the 𝑅 2 , so we know the current
𝐼 . We know that 𝑅1 must then have 2𝐼 .
pr
The voltage at the output will then be.

𝑘𝑇 𝑇0 𝑘 𝐽2 2𝑅 2 𝑉𝐺0 − 𝑉𝑏𝑒 0
 

to do I
𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln +𝑇 ln −
𝑞 𝑇 𝑞 𝐽1 𝑅 1 𝑇0

where 𝑉𝐺0 is the bandgap, 𝑉𝑏𝑒 0 is the base emitter measured at a

temperature 𝑇0 and the 𝐽 ’s are the current densities.

To get a constant output voltage, the relationship between the

resistors should be approximately

𝑅2 𝑉𝐺0 − 𝑉𝑏𝑒 0
=
𝑅1 2𝑇0 𝑘 ln( 𝐽2 )
𝑞 𝐽1

In typical simulations, the variation can be low over the temperature

range. The second order error is the remaining error from

𝑘𝑇 𝑇0 𝑘 𝐽2 2𝑅 2 𝑉𝐺0 − 𝑉𝑏𝑒 0
 
𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln +𝑇 ln −
𝑞 𝑇 𝑞 𝐽1 𝑅 1 𝑇0
 9.2 Bandgap voltage reference 109

Where the last term is zero, so

𝑘𝑇 𝑇0
𝑉𝐵𝐺 = 𝑉𝐺0 + (𝑚 − 1) ln
𝑞 𝑇

Over corners, I do expect that there is variation. It may be that the

𝑉𝐷 modeling is not perfect, which means the cancellation of the
last term is incomplete.

We could include trimming of PTAT to calibrate for the remaining

error, however, if we wanted to remove the linear gradient, we
would need a two point temperature test of every IC, which too
expensive for low-cost devices.

9.2.5 Low voltage bandgap

The Brokaw reference, and others, have a 1.2 V output voltage,

which is hard if your supply is below about 1.4 V. As such, people
have investigated lower voltage references. The original circuit
was presented by Banba A CMOS bandgap reference circuit with
sub-1-V operation
110 9 References and bias

In real ICs though, you should ask yourself long and hard whether
you really need these low-voltage references. Most ICs today still
have a high voltage, either 1.8 V or 3.0 V.

If you do need them though, consider the circuit below. We have

two diodes at different current densities. The Δ𝑉𝐷 will be across
𝑅 1 . The voltage at the input of the OTA will be 𝑉𝐷 and the OTA
will ensure the both are equal.

The current will then be

Δ𝑉𝐷
𝐼1 =
𝑅1

and we know the current increases with temperature, since Δ𝑉𝐷

increases with temperature.

TN

In the figure below I’ve used Δ𝑉𝐵𝐸 , it’s the same as Δ𝑉𝐷 , so ignore
that error.

Assume we copy the 𝑉𝐷 to another node, and place it across a

second resistor 𝑅 2 , as shown in the figure below. The current in
this second resistor is then

𝑉𝐷
𝐼2 =
𝑅2

and we know the current decreases with temperature, since 𝑉𝐷

decreases with temperature.
 9.2 Bandgap voltage reference 111

From before, we know the current in 𝑅 1 is proportional to temper-

ature. As such, if we combine the two with the correct proportions,
then we can get a current that does not change with temperature.

I WE

R
R2
9N

Let’s remove the OTA, and connect 𝑅 2 directly to 𝑉𝐷 nodes, you

should convince yourself of the fact that this does not change 𝐼1 at
all.

Ra in
ti NE R
Iz
13g

It does, however, change the current in the PMOS. Provided we scale

𝑅 2 correctly, then the PTAT 𝐼1 can be compensated by the CTAT 𝐼2 ,
and we have a current that is independent of temperature.

𝑉𝐷 Δ𝑉𝐷
𝐼𝑃𝑀𝑂𝑆 = +
𝑅2 𝑅1
112 9 References and bias

Assuming we copy the current into another resistor 𝑅 3 , as shown

below, we can get a voltage that is

𝑉𝐷 Δ𝑉𝐷
 
𝑉𝑂𝑈𝑇 = 𝑅 3 +
𝑅2 𝑅1

Where the output voltage can be chosen freely, and indeed be lower
than 1.2 V.

p p
ti MI p
12 152
Rz

9.3 Bias

Sometimes we just need a current

BE

9.3.1 Voltage to current conversion

With a known voltage, we can convert to a known current with the

circuit below.

On-chip we don’t have accurate resistors, but for bias currents, it’s
usually ok with + − 20 variation (the variation of R).

Across a IC, we can expect the resistors to match within a few

percent, as such, we can recreate a voltage with a accuracy of a few
percent difference from the original if we have a second resistor on
the other side of the IC.

If we wanted to create an accurate current, then we’d trim the R

until the current is what we want.
 9.3 Bias 113

IRV
R

9.3.2 GM Cell

Ib ImmbxEMVett
lil Vetti tremlett
ITEM
j vett Mf Velte
6Me Y
T
1 1
Velt 2 Veltz

Vo Veltz
KI gu If
F Vo ZI
Vet If
ist Ist
Z
Its
y
Sometimes we don’t need a full bandgap reference. In those cases,
we can use a GM cell, where the impedance could be a resistor, in
Vo
which case Vo

Z gu ta
𝑉𝑜 = 𝑉𝐺𝑆1 − 𝑉𝐺𝑆2 = 𝑉𝑒 𝑓 𝑓 1 + 𝑉𝑡𝑛 − 𝑉𝑒 𝑓 𝑓 2 − 𝑉𝑡𝑛 = 𝑉𝑒 𝑓 𝑓 1 − 𝑉𝑒 𝑓 𝑓 2

Assuming strong inversion, then

1 𝑊1 2
𝐼𝐷 1 = 𝜇𝑛 𝐶 𝑜𝑥 𝑉
2 𝐿1 𝑒 𝑓 𝑓 1
114 9 References and bias

1 𝑊1
𝐼𝐷 2 = 𝜇𝑛 𝐶 𝑜𝑥 4 𝑉𝑒2𝑓 𝑓 2
2 𝐿1

𝐼𝐷 1 = 𝐼𝐷 2

1 𝑊1 2 1 𝑊1
𝜇𝑛 𝐶 𝑜𝑥 𝑉𝑒 𝑓 𝑓 1 = 𝜇𝑛 𝐶 𝑜𝑥 4 𝑉𝑒2𝑓 𝑓 2
2 𝐿1 2 𝐿1

𝑉𝑒 𝑓 𝑓 1 = 2𝑉𝑒 𝑓 𝑓 2

Inserted into above

1 1
𝑉𝑜 = 𝑉𝑒 𝑓 𝑓 1 − 𝑉𝑒 𝑓 𝑓 1 = 𝑉𝑒 𝑓 𝑓 1
2 2

Still assuming strong inversion, such that

2𝐼 𝑑
𝑔𝑚 =
𝑉𝑒 𝑓 𝑓

we find that

𝑉𝑒 𝑓 𝑓 1
𝐼=
2𝑍

1
𝑍⇒
𝑔𝑚

If we use a resistor for Z, then we can get a transconductance that

is proportional to a resistor, or a constant 𝑔𝑚 bias.

We can use other things for Z, like a switched capacitor

Vo
Vo

z Co g arr
air
C E

V I R Qc Vo C

I Qf
E
 9.4 Want to learn more? 115

9.4 Want to learn more?

A simple three-terminal IC bandgap reference

A CMOS bandgap reference circuit with sub-1-V operation
A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference
without requiring low threshold voltage device
The Bandgap Reference
The Design of a Low-Voltage Bandgap Reference
 Analog frontend and filters 10
Keywords: H(s), BiQuad, Gm-C, Active-RC, OTA 10.1 Introduction . . . . 117
10.2 Filters . . . . . . . . . 119
10.2.1 First order filter . . . 120
10.2.2 Second order filter . 121
10.1 Introduction 10.2.3 How do we im-
plement the filter
sections? . . . . . . . 122
The world is analog, and these days, we do most signal processing 10.3 Gm-C . . . . . . . . . 122
in the digital domain. With digital signal processing we can reuse 10.3.1 Differential Gm-C . 123
the work of others, buy finished IPs, and probably do processing 10.3.2 Finding a transcon-
at lower cost than for analog. ductor . . . . . . . . . 125
10.4 Active-RC . . . . . . 126
Analog signals, however, might not be suitable for conversion to 10.4.1 General purpose first
digital. A sensor might have a high, or low impedance, and have order filter . . . . . . 126
the signal in the voltage, current, charge or other domain. 10.4.2 General purpose
biquad . . . . . . . . 129
To translate the sensor signal into something that can be converted 10.5 The OTA is not ideal 130
to digital we use analog front-ends (AFE). How the AFE looks 10.6 Example circuit . . . 130
will depend on application, but it’s common to have amplification, 10.7 My favorite OTA . . 131
frequency selectivity or domain transfer, for example current to 10.8 Want to learn more? 133
voltage.

An ADC will have a sample rate, and will alias (or fold) any signal
above half the sample rate, as such, we also must include a anti-
Why
alias filter in AFE that reduces any signal outside the bandwidth
of the ADC as close to zero as we need.

Sensor AFE Abc

Amplification

Frequency selectivity
discrete time?

Discrete value
Bits
(Quantization)
Domain transfer

One example of an analog frontend is the recieve chain of a typical

bluetooth radio. The signal that arrives at the antenna, or the
Sensor AFE Abc
“sensor”, can be weak, maybe -90 dBm.

At the same time, at another frequency, there could be a unwanted

signal, or blocker, of -30 dBm

Assume for the moment we actually used an ADC at the antenna,

how many bits would we need?

Bluetooth uses Gaussian Frequency Shift Keying, which is a con-

stant envelope binary modulation, and it’s ususally sufficient with
lowSensor
number AFE
RFEof bits, ADC8-bits for the signal is more than
assume
enough.
118 10 Analog frontend and filters

If we assume the maximum of the ADC should be the blocker in

the table below, and the resolution of the digital should be given
by

What Power [dBm] Voltage [V]

Blocker -30 7m
Wanted -90 7u
Resolution Wanted/255 = 28 n

Then we can calculate the number of bits as

7 mV
ADC resolution ⇒ ln /ln 2 ≈ 18 bits
28 nV

If we were to sample at 5 GHz, to ensure the bandwidth is sufficient

for a 2.480 GHz maximum frequency we can actually compute the
power consumption.

Given the Walden figure of merit of

𝑃
𝐹𝑂 𝑀 =
2𝐸𝑁 𝑂𝐵 𝑓 𝑠

The best FOM in literature is about 1 fJ/step, so

𝑃 = 1 fJ/step × 218 × 5GHz = 1.31 W

If we look at a typical system, like the Whoop. We can have a look

at teardowns, to find the battery size.

Whoop battery is 205mAh at 3.8 V

Then we can compute the lifetime running an ADC based Bluetooth

Radio

205 mAh
Hours = = 0.6 h
1.32 W/3.8 V

I know my whoop lasts for almost a week, so it can’t be what

Bluetooth ICs do.

I know a little bit about radio’s, especially inside the Whoop, since
it has

Nordic Inside

I can’t tell you how the Nordic radio works, but I can tell you
how others usually make their radio’s. The typical radio below has
multiple blocks in the AFE.
 10.2 Filters 119

Sensor AFE Abc

First is low-noise amplifier (LNA) amplifying the signal by maybe

10 times. The LNA reduces the noise impact of the following blocks.
The next is the complex mixer stage, which shifts the input signal
from radio frequency down to a low frequency, but higher than the
bandwidth of the wanted signal. Then there is a complex anti-alias

unwantedSensor RFE ADC

filter, also called a poly-phase filter, which rejects parts of the
AFE
signals. Lastly there is a complex ADC to convert to
digital.

In digital we can further filter to select exactly the wanted signal.

Digital filters can have high stop band attenuation at a low power
and cost. There could also be digital mixers to further reduce the
frequency.

The AFE makes the system more efficient. In the 5 GHz ADC
output, from the example above, there’s lot’s of information that
we don’t use.

An AFE can reduce the system power consumption by constraining

digital information processing and conversion to the parts of the
spectrum with information of interest.

There are instances, though, where the full 2.5 GHz bandwidth has
useful information. Imagine in a cellular base station that should
process multiple cell-phones at the same time. In that case, it could
make sense with an ADC at the antenna.

What make sense depends on the application.

10.2 Filters

A filter can be fully described by the transfer function, usually

output
denoted by 𝐻(𝑠) = input .

Most people will today start design with a high-level simulation,

in for example Matlab, or Python. Once they know roughly the
transfer function, they will implement the actual analog circuit.

For us, as analog designers, the question becomes “given an 𝐻(𝑠),

how do we make an analog circuit?” It can be shown that a
120 10 Analog frontend and filters

combination of 1’st and 2’nd order stages can synthesize any order
filter.

Once we have the first and second order stages, we can start looking
into circuits.

10.2.1 First order filter

In the book they use signal flow graphs to show how the first
order stage can be generated. By selecting the coefficients 𝑘 0 , 𝑘 1
and 𝜔0 we can get any first order filter, and thus match the 𝐻(𝑠)
we want.

I would encourage you to try and derive from the signal flow graph
the 𝐻(𝑠) and prove to your self the equation is correct.

Vi Ys Vo

Second order
Signal flow graphs are useful when dealing with linear systems.

The instructions to compute the transfer functions are

1. any line with a coefficient is a multiplier MÉE

2. any box output is a multiplication of the coefficient and the
input
3. any sum, well, sum all inputs
a 4. be aware of gremlins (a sudden -+ swap)

𝑉𝑜 (𝑠) 𝑘 1 𝑠 + 𝑘 0
𝐻(𝑠) = =
𝑉𝑖 (𝑠) 𝑠 + 𝑤𝑜

Let’s call the 1/𝑠 box input 𝑢

K2 S
 10.2 Filters 121

𝑢 = (𝑘 0 + 𝑘 1 𝑠)𝑉𝑖 − 𝜔0𝑉𝑜

𝑉𝑜 = 𝑢/𝑠
Wo

Vi ko V0
𝑢 = 𝑉𝑜 𝑠 = (𝑘 0 + 𝑘1 𝑠)𝑉𝑖 − 𝜔0𝑉𝑜
Ks

(𝑠 + 𝜔0 )𝑉𝑜 = (𝑘 0 + 𝑘 1 𝑠)𝑉𝑖

Second order
𝑉𝑜 𝑘1 𝑠 + 𝑘0
=
𝑉𝑖 𝑠 + 𝜔0

10.2.2 Second order filter

Bi-quadratic is a general purpose second order filter.

V25
Bi-quadratic just means “there are two quadratic equations”. Once
we match the 𝑘 ’s 𝜔0 and 𝑄 to our wanted 𝐻(𝑠) we can proceed
with the circuit implementation.

Wo

Wo Q

Vi kowo wo
V0

has

𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜

Follow exactly the same principles as for first order signal flow
graph. If you fail, and you can’t find the problem with your algebra,
then maybe you need to use Maple or Mathcad.

I guess you could also spend hours training on examples to get

better at the algebra. Personally I find such tasks mind numbingly
boring, and of little value. What’s important is to remember that
you can always look up the equation for a bi-quad in a book.
122 10 Analog frontend and filters

10.2.3 How do we implement the filter sections?

While I’m sure you can invent new types of filters, and there
probably are advanced filters, I would say there is roughly three
types. Passive filters, that do not have gain. Active-RC filters, with
OTAs, and usually trivial to make linear. And Gm-C filters, where
we use the transconductance of a transistor and a capacitor to
set the coefficients. Gm-C are usually more power efficient than
Active-RC, but they are also more difficult to make linear.

In many AFEs, or indeed Sigma-Delta modulator loop filters, it’s

common to find a first Active-RC stage, and then Gm-C for later
stages.

10.3 Gm-C

In the figure below you can see a typical Gm-C filter and the
equations for the transfer function. One important thing to note

Gnc
is that this is Gm with capital G, not the 𝑔𝑚 that we use for small
signal analysis.

In a Gm-C filter the input and output nodes can have significant
swing, and thus cannot always be considered small signal.

Io
Vi Gm Vo V
c

𝐼𝑜 𝜔𝑡𝑖
𝑉𝑜 = = 𝑉𝑖
𝑠𝐶 𝑠

𝐺𝑚
𝜔𝑡𝑖 =
𝐶
Io
10.3.1 Differential Gm-C
wei
10.3 Gm-C

of
123

In a real IC we would almost always use differential circuit, as

shown below. The transfer function is luckily the same.

gmVi
V
Vit Gm ut am
to Gulf I
grivi guv
Vo
IE 𝑠𝐶𝑉𝑜 = 𝐺 𝑚 𝑉 𝑖
WEVi
wei e
of
𝑉𝑜 𝐺𝑚
𝐻(𝑠) = =
I 𝑉𝑖 𝑠𝐶
2
Differential circuits are fantastic for multiple reasons, power supply

Use 3D
rejection ratio, noise immunity, symmetric non-linearity, but the

Crease
qualities I like the most is that the outputs can be flipped to
implement negative, or positive gain.

figure
ut am
I c

guv
𝑉𝑜 𝐺𝑚
𝐻(𝑠) = =−
𝑉𝑖 𝑠𝐶
124 10 Analog frontend and filters

The figure below shows a implementation of a first-order Gm-C

filter that matches our signal flow graph.

I would encourage you to try and calculate the transfer function.

ex
Ganz

is
Vi s iz
Gm
i t Vols
do

do
i
is
iz

Given the transfer function from the signal flow graph, we see that
we can select 𝐶 𝑥 , 𝐶 𝑎 and 𝐺 𝑚 to get the desired 𝑘 ’s and 𝜔0
Gy
G Gs
𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
Ca
or
𝑠 + 𝑤𝑜 CB
GL
Vi G
63
𝑠 𝐶 𝑎𝐶+𝐶
𝑥
𝑥
+ 𝐺𝑚1
𝐶 𝑎 +𝐶 𝑥
Vo
𝐻(𝑠) = 𝐺𝑚2
𝑠+ 𝐶 𝑎 +𝐶 𝑥

Below is a general purpose Gm-C bi-quadratic system.

Gmt Gul Gms Vout

ca c

20

Guy Gms
Vin
20

𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜
 10.3 Gm-C 125

𝑠 2 𝐶𝑋𝐶+𝐶
𝑋
𝐵
+ 𝑠 𝐶𝑋𝐺+𝐶
𝑚5
𝐵
+ 𝐺𝑚2 𝐺𝑚4
𝐶 𝐴 (𝐶 𝑋 +𝐶 𝐵 )
𝐻(𝑠) =
𝑠 2 + 𝑠 𝐶𝑋𝐺+𝐶
𝑚2
𝐵
+ 𝐺𝑚1 𝐺𝑚2
𝐶 𝐴 (𝐶 𝑋 +𝐶 𝐵 )

10.3.2 Finding a transconductor

Although you can start with the Gm-C cells in the book, I would
actually choose to look at a few papers first.

The main reason is that any book is many years old. Ideas turn
into papers, papers turn into books, and by the time you read the
book, then there might be more optimal circuits for the technology
you work in.

If I were to do a design in 22 nm FDSOI I would first see if someone

has already done that, and take a look at the strategy they used. If
I can’t find any in 22 nm FDSOI, then I’d find a technology close to
the same supply voltage.

Start with IEEEXplore

I could not find a 22 nm FDSOI Gm-C based circuit on the initial

search. If I was to actually make a Gm-C circuit for industry I
would probably spend a bit more time to see if any have done it,
maybe expanding to other journals or conferences.

I know of Pieter Harpe, and his work is usually superb, so I

would take a closer look at A 77.3-dB SNDR 62.5-kHz Bandwidth
Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled
Gm-C Integrator

And from Figure 10 a) we can see it’s a similar Gm-C cell as chapter
12.5.4 in CJM.

One of my Ph.d’s used the transonductor below on his master

thesis Design Considerations for a Low-Power Control-Bounded
A/D Converter.
 inherent linearity and the state boundary bx .
The schematic for the transconductor considered in this thesis is given in
126 figure
10 Analog frontend and5.16.
filtersSpectre netlist and some additional design details are given
in appendix F and a summary of some key performance metrics is listed
in table 5.3.

Vdd
Vcmf b

M3a M3b
io Vdd Vdd i+
o

M2a M2b

vi+ M1a M1b vi

Vbn Mbn1

Vss

Figure 5.16: Transconductor schematic

The transconductor comprises a single di↵erential pair (M1 ) with an ac-

tive load (M3 ). The cascode/common-gate transistors, M2 , are included
10.4Miller-e↵ect
to limit the Active-RC on the gate-drain capacitor Cgd1 of the input
transistors. The transconductor achieves a DC-gain of about 150. In
the absence of M2 , Cgd1 would have been boosted from about 200aF to
more thanThe Active-RC filter should be well know at this point. However,
20fF, thereby becoming a dominating capacitor at the floating
what might be new is that the open loop gain 𝐴0 and unity gain
gate node. The DC-gain, and thereby the gate-drain capacitance, follow
𝜔𝑡 𝑎

72
10.4.1 General purpose first order filter

Below is a general purpose first order filter and the transfer function.
I’ve used the condutance 𝐺 = 𝑅1 instead of the resistance. The
reason is that it sometimes makes the equations easier to work
out.

If you’re stuck on calculating a transfer function, then try and

switch to conductance, and see if it resolves.

I often get my mind mixed up when calculating transfer functions.

I don’t know if it’s only me, but if it’s you also, then don’t worry,
it’s not that often you have to work out transfer functions.

Once in a while, however, you will have a problem where you must
calculate the transfer function. Sometimes it’s because you’ll need
to understand where the poles/zeros are in a circuit, or you’re
trying to come up with a clever idea, or I decide to give this exact
problem on the exam.
 10.4 Active-RC 127

Ga

Ven Ci Cr
Vout
G

𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 + 𝑤𝑜

− 𝐶𝐶12 𝑠 − 𝐺1
𝐶2
𝐻(𝑠) = 𝐺2
𝑠+ 𝐶2

VI
Let’s work through the calculation.
Vo
[Link] Step 1: Simplify

The conductance from 𝑉𝑖𝑛 to virtual ground can be written as

𝐺 𝑖𝑛 = 𝐺1 + 𝑠𝐶1
The feedback conductance, between 𝑉𝑜𝑢𝑡 and virtual ground I
write as
𝐺 𝑓 𝑏 = 𝐺2 + 𝑠𝐶2

[Link] Step 2: Remember how an OTA works

An ideal OTA will force its inputs to be the same. As a result, the
potential at OTA− input must be 0.
The input current must then be
𝐼 𝑖𝑛 = 𝐺 𝑖𝑛 𝑉𝑖𝑛
Here it’s important to remember that there is no way for the input
current to enter the OTA. The OTA is high impedance. The input
current must escape through the output conductance 𝐺 𝑓 𝑏 .
What actually happens is that the OTA will change the output
voltage 𝑉𝑜𝑢𝑡 until the feedback current , 𝐼 𝑓 𝑏 , exactly matches 𝐼 𝑖𝑛 .
That’s the only way to maintain the virtual ground at 0 V. If
the currents do not match, the voltage at virtual ground cannot
continue to be 0 V, the voltage must change.
128 10 Analog frontend and filters

[Link] Step 3: Rant a bit

The previous paragraph should trigger your spidy sense. Words

like “exactly matches” don’t exist in the real world. As such, how
closely the currents match must affect the transfer function. The
open loop gain 𝐴0 of the OTA matters. How fast the OTA can
react to a change in voltage on the virtual ground, approximated
by the unity-gain frequency 𝜔𝑡 𝑎 (the frequency where the gain of
the OTA equals 1, or 0 dB), matters. The input impedance of the
OTA, whether the gate leakage of the input differential pair due
to quantum tunneling, or the capacitance of the input differential
pair, matters. How much current the OTA can deliver (set by slew
rate), matters.

Active-RC filter design is “How do I design my OTA so it’s good

enough for the filter”. That’s also why, for integrated circuits, you
will not have a library of OTAs that you just plug in, and they
work.

I would be very suspicious of working anywhere that had an OTA

library I was supposed to use for integrated filter design. I’m not
saying it’s impossible that some company actually has an OTA
library, but I think it’s a bad strategy. First of all, if an OTA is generic
enough to be used “everywhere”, then the OTA is likely using too
much power, consumes too much area, and is too complex. And
the company runs the risk that the designer have not really checked
that the OTA works porperly in the filter because “Someone else
designed the OTA, I just used in my design”.

But, for now, to make our lifes simpler, we assume the OTA is ideal.
That makes the equations pretty, and we know what we should
get if the OTA actually was ideal.

[Link] Step 4: Do the algebra

The current flowing from 𝑉𝑜𝑢𝑡 to virtual ground is

𝐼 𝑜𝑢𝑡 = 𝐺 𝑓 𝑏 𝑉𝑜𝑢𝑡

The sum of currents into the virtual ground must be zero

𝐼 𝑖𝑛 + 𝐼 𝑜𝑢𝑡 = 0

Insert, and do the algebra

𝐺 𝑖𝑛 𝑉𝑖𝑛 + 𝐺 𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 = 0

⇒ −𝐺 𝑖𝑛 𝑉𝑖𝑛 = 𝐺 𝑜𝑢𝑡 𝑉𝑜𝑢𝑡

 10.4 Active-RC 129

𝑉𝑜𝑢𝑡 𝐺 𝑖𝑛
=−
𝑉𝑖𝑛 𝐺 𝑜𝑢𝑡

𝐺1 + 𝑠𝐶1
=−
𝐺2 + 𝑠𝐶2

−𝑠 𝐶𝐶21 − 𝐺1
𝐶2
= 𝐺2
𝑠+ 𝐶2

10.4.2 General purpose biquad

A general bi-quadratic active-RC filter is shown below. These kind

of general purpose filter sections are quite useful.

Imagine you wanted to make a filter, any filter. You’d decompose

into first and second order sections, and then you’d try and match
the transfer functions to the general equations.

Gy
G Gs
or
Ca
L
CB
Vi G
63
Vo

𝑘2 𝑠 2 + 𝑘1 𝑠 + 𝑘0
𝐻(𝑠) =
𝑠 2 + 𝜔𝑄0 𝑠 + 𝜔2𝑜

h i
𝐶1 2
𝐶𝐵 𝑠 + 𝐺2
𝐶𝐵 𝑠 + ( 𝐶𝐺𝐴1 𝐺𝐶𝐵3 )
𝐻(𝑠) = h i
𝐺5 𝐺3 𝐺4
𝑠2 + 𝐶𝐵 𝑠 + 𝐶𝐴 𝐶𝐵
130 10 Analog frontend and filters

10.5 The OTA is not ideal

VI
Vo

𝐴0
𝐻(𝑠) ≈ 𝑠
(1 + 𝑠𝐴 𝑜 𝑅𝐶)(1 + 𝑤 𝑡𝑎 )

where
𝐴0
is the gain of the amplifier, and

𝜔𝑡 𝑎

is the unity-gain frequency.

At frequencies above 𝐴01𝑅𝐶 and below 𝑤 𝑡 𝑎 the circuit above is a

good approximation of an ideal integrator.

See page 511 in CJM (chapter 5.8.1)

10.6 Example circuit

One place where both active-RC and Gm-C filters find a home are
continuous time sigma-delta modulators. More on SD later, for now,
just know that SD us a combination of high-gain, filtering, simple
ADCs and simple DACs to make high resolution analog-to-digital
converters.

One such an example is

A 56 mW Continuous-Time Quadrature Cascaded Sigma-Delta

Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

Below we see the actual circuit. It may look complex, and it is.

Not just “complex” as in complicated circuit, it’s also “complex”

as in “complex numbers”.
 10.7 My favorite OTA 131

We can see there are two paths “i” and “q”, for “in-phase” and
“quadrature-phase”. The fantasitc thing about complex ADCs is
that we can have a-symmetric frequency response around 0 Hz.

It will be tricky understanding circuits like this in the beginning,

but know that it is possible, and it does get easier to understand.

With a complex ADC like this, the first thing to understand is the
rough structure.

There are two paths, each path contains 2 ADCs connected in series
(Multi-stage Noise-Shaping or MASH). Understanding everything
at once does not make sence.

Start with “Vpi” and “Vmi”, make it into a single path (set Rfb1
and Rfb2 to infinite), ignore what happens after R3 and DAC2i.

Now we have a continuous time sigma delta with two stages. First
stage is a integrator (R1 and C1), and second stage is a filter (Cff1,
R2 and C2). The amplified and filtered signal is sampled by the
ADC1i and fed back to the input DAC1i.

It’s possible to show that if the gain from 𝑉(𝑉 𝑝𝑖, 𝑉 𝑝𝑚) to ADC1i
input is large, then 𝑌 1 𝑖 = 𝑉(𝑉 𝑝𝑖, 𝑉 𝑝𝑚) at low frequencies.

10.7 My favorite OTA

Over the years I’ve developed a love for the current mirror OTA. A
single stage, with load compensation, and an adaptable range of
DC gains.

Sometimes simple current mirrors are sufficient, sometimes cas-

coded, or even active cascodes are necessary.

Below is the differential current mirror OTA.

132 10 Analog frontend and filters

1 1

1 1
Von Vop
1
Vin Vip

Von Vop
Vin Vip

In a differential OTA we need to control the output common mode.

In order to control the common mode, we must sense the common
mode.

Below is a circuit I often use to sense the common mode. Ideally

the source followers would be native transistors, but those are not
always available.

The reference for the common mode can be from a bandgap, or in

the case below, VDD/2. Von Vop

VCREF
Von Vop
VCOUT

VCREF

VCOUT

Once we have both the sensed common mode, and the common
mode reference, we can use another OTA to control the common
mode.

The nice thing about the circuit below is that the common mode
feedback loop has the same dominant pole as the differential
loop.
 10.8 Want to learn more? 133

Von Vop
VCOUT VCREF

You can find the schematic for the OTA at

CNR_OTA_SKY130NM
DIFF OTA
VDD_1V8

BIAS x16[1:0]

VBP1
x18 x20 x11 x7

VBP2
x5[1:0]

CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0

CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0

VCONP VCOPP
VDD_1V8
x26 x28[3:0]
x17[1:0] x19 x21 x12 x8 x6[1:0]

VCP VCP VCP VCP

CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0
CNRATR_PCH_8C1F2 CNRATR_PCH_8C1F2 CNRATR_PCH_8C1F2
CNRATR_PCH_8C1F2 CNRATR_PCH_8C1F2 CNRATR_PCH_8C1F2
x27
VBP

CNRATR_PCH_8C4F0
CNRATR_NCH_8C1F2 CNRATR_NCH_8C1F2
VCP VON VSS VOP
VIN VIP
x22 VS x2

CNRATR_NCH_8C1F2 CNRATR_NCH_8C1F2 CNRATR_NCH_8C1F2 CNRATR_NCH_8C1F2

IBPSR VCN VCN

x14[1:0] x15 x4 x3[1:0]

VCN
VCONN VCOPN
CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_2C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0
CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0
VBN1 IBPSR VBN2

x24 x25 VSS x29[3:0] x30 x13[1:0] x10 VSS x23[3:0] x1 x2[1:0]

VCM VCM OTA

VDD_1V8
VDD_1V8
x51 x44 x49 x50
CNRATR_NCH_12C1F2 CNRATR_NCH_12C1F2 CNRATR_NCH_12C1F2 VBP
C=5.38e-14

C=5.38e-14
SUNTR_RPPO16

VSS VOP VSS VSS VON

CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0 CNRATR_PCH_8C2F0
x31 x33 x35
x40

VCBP
MF=1 c1

C1 c0

MF=1 c1

C2 c0

VCR VCONP VCOPP

5/5
cap_mim_m3_1

5/5
cap_mim_m3_1

VSC
x42 x43
SUNTR_RPPO16

VCREF VDD_1V8 VCREF

LPCO LPCI
CNRATR_PCH_8C1F2
CNRATR_PCH_8C1F2
x39

VCOP SUNTR_RPPO16 SUNTR_RPPO16 VCON

x9
SUNTR_RPPO16

x37 x38
VCONN VCOPN
VCBN1 VCBN2

CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0

IBPSR IBPSR IBPSR CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0
CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0 CNRATR_NCH_8C12F0

x32[3:0] x34[3:0] x36[3:0]

VSS x52 x45 VSS x46 x47 x48

Designer
Updated

10.8 Want to learn more?

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-

Shaping SAR ADC With Duty-Cycled Gm-C Integrator
Design Considerations for a Low-Power Control-Bounded A/D
Converter
A 56 mW Continuous-Time Quadrature Cascaded Sigma-Delta
Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band
Complex signal processing is not - complex
 Switched-Capacitor Circuits 11
Keywords: SC DAC, SC FUND, DT, Alias, Subsample, Z Do- 11.1 Active-RC . . . . . . 135
main, FIR, IIR, SC MDAC, SC INT, Switch, Non-Overlap, VBE 11.2 Gm-C . . . . . . . . . 137
SC, Nyquist 11.3 Switched capacitor . 137
11.3.1 An example SC circuit 140
11.4 Discrete-Time Sig-
nals . . . . . . . . . . 142
11.1 Active-RC 11.4.1 The mathematics . . 143
11.4.2 Python discrete time
A general purpose Active-RC bi-quadratic (two-quadratic equa- example . . . . . . . . 144
11.4.3 Aliasing, bandwidth
tions) filter is shown below
and sample rate
theory . . . . . . . . . 145
Gy 11.4.4 Z-transform . . . . . 147
G 11.4.5 Pole-Zero plots . . . 148
Gs 11.4.6 Z-domain . . . . . . . 148
or
Ca 11.4.7 First order filter . . . 149
L
CB
11.4.8 Finite-impulse re-
Vi G sponse(FIR) . . . . . 151
63 11.5 Switched-Capacitor 152
Vo
11.5.1 Switched capacitor
gain circuit . . . . . . 154
11.5.2 Switched capacitor
integrator . . . . . . . 155
If you want to spend a bit of time, then try and calculate the transfer 11.5.3 Noise . . . . . . . . . 156
11.5.4 Sub-circuits for
function below.
SC-circuits . . . . . . 158
11.5.5 Example . . . . . . . 161
h i
𝐶1 2
𝐶𝐵 𝑠 + 𝐺2
𝐶𝐵 𝑠 + ( 𝐶𝐺𝐴1 𝐺𝐶𝐵3 ) 11.6 Want to learn more? 162
𝐻(𝑠) = h i
𝐺5 𝐺3 𝐺4
𝑠2 + 𝐶𝐵 𝑠 + 𝐶𝐴 𝐶𝐵

Active resistor capacitor filters are made with OTAs (high output
impedance) or OPAMP (low output impedance). Active amplifiers
will consume current, and in Active-RC the amplifiers are always
on, so there is no opportunity to reduce the current consumption
by duty-cycling (turning on and off).

Both resistors and capacitors vary on an integrated circuit, and the

3-sigma variation can easily be 20 %.

The pole or zero frequency of an Active-RC filter is proportional to

the inverse of the product between R and C

𝐺 1
𝜔 𝑝|𝑧 ∝ =
𝐶 𝑅𝐶

As a result, the total variation of the pole or zero frequency is can

have a 3-sigma value of
136 11 Switched-Capacitor Circuits

q √
𝜎𝑅𝐶 = 𝜎𝑅2 + 𝜎𝐶2 = 0.022 + 0.022 = 0.028 = 28 %

On an IC we sometimes need to calibrate the R or C in production

to get an accurate RC time constant.

We cannot physically change an IC, every single one of the 100

million copies of an IC is from the same Mask set. That’s why ICs
are cheap. To make the Mask set is incredibility expensive (think 5
million dollars), but a copy made from the Mask set can cost one
dollar or less. To calibrate we need additional circuits.

Imagine we need a resistor of 1 kOhm. We could create that

by parallel connection of larger resistors, or series connection of
smaller resistors. Since we know the maximum variation is 0.02,
then we need to be able to calibrate away +- 20 Ohms. We could
have a 980 kOhm resistor, and then add ten 4 Ohm resistors in
series that we can short with a transistor switch.

But is a resolution of 4 Ohms accurate enough? What if we need a

precision of 0.1%? Then we would need to tune the resistor within
+-1 Ohm, so we might need 80 0.5 Ohm resistors.

But how large is the on-resistance of the transistor switch? Would

that also affect our precision?

But is the calibration step linear with addition of the transistors? If

we have a non-linear calibration step, then we cannot use gradient
decent calibration algorithms, nor can we use binary search.

Analog designers need to deal with an almost infinite series of

“But”.

The experienced designer will know when to stop, when is the

“But what if” not a problem anymore.

The most common error in analog integrated circuit design is a “I

did not imagine that my circuit could fail in this manner” type of
problem. Or, not following the line of “But”’s far enough.

But if we follow all the “But”’s we will never tapeout!

Active-RC filters are great for linearity, but if we need accurate

time constant, there are better alternatives.
 G Gs
or
Ca
GL CB
Vi G 11.2 Gm-C 137
63
Vo

11.2 Gm-C

Gmt Gul Gms Vout

ca c

20

Guy Gms
Vin
20

h i
𝐶𝑋
𝑠 2
𝐶 𝑋 +𝐶 𝐵 + 𝑠 𝐶𝑋𝐺+𝐶
𝑚5
𝐵
+ 𝐺𝑚2 𝐺𝑚4
𝐶 𝐴 (𝐶 𝑋 +𝐶 𝐵 )
𝐻(𝑠) = h i
𝑠 2 + 𝑠 𝐶𝑋𝐺+𝐶
𝑚2
𝐵
+ 𝐺𝑚1 𝐺𝑚2
𝐶 𝐴 (𝐶 𝑋 +𝐶 𝐵 )

The pole and zero frequency of a Gm-C filter is

𝐺𝑚
𝜔 𝑝|𝑧 ∝
𝐶

The transconductance accuracy depends on the circuit, and the

bias circuit, so we can’t give a general, applies for all circuits, sigma
number. Capacitors do have 3-sigma 20 % variation, usually.

Same as Active-RC, Gm-C need calibration to get accurate pole or

zero frequency.

11.3 Switched capacitor

The first time you encounter Switched Capacitor (SC) circuits, they
do require some brain training. So let’s start simple.

Consider the circuit below. Assume that the two transistors are
ideal (no-charge injection, no resistance).
138 11 Switched-Capacitor Circuits

Vi
zi 0

C
Q
Vgud

For SC circuits, we need to consider the charge on the capacitors,

and how they change with time.
The charge on the capacitor at the end ‗ of phase 2 is

𝑄 𝜙2$ = 𝐶1𝑉𝐺𝑁 𝐷 = 0

while at the end of phase 1

V0
𝑄 𝜙1$ = 𝐶1𝑉𝐼
Vi
The impedance, from Ohm’s law is
zi C
𝑍 𝐼 = (𝑉𝐼 − 𝑉𝐺𝑁 𝐷 )/𝐼𝐼

And from SI units units we can see current is

𝑄
𝐼𝐼 = = 𝑄 𝑓𝜙
9 a 𝑑𝑡

Charge cannot disappear, charge is conserved. As such, the charge

going out from the input must be equal to the difference of charge
at the end of phase 1 and phase 2.
Vi Vo
𝑉𝐼 − 𝑉𝐺𝑁 𝐷
𝑍𝐼 =
Zi 𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

‗I
C
use the $ to mark the end of the period. It comes from Regular Expressions.
 11.3 Switched capacitor 139

Vi
zi
Inserting for the charges, we can see that the impedance is
0
𝑉𝐼 1
𝑍𝐼 = =
(𝑉𝐼 𝐶 − 0) 𝑓𝜙 𝐶1 𝑓𝜙

C
A common confusion with SC circuits is to confuse the impedance
of a capacitor 𝑍 = 1/𝑠𝐶 with the impedance of a SC circuit
𝑍 = 1/ 𝑓 𝐶 . The impedance of a capacitor isQ
complex (varies with
Vgudwhile the SC circuit impedance is real (a
frequency and time),
resistance).

The main difference between the two is that the impedance of a

capacitor is continuous in time, while the SC circuit is a discrete
time circuit, and has a discrete time impedance.

The circuit below is drawn slightly differently, but the same equa-
tion applies.

V0
Vi
zi C

If we compute the impedance.

9 a
𝑉𝐼 − 𝑉𝑂
𝑍𝐼 =
𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

Vi Vo
𝑄 𝜙1$ = 𝐶1 (𝑉𝐼 − 𝑉𝑂 )
Zi C
𝑄 𝜙2$ = 0

𝑉𝐼 − 𝑉𝑂 1
𝑍𝐼 = =
(𝐶1 (𝑉𝐼 − 𝑉𝑂 )) 𝑓𝜙 𝐶1 𝑓𝜙

Which should not be surprising, as all I’ve done is to rotate the

circuit and call 𝑉𝐺𝑁 𝐷 = 𝑉0 .

Let’s try the circuit below.

 zi C

140 11 Switched-Capacitor Circuits

9 a

Vi Vo
Zi C

𝑉𝐼 − 𝑉𝑂
𝑍𝐼 =
𝑄 𝜙1$ − 𝑄 𝜙2$ 𝑓𝜙

𝑄 𝜙1$ = 𝐶1𝑉𝐼 )

𝑄 𝜙2$ = 𝐶1𝑉𝑂

Inserted into the impedance we get the same result.

𝑉𝐼 − 𝑉𝑂 1
𝑍𝐼 = =
(𝐶1𝑉𝐼 − 𝐶1𝑉𝑂 )) 𝑓𝜙 𝐶1 𝑓𝜙

The first time I saw the circuit above it was not obvious to me that
the impedance still was 𝑍 = 1/𝐶 𝑓 . It’s one of the cases where
mathematics is a useful tool. I could follow a set of rules (charge
conservation), and as long as I did the mathematics right, then
from the equations, I could see how it worked.

11.3.1 An example SC circuit

An example use of an SC circuit is

A pipelined 5-Msample/s 9-bit analog-to-digital converter

Shown in the figure below. You should think of the switched

capacitor circuit as similar to a an amplifier with constant gain. We
can use two resistors and an opamp to create a gain. Imagine we
create a circuit without the switches, and with a resistor of 𝑅 from
input to virtual ground, and 4𝑅 in the feedback. Our Active-R
would have a gain of 𝐴 = 4.
 11.3 Switched capacitor 141

The switches disconnect the OTA and capacitors for half the time,
but for the other half, at least for the latter parts of 𝜙2 the gain is
four.

The output is only correct for a finite, but periodic, time interval.
The circuit is discrete time. As long as all circuits afterwards also
have a discrete-time input, then it’s fine. An ADC can sample the
output from the amplifier at the right time, and never notice that
the output is shorted to a DC voltage in 𝜙1

We charge the capacitor 4𝐶 to the differential input voltage in 𝜙1

𝑄 1 = 4𝐶𝑉𝑖𝑛

Then we turn off 𝜙1 , which opens all switches. The charge on 4𝐶

will still be 𝑄 1 (except for higher order effects like charge injection
from switches).

After a short time (non-overlap), we turn on 𝜙2 , closing some of the

switches. The OTA will start to force its two inputs to be the same
voltage, and we short the left side of 4𝐶 . After some time we would
have the same voltage on the left side of 4𝐶 for the two capacitors,
and another voltage on the right side of the 4𝐶 capacitors. The two
capacitors must now have the same charge, so the difference in
charge, or differential charge must be zero.

Physics tell us that charge is conserved, so our differential charge

𝑄1 cannot vanish into thin air. The difference in electrons that
made 𝑄 1 must be somewhere in our circuit.

Assume the designer of the circuit has done a proper job, then the
𝑄1 charge will be found on the feedback capacitors.
142 11 Switched-Capacitor Circuits

We now have a 𝑄 1 charge on smaller capacitors, so the differential

output voltage must be

𝑄1 = 4𝐶𝑉𝑖𝑛 = 𝑄 2 = 𝐶𝑉𝑜𝑢𝑡

The gain is

𝑉𝑜𝑢𝑡
𝐴= =4
𝑉𝑖𝑛

Why would we go to all this trouble to get a gain of 4?

In general, we can sum up with the following equation.

𝐶1
𝜔 𝑝|𝑧 ∝
𝐶2

We can use these “switched capacitor resistors” to get pole or zero

frequency or gain proportional to a the relative size of capacitors,
which is a fantastic feature. Assume we make two identical ca-
pacitors in our layout. We won’t know the absolute size of the
capacitors on the integrated circuit, whether the 𝐶1 is 100 fF or 80
fF, but we can be certain that if 𝐶1 = 80 fF, then 𝐶2 = 80 fF to a
precision of around 0.1 %.

With switched capacitor amplifiers we can set an accurate gain,

and we can set an accurate pole and zero frequency (as long as we
have an accurate clock and a high DC gain OTA).

The switched capacitor circuits do have a drawback. They are

discrete time circuits. As such, we must treat them with caution,
and they will always need some analog filter before to avoid a
phenomena we call aliasing.

11.4 Discrete-Time Signals

An random, Gaussian, continuous time, continuous value, signal

has infinite information. The frequency can be anywhere from
zero to infinity, the value have infinite levels, and the time division
is infinitely small. We cannot store such a signal. We have to
quantize.

If we quantize time to 𝑇 = 1 ns, such that we only record the value

of the signal every 1 ns, what happens to all the other information?
The stuff that changes at 0.5 ns or 0.1 ns, or 1 ns.

We can always guess, but it helps to know, as in absolutely know,

what happens. That’s where mathematics come in. With mathe-
matics we can prove things, and know we’re correct.
 11.4 Discrete-Time Signals 143

11.4.1 The mathematics

Define
𝑥𝑐
as a continuous time, continuous value signal

Define (
1 if 𝑡 ≥ 0
ℓ (𝑡) =
0 if 𝑡 < 0

Define
𝑥 𝑐 (𝑛𝑇)
𝑥 𝑠𝑛 (𝑡) = [ℓ (𝑡 − 𝑛𝑇) − ℓ (𝑡 − 𝑛𝑇 − 𝜏)]
𝜏

where 𝑥 𝑠𝑛 (𝑡) is a function of the continuous time signal at the time

interval 𝑛𝑇 .

Define
∞
X
𝑥 𝑠 (𝑡) = 𝑥 𝑠𝑛 (𝑡)
𝑛=−∞

where 𝑥 𝑠 (𝑡) is the sampled, continuous time, signal.

Think of a sampled version of an analog signal as an infinite sum

of pulse trains where the area under the pulse train is equal to the
analog signal.

Why do this?

With a exact definition of a sampled signal in the time-domain it’s

sometimes possible to find the Laplace transform, and see how the
frequency spectrum looks.

If
∞
X
𝑥 𝑠 (𝑡) = 𝑥 𝑠𝑛 (𝑡)
𝑛=−∞

Then
1 1 − 𝑒 −𝑠𝜏
𝑋𝑠𝑛 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏 𝑠

And
∞
1 1 − 𝑒 −𝑠𝜏 X
𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏 𝑠 𝑛=−∞

Thus
∞
X
lim → 𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝜏→0 𝑛=−∞

Or
∞
𝑗 𝑘 2𝜋
 
1 X
𝑋𝑠 (𝑗𝜔) = 𝑋𝑐 𝑗𝜔 −
𝑇 𝑘=−∞ 𝑇
144 11 Switched-Capacitor Circuits

The spectrum of a sampled signal is an infinite sum of frequency

shifted spectra
or equivalently
When you sample a signal, then there will be copies of the input
spectrum at every
𝑛 𝑓𝑠

However, if you do an FFT of a sampled signal, then all those

infinite spectra will fold down between

0 → 𝑓𝑠 1 /2

or
− 𝑓𝑠 1 /2 → 𝑓𝑠 1 /2
for a complex FFT

11.4.2 Python discrete time example

If your signal processing skills are a bit thin, now might be a good
time to read up on FFT, Laplace transform and But what is the
Fourier Transform?
In python we can create a demo and see what happens when
we “sample” an “continuous time” signal. Hopefully it’s obvious
that it’s impossible to emulate a “continuous time” signal on a
digital computer. After all, it’s digital (ones and zeros), and it has
a clock!
We can, however, emulate to any precision we want.
The code below has four main sections. First is the time vector.
I use Numpy, which has a bunch of useful features for creating
ranges, and arrays.
Secondly, I create continuous time signal. The time vector can
be used in numpy functions, like [Link](), and I combine three
sinusoid plus some noise. The sampling vector is a repeating
pattern of 11001100, so our sample rate should be 1/2’th of the input
sample rate. FFT’s can be unwieldy beasts. I like to use coherent
sampling, however, with multiple signals and samplerates I did
not bother to figure out whether it was possible.
The alternative to coherent sampling is to apply a window function
before the FFT, that’s the reason for the Hanning window below.
[Link]
#- Create a time vector
N = 2**13
t = [Link](0,N,N)

#- Create the "continuous time" signal with multiple

#- "sinusoidal signals and some noise
f1 = 233/N
 11.4 Discrete-Time Signals 145

fd = 1/N*119
x_s = [Link](2*[Link]*f1*t) + 1/1024*[Link](N) + \
0.5*[Link](2*[Link]*(f1-fd)*t) + 0.5*[Link](2*[Link]*(f1+fd)*t)

#- Create the sampling vector, and the sampled signal

t_s_unit = [1,1,0,0,0,0,0,0]
t_s = [Link](t_s_unit,int(N/len(t_s_unit)))
x_sn = x_s*t_s

#- Convert to frequency domain with a hanning window to avoid FFT bin

#- energy spread
Hann = True
if(Hann):
w = [Link](N+1)
else:
w = [Link](N+1)
X_s = [Link]([Link]([Link](w[0:N],x_s)))
X_sn = [Link]([Link]([Link](w[0:N],x_sn)))

Try to play with the code, and see if you can understand what it
does.

Below are the plots. On the left side is the “continuous value,
continuous time” emulation, on the right side “discrete time,
continuous value”.

The top plots are the time domain, while the bottom plots is
frequency domain.

The FFT is complex, so that’s why there are six sinusoids bottom
left. The “0 Hz” would be at x-axis index 4096 (213 /2).

The spectral copies can be seen bottom right. How many spectral
copies, and the distance between them will depend on the sample
rate (length of t_s_unit). Try to play around with the code and
see what happens.

2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
Time Domain

0.0 0.0
0.5 0.5
1.0 1.0
1.5 1.5
2.0 2.0
0 2000 4000 6000 8000 0 2000 4000 6000 8000
60
60
40
40
20
Frequency Domain

20
0
0
20
20
40
40
60
60
80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
Continuous time, continuous value Discrete time, continuous value

11.4.3 Aliasing, bandwidth and sample rate theory

I want you to internalize that the spectral copies are real. They
are not some “mathematical construct” that we don’t have to deal
146 11 Switched-Capacitor Circuits

with.

They are what happens when we sample a signal into discrete

time. Imagine a signal with a band of interest as shown below in
Green. We sample at 𝑓𝑠 . The pink and red unwanted signals do not
As such
disappear x t should
after sampling, be band
even
limited before
though they are above the Nyquist
sampling
frequency ( 𝑓𝑠 /2). They fold around 𝑓𝑠 /2, and in may appear in-
band. That’s why it’s important to band limit analog signals before
they are sampled.

As such x t should
limited before
be bandBefore Saulius

N
sampling

P T it it
Es th thBefore
f
Saulius
ask o

8
P T
Es thi
NIii it it
th
After sampling

f ask o
I f
Es th th Issampling
After

8 I
components
Es
are
wanted signalth
Iii
With an anti-alias filter (yellow) we ensure that the unwanted
i low enough before
th Is
(green) is undisturbed.
Sampling
Beforesampling.
f As a result, our
Anti Alias

ot I Before Sampling
o LP o SH o
Es th it th f Anti Alias
After sampling
ot I o LP o SH o
Es th it th f
8 1 I f
Es th thAfterf sampling
8 1 I f
Es th th f

Assume that we we’re interested in the red signal. We could still

use a sample rate of 𝑓𝑠 . If we bandpass-filtered all but the red signal
the red signal would fold on sampling, as shown in the figure
below.

Remember that the Nyquist-Shannon states that a sufficient no-

loss condition is to sample signals with a sample rate of twice the
bandwidth of the signal.
 11.4 Discrete-Time Signals 147

Nyquist-Shannon has been extended for sparse signals, compressed

sensing, and non-uniform sampling to demonstrate that it’s suffi-
cient for the average sample rate to be twice the bandwidth. One
2009 paper Blind Multiband Signal Reconstruction: Compressed
Sensing for Analog Signal is a good place to start to delve into the
latest on signal reconstruction.

Before Sampling

AEs p th I I
th Is
M a app ask o

A
After sampling

o 1 I p p 1 I f
Es th th f

11.4.4 Z-transform

Someone got the idea that writing

∞
X
𝑋𝑠 (𝑠) = 𝑥 𝑐 (𝑛𝑇)𝑒 −𝑠𝑛𝑇
𝑛=−∞

was cumbersome, and wanted to find something better.

∞
X
𝑋𝑠 (𝑧) = 𝑥 𝑐 [𝑛]𝑧 −𝑛
𝑛=−∞

For discrete time signal processing we use Z-transform

If you’re unfamiliar with the Z-transform, read the book or search

[Link]

The nice thing with the Z-transform is that the exponent of the
z tell’s you how much delayed the sample 𝑥 𝑐 [𝑛] is. A block that
delays a signal by 1 sample could be described as 𝑥 𝑐 [𝑛]𝑧 −1 , and an
accumulator

𝑦[𝑛] = 𝑦[𝑛 − 1] + 𝑥[𝑛]

in the Z domain would be

𝑌(𝑧) = 𝑧 −1𝑌(𝑧) + 𝑋(𝑧)

148 11 Switched-Capacitor Circuits

With a Z-domain transfer function of

𝑌(𝑧) 1
=
𝑋(𝑧) 1 − 𝑧 −1

11.4.5 Pole-Zero plots

If you’re not comfortable with pole/zero plots, have a look at

What does the Laplace Transform really tell us

Think about the pole/zero plot as a surface your looking down

onto. At 𝑎 = 0 we have the steady state fourier transform. The “x”
shows the complex frequency where the fourier transform goes to
infinity.

Any real circuit will have complex conjugate, or real, poles/zeros.

A combination of two real circuits where one path is shifted 90
degrees in phase can have non-conjugate complex poles/zeros.

If the “x” is 𝑎 < 0, then any perturbation will eventually die out. If
the “x” is on the 𝑎 = 0 line, then we have a oscillator that will ring
forever. If the “x” is 𝑎 > 0 then the oscillation amplitude will grow
without bounds, although, only in Matlab. In any physical circuit
an oscillation cannot grow without bounds forever.

Growing without bounds is the same as “being unstable”.

jw s atjw

a
X

poles
11.4.6 Z-domain
440
O
0 Leros
Spectra repeat every ifs
2𝜋

As such, it does nottime

Discrete make sense to talk about a plane with a 𝑎 and
a 𝑗𝜔 . Rather we use the complex number 𝑧 = 𝑎 + 𝑗𝑏 .
spe
Z plane
b every
jw Zsa
 a 11.4 Discrete-Time Signals 149
X

As long as the poles (“x”) are within the unit circle, oscillations
will die out. If the poles are on the unit-circle, then we have an
oscillator. Outside the unit circle the oscillation will grow without
bounds, or in other words, be unstable.

poles 440
We can translate between Laplace-domain and Z-domain with the
Bi-linear transform

O
0 Leros ifs
𝑠=
𝑧−1
𝑧+1

Discrete time
Warning: First-order approximation [Link]
iki/Bilinear_transform

spectra
Z plane at
b every
jw Zsa
g
x
x

11.4.7 First order filter

Assume a first order filter given by the discrete time equation.

𝑦[𝑛 + 1] = 𝑏𝑥[𝑛] + 𝑎 𝑦[𝑛] ⇒ 𝑌𝑧 = 𝑏𝑋 + 𝑎𝑌

The “n” index and the “z” exponent can be chosen freely, which
sometimes can help the algebra.

𝑦[𝑛] = 𝑏𝑥[𝑛 − 1] + 𝑎 𝑦[𝑛 − 1] ⇒ 𝑌 = 𝑏𝑋 𝑧 −1 + 𝑎𝑌𝑧 −1

The transfer function can be computed as

𝑏
𝐻(𝑧) =
𝑧−𝑎

From the discrete time equation we can see that the impulse will
never die out. We’re adding the previous output to the current
150 11 Switched-Capacitor Circuits

input. That means the circuit has infinite memory. Accordingly,

filters of this type are known as. Infinite-impulse response (IIR)

(
𝑘 if 𝑛 < 1
ℎ[𝑛] =
𝑎 𝑛−1 𝑏 + 𝑎 𝑛 𝑘 if 𝑛 ≥ 1

Head’s up: Fig 13.12 in AIC is wrong

From the impulse response it can be seen that if 𝑎 > 1, then the
filter is unstable. Same if 𝑏 > 1. As long as |𝑎 + 𝑗𝑏| < 1 the filter
should be stable.

Firs
Hz
stable
unstable
ak
66 ha
It t a
xD
gy
Aza y

FIR
The first order filter can be implemented in python, and it’s really
not hard. See below. The 𝑥 𝑠 𝑛 vector is from the previous python
112
example.

Fitt impulse repose

There are smarter, and faster ways to do IIR filters (and FIR) in
Infinite
python, see [Link] e respon

H t Ea
E
we can see the sampled time domain and Hee
z
From the plot below
spectra on the left, and the filtered time domain and spectra on the
right.

[Link]
hlultakes
XE

4 Iya
 11.4 Discrete-Time Signals 151

1.00 1.00
0.75 0.75
0.50 0.50
0.25 0.25
Time Domain

0.00 0.00
0.25 0.25
0.50 0.50
0.75 0.75
1.00 1.00
1000 1050 1100 1150 1200 1250 1300 1350 1400 1000 1050 1100 1150 1200 1250 1300 1350 1400
60
40
40
20 20
Frequency Domain

0 0
20
20
40
40
60
60 80
0 2000 4000 6000 8000 0 2000 4000 6000 8000
Sampled IIR Filter

#- IIR filter
b = 0.3
a = 0.25
z = a + 1j*b
z_abs = [Link](z)
print("|z| = " + str(z_abs))
y = [Link](N)
y[0] = a
for i in range(1,N):
y[i] = b*x_sn[i-1] + y[i-1]

The IIR filter we implemented above is a low-pass filter, and the

filter partially rejects the copied spectra, as expected.

11.4.8 Finite-impulse response(FIR)

FIR filters are unconditionally stable, since the impulse response

will always die out. FIR filters are a linear sum of delayed inputs.

In my humble opinion, there is nothing wrong with an IIR. Yes,

the could become unstable, however, they can be designed safely.
I’m not sure there is a theological feud on IIR vs FIR, I suspect
there could be. Talk to someone that knows digital filters better
than me.

But be wary of rules like “IIR are always better than FIR” or visa
versa. Especially if statements are written in books. Remember that
the book was probably written a decade ago, and based on papers
two decades old, which were based on three decades old state of
the art. Our abilities to use computers for design has improved a
bit the last three decades.

2
1X
𝐻(𝑧) = 𝑧 −1
3 𝑖=0
 E
152 11 Switched-Capacitor Circuits
hl
XE

4
43
Iya
11.5 Switched-Capacitor

Below is an example of a switched-capacitor circuit during phase 1.

Think of the two phases as two different configurations of a circuit,
each with a specific purpose.

Cz
t
it q Ve
t c G

Q
This is the SC circuit during the sampling phase. Imagine that
Q
we somehow have stored a voltage 𝑉1 = ℓ on capacitor 𝐶1 (the
switches for that sampling or storing are not shown). The charge

Qz
on 𝐶1 is
Qz
𝑄 1𝜙1 $ = 𝐶1𝑉1

The 𝐶2 capacitor is shorted, as such, 𝑉2 = 0, which must mean that

the charge on 𝐶2 given by

𝑄 2 𝜙1 $ = 0

The voltage at the negative input of the OTA must be 0 V, as the

positive input is 0 V, and we assume the circuit has settled all
transients.

C E
 11.5 Switched-Capacitor 153

Imagine we (very carefully) open the circuit around 𝐶2 and close

the circuit from the negative side of 𝐶1 to the OTA negative input,
as shown below.

Cz
t t
Ve un

Q
It’s the OTA that ensures that the negative input is the same as the
positive input, but the OTA cannot be infinitely fast. At the same
time, the voltage across 𝐶1 cannot change instantaneously. Neither

Qz
can the voltage across 𝐶2 . As such, the voltage at the negative input
must immediately go to −𝑉1 (ignoring any parasitic capacitance at
the negative input).

The OTA does not like it’s inputs to be different, so it will start to
charge 𝐶2 to increase the voltage at the negative input to the OTA.
When the negative input reaches 0 V the OTA is happy again. At
that point the charge on 𝐶1 is

𝑄 1 𝜙2 $ = 0

A key point is, that even the voltages now have changed, there is
zero volt across 𝐶1 , and thus there cannot be any charge across 𝐶1

E E have disappeared. The negative

the charge that was there cannot
input of the OTA is a high impedance node, and cannot supply
charge. The charge must have gone somewhere, but where?

In process of changing the voltage at the negative input of the OTA

A we’ve Bchanged Athe voltage across 𝐶2 . TheB voltage change must
exactly match the charge that was across 𝐶1 , as such

𝑄2𝜙2 $ = 𝑄 1𝜙1 $ = 𝐶1𝑉1 = 𝐶2𝑉2

c
thus c

A
𝑉2 𝐶1
B
=
C
𝑉1 𝐶2
 a

154 11 Switched-Capacitor Circuits

if
a
ur
11.5.1 Switched capacitor gain circuit
Vocutis Vi n
Cg
Redrawing the previous circuit, and adding a few more switches
we can create aHswitched capacitor gain circuit.
VoZa switch to sampleHE
There is now
Evi g a across 𝐶1 during
the input voltage
phase 1 and reset 𝐶2 . During phase 2 we configure the circuit to
leverage the OTA to do the charge transfer from 𝐶1 to 𝐶2 .

a
Cz

Vien
VoEu

i n
The discrete time output from the circuit will be as shown below.
It’s only at the end of the second phase that the output signal is err
i HE
ga valid. As a result, it’s common to use the sampling phase of the
next circuit close to the end of phase 2.

For charge to be conserved the clocks for the switch phases must
never be high at the same time.

Cz

viii
VoEu

error
 11.5 Switched-Capacitor 155

The discrete time, Z-domain and transfer function is shown below.

The transfer function tells us that the circuit is equivalent to a
gain, and a delay of one clock cycle. The cool thing about switch
capacitor circuits is that the precision of the gain is set by the
relative size between two capacitors. In most technologies that
relative sizing can be better than 0.1 %.

Gain circuits like the one above find use in most Pipelined ADCs,
and are common, with some modifications, in Sigma-Delta
ADCs.

𝐶1
𝑉𝑜 [𝑛 + 1] = 𝑉𝑖 [𝑛]
𝐶2

𝐶1
𝑉𝑜 𝑧 = 𝑉𝑖
𝐶2

𝑉𝑜 𝐶 1 −1
= 𝐻(𝑧) = 𝑧
𝑉𝑖 𝐶2

11.5.2 Switched capacitor integrator

Removing one switch we can change the function of the switched

capacitor gain circuit. If we don’t reset 𝐶2 then we accumulate the
input charge every cycle.

Vos
C Cz
Cz

Vith

Nt
a
VoEu
G
N
no

arrow
The output now will grow without bounds, so integrators are most
often used in filter circuits, or sigma-delta ADCs where there is
feedback to control the voltage swing at the output of the OTA.

VoEn VoEn I Vicu r

Et
 156 11 Switched-Capacitor Circuits

Vos
C Cz
Cz

Nt
a
VoEu
N
no

arrow
Make sure you read and understand the equations below, it’s good
to realize that discrete time equations, Z-domain and transfer
functions in the Z-domain are actually easy.

𝐶1
𝑉𝑜 [𝑛] = 𝑉𝑜 [𝑛 − 1] + 𝑉𝑖 [𝑛 − 1]
𝐶2
En I Vicu r
Et 𝑉𝑜 − 𝑧 −1𝑉𝑜 =
𝐶 1 −1
𝐶2
𝑧 𝑉𝑖

zaVi
É Maybe one confusing thing is that multiple transfer functions can
mean the same thing, as below.

EEE E 𝐻(𝑧) =
𝐶 1 𝑧 −1
𝐶2 1 − 𝑧 − 1
=
𝐶1 1
𝐶2 𝑧 − 1

11.5.3 Noise

Capacitors don’t make noise, but switched-capacitor circuits do

have noise. The noise comes from the thermal, flicker, burst noise
in the switches and OTA’s. Both phases of the switched capacitor
circuit contribute noise. As such, the output noise of a SC circuit is
usually

2 𝑘𝑇
𝑉𝑛2 >
𝐶
 11.5 Switched-Capacitor 157

I find that sometimes it’s useful with a repeat of mathematics, and

since we’re talking about noise.

The mean, or average of a signal is defined as

Mean ∫ +𝑇/2
1
𝑥(𝑡) = lim 𝑥(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

Define

Mean Square
∫ +𝑇/2
1
𝑥 2 (𝑡) = lim 𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

How much a signal varies can be estimated from the Variance

2
𝜎2 = 𝑥 2 (𝑡) − 𝑥(𝑡)

where
𝜎
is the standard deviation. If mean is removed, or is zero, then

𝜎2 = 𝑥 2 (𝑡)

Assume two random processes,

𝑥 1 (𝑡)

and
𝑥 2 (𝑡)
with mean of zero (or removed).

𝑥 𝑡𝑜𝑡 (𝑡) = 𝑥 1 (𝑡) + 𝑥 2 (𝑡)

𝑥 𝑡𝑜𝑡
2
(𝑡) = 𝑥 12 (𝑡) + 𝑥 22 (𝑡) + 2𝑥 1 (𝑡)𝑥 2 (𝑡)

Variance (assuming mean of zero)

∫ +𝑇/2
1
𝜎𝑡𝑜𝑡
2
= lim 𝑥 𝑡𝑜𝑡
2
(𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

∫ +𝑇/2
1
𝜎𝑡𝑜𝑡
2
= 𝜎12 + 𝜎22 + lim 2 𝑥 1 (𝑡)𝑥 2 (𝑡)𝑑𝑡
𝑇→∞ 𝑇 −𝑇/2

Assuming uncorrelated processes (covariance is zero), then

𝜎𝑡𝑜𝑡
2
= 𝜎12 + 𝜎22
158 11 Switched-Capacitor Circuits

In other words, if two noises are uncorrelated, then we can sum

the variances. If the noise sources are correlated, for example,
noise comes from the same transistor, but takes two different paths
through the circuit, then we cannot sum the variances. We must
also add the co-variance.

11.5.4 Sub-circuits for SC-circuits

Switched-capacitor circuits are so common that it’s good to delve

a bit deeper, and understand the variants of the components that
make up SC circuits.

[Link] OTA

At the heart of the SC circuit we usually find an OTA. Maybe a

current mirror, folded cascode, recycling cascode, or my favorite: a
fully differential current mirror OTA with cascoded, gain boosted,
output stage using a parallel common mode feedback.

Not all SC circuits use OTAs, there are also comparator based SC
circuits.

Below is a fully-differential two-stage OTA that will work with

most SC circuits. The notation “24F1F25” means “the width is 24
F” and “length is 1.25 F”, where “F” is the minimum gate length
in that technology.

As bias circuit to make the voltages the below will work

 11.5 Switched-Capacitor 159

Cz Cz
t t
it q Ve un

t c G

Q Q
[Link] Switches
Qz Qz
If your gut reaction is “switches, that’s easy”, then you’re very
wrong. Switches can be incredibly complicated. All switches will be
made of transistors, but usually we don’t have enough headroom
to use a single NMOS or PMOS. We may need a transmission
gate

C E E

A B A B A B

c
c

A B
C

The challenge with transmission gates is that when the voltage at

the input is in the middle between VDD and ground then both
PMOS and NMOS, although they are on , they might not be that
on. Especially in nano-scale CMOS with a 0.8 V supply and 0.5 V
threshold voltage. The resistance mid-rail might be too large.
For switched-capacitor circuits we must settle the voltages to the
required accuracy. In general

𝑡 > − log(error)𝜏

For example, for a 10-bit ADC we need 𝑡 > − log(1/1024)𝜏 = 6.9𝜏.

This means we need to wait at least 6.9 time constants for the voltage
to settle to 10-bit accuracy in the switched capacitor circuit.
Assume the capacitors are large due to noise, then the switches
must be low resistance for a reasonable time constant. Larger
160 11 Switched-Capacitor Circuits

switches have smaller resistance, however, they also have more

charge in the inversion layer, which leads to charge injection when
the switches are turned of. Accordingly, larger switches are not
always the solution.

Sometimes it may be sufficient to switch the bulks, as shown on

the left below. But more often that one would like, we have to
implement bootstrapped switches as shown on the right.

c e
c e
A c e B c
A B

The switch I used in my JSSC SAR is a fully differential boostrapped

switch with cross coupled dummy transistors. The JSSC SAR I’ve
also ported to GF130NM, as i shown below. The switch is at the
bottom. i
Be
wulffern/sun_sar9b_sky130nm
Ap

E e
C E
g
An Bu

looks like the one below.

 C

11.5 Switched-Capacitor 161

i
i
Be

Ap

E e
C E
g
An Bu

[Link] Non-overlapping clocks

The non-overlap generator is standard. Use the one shown below.

Make sure you simulate that the non-overlap is sufficient in all
corners.

on

if
a
ur

cutis
Vo Vi n
Cg
11.5.5 Example
H
VoZ
Evi HE
ga
In the circuit below there is an example of a switched capacitor cir-
cuit used to increase the Δ𝑉𝐷 across the resistor. We can accurately
set the gain, and thus the equation for the differential output will
be Cz

Vien viii
Vo𝑘𝑇
Eu
𝑉𝑂 (𝑧) = 10 ln(𝑁)𝑧 −1
𝑞

error
162 11 Switched-Capacitor Circuits

n
I 2

TCalooff

11.6 Want to learn more?

Blind Multiband Signal Reconstruction: Compressed Sensing for

Analog Signal
Comparator-based switched-capacitor pipelined analog-to-digital
converter with comparator preset, and comparator delay compen-
sation
A Compiled 9-bit 20-MS/s 3.5-fJ/[Link] SAR ADC in 28-nm
FDSOI for Bluetooth Low Energy Receivers
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching
Procedure
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-
Sigma Modulator
Ring Amplifiers for Switched Capacitor Circuits
A Switched-Capacitor RF Power Amplifier
Design of Active N-Path Filters
 Oversampling and Sigma-Delta
ADCs 12
Keywords: Quantization, OSR, NEG FB, STF, NTF, SAR, First Order, 12.1 ADC state-of-the-art 163
12.1.1 What makes a state-
SC SD, CT SD, INCR, FOM
of-the-art ADC . . . 164
12.1.2 High resolution FOM 170
12.2 Quantization . . . . 171
12.1 ADC state-of-the-art 12.2.1 Signal to Quantiza-
tion noise ratio . . . 175
12.2.2 Understanding
The performance of an analog-to-digital converter is determined quantization . . . . . 175
by the effective number of bits (ENOB), the power consumption, 12.2.3 Why you should care
about quantization
and the maximum bandwidth. The effective number of bits contain
noise . . . . . . . . . 177
information on the linearity of the ADC. The power consumption
12.3 Oversampling . . . 178
shows how efficient the ADC is. The maximum bandwidth limits
12.3.1 Noise power . . . . . 178
what signals we can sample and reconstruct in digital domain. 12.3.2 Signal power . . . . 179
12.3.3 Signal to Noise Ratio 179
Many years ago, Robert Walden did a study of ADCs, one of the 12.3.4 Signal to Quantiza-
plot’s is shown below. tion Noise Ratio . . . 179
12.3.5 Python oversample 180
1999, R. Walden: Analog-to-digital converter survey and analysis
12.4 Noise Shaping . . . 181
12.4.1 The magic of feed-
There are obvious trends, the faster an ADC is, the less precise
back . . . . . . . . . . 181
the ADC is ( lower SNDR). There are also fundamental limits, 12.4.2 Sigma-delta principle 182
Heisenberg tells us that a 20-bit 10 GS/s ADC is impossible, 12.4.3 Signal transfer func-
according to Walden. tion . . . . . . . . . . 184
12.4.4 Noise transfer func-
tion . . . . . . . . . . 184
12.4.5 Combined transfer
function . . . . . . . 185
12.5 First-Order Noise-
Shaping . . . . . . . 185
12.5.1 SQNR and ENOB . . 187
12.6 Examples . . . . . . 187
12.6.1 Python noise-shaping 187
12.6.2 The wonderful world
of SD modulators . . 189
12.7 Want to learn more? 193
The uncertainty principle states that the precision we can determine
position and the momentum of a particle is

ℏ
𝜎𝑥 𝜎𝑝 ≥
2
. There is a similar relation of energy and time, given by

ℎ
Δ𝐸Δ𝑡 >
2𝜋
where Δ𝐸 is the difference in energy, and Δ𝑡 is the difference in
time.
164 12 Oversampling and Sigma-Delta ADCs

You should take these limits with a grain of salt. The plot assumes
50 Ohm and 1 V full-scale. As a result, the “Heisenberg” line that
appears to be unbreakable certainly is breakable. Just change the
voltage to 100 V, and the number of bits can be much higher. Always
check the assumptions.

A more recent survey of ADCs comes from Boris Murmann. He

still maintains a list of the best ADCs from ISSCC and VLSI
Symposium.

B. Murmann, ADC Performance Survey 1997-2023

A common figure of merit for low-to-medium resolution ADCs is

the Walden figure of merit, defined as

𝑃
𝐹𝑂 𝑀𝑊 =
2𝐵 𝑓 𝑠

Below 10 fJ/[Link] is good.

Below 1 fJ/[Link] is extreme.

In the plot below you can see the ISSCC and VLSI ADCs.

2.E+03
FOMW,hf [fJ/conv-step]

2.E+02

2.E+01

ISSCC 2021

2.E+00 VLSI 2021

ISSCC 1997-2020
VLSI 1997-2020
Envelope
2.E-01
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

fsnyq [Hz]

12.1.1 What makes a state-of-the-art ADC

People from NTNU have made some of the worlds best ADCs

If you ever want to make an ADC, and you want to publish

the measurements, then you must be better than most. A good
algorithm for state-of-the-art ADC design is to first pick a sample
rate with low number of data (blank spaces in the plot above), then
read the papers in the vicinity of the blank space to understand
the application, then set a target FOM which is best in world, then
try and find a ADC architecture that can achieve that FOM.

That’s pretty much the algorithm I, and others, have followed to

make state-of-the-art ADCs. A few of the NTNU ADCs are:
 12.1 ADC state-of-the-art 165

[1] A Compiled 9-bit 20-MS/s 3.5-fJ/[Link] SAR ADC in 28-nm

FDSOI for Bluetooth Low Energy Receivers

[2] A 68 dB SNDR Compiled Noise-Shaping SAR ADC With

On-Chip CDAC Calibration

In order to publish, there must be something new. Preferably a

new circuit. Below is the circuit from [1]. It’s a standard successive-
approximation register (SAR) analog-to-digital converter.

The differential input signal is sampled on a capacitor array where

the bottom plate is connected to either VSS or VREF. Once the volt-
age is sampled, the comparator will decide whether the differential
voltage is larger, or smaller than 0. Depending on the decision, the
MSB capacitors (left-most) in figure will switch the bottom plate in
order to effectively subtract a voltage equivalent to half the VREF
voltage.

The comparator makes another decision, and 1/4’th the VREF

voltage is subtracted or added. Then 1/8’th and so on implementing
a binary search to find the input voltage.

The “bit-cycling” (binary-search) loop is self-timed, as such, when

the comparator has made a decision, the next cycle starts.

In (b) we can see the enable flip-flop for the next stage. The CK
bar is the sample clock, as such, A is high during sampling. The
output of the comparator (P and N) is low.

As soon as the comparator makes a decision, P or N goes high, A

will be pulled low, if EI is enabled.

In (c) we can see that the bottom plate of the capacitors 𝐷𝑃 0 , 𝐷𝑃 1 ,

𝐷𝑁 0 , and 𝐷𝑁 1 , are controlled by P and N.

In (d) we can see that the bottom plate of the capacitors also used to
set the comparator clock low again (CO), resetting the comparator,
and pulling P and N low, which in (b) enables the next SAR logic
state.
166 12 Oversampling and Sigma-Delta ADCs

How fast the 𝐷𝑋𝑋 settle depend on the size of the capacitors, as
such, the comparator clock will be slow for the MSB, and very fast
for the LSB. This was my main circuit contribution in the paper.
I think it’s quite clever, because both the VDD and the capacitor
corner will change the settling time. It’s important that the capacitor
values fully settle before the next comparator decision, and as a
result of the circuit in (c,d) the delay is automatically adjusted.

For further details see the paper.

CK D8 CK D7 CK D6 CK D5 CK D4 CK D3 CK D2 CK D1 CK D0
DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N

CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO
LOGIC[8] LOGIC[7] LOGIC[6] LOGIC[5] LOGIC[4] LOGIC[3] LOGIC[2] LOGIC[1] LOGIC[0] CK
CK EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO
DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 X1

X2
CK
CK CM P
VP +
P

VN −
Bootstrapped 28 · CU N IT 27 · CU N IT 26 · CU N IT 25 · CU N IT 24 · CU N IT 23 · CU N IT 22 · CU N IT 21 · CU N IT 20 · CU N IT N
NMOS switches
(a)

VDD VDD VDD VDD

VREF VREF VDD VDD

CK MP 0 MP 3 CK MP 4 CK MP 5

MP 6 MP 7
DP 0 DN 0 DN 1 DP 1
N MP 2 EI MN 6 EI MN 9
A

EI MN 0 P MP 1 MN 5 MN 8
EO B

P MN 1 N MN 2 MN 3 P MN 4 N MN 7 CK MN 10
CI CO

(b) (c) (d)

For state-of-the-art ADC papers it’s not sufficient with the idea,
and simulation. There must be proof that it actually works. No-one
will really believe that the ADC works until there is measurements
of an actual taped out IC.

Below you can see the layout of the IC I made for the paper. Notice
that there are 9 ADCs. I had many ideas that I wanted to try out,
and I was not sure what would actually be state of the art. As a
result, I taped out multiple ADCS.
 12.1 ADC state-of-the-art 167

The two ADCs that I ended up using in the paper is shown below.
The one on the left was made with 180 nm IO transistors, while
the one on the right was made with core-transistors. Notice that
the layout of the two is quite similar.

Comparator

Logic
106µm

CDAC

80µm

Switch

39µm
40µm
(a) (b)

Once taped out, and many months of waiting, a few months of

measurement in the lab, I had some results that would be good
enough to qualify for the best conference, and luckily the best
journal.
0 0
Amplitude = -0.42 dBFS, ENOB = 7.82 b Amplitude = -0.60 dBFS, ENOB = 7.42 b
Magnitude [dBFS]

Magnitude [dBFS]

−20 −20
SNDR = 48.84 dB, SFDR = 63.11 dBc SNDR = 46.43 dB, SFDR = 61.72 dBc
Samples = 16384 Samples = 16384
−40 −40
VDD = 0.69 V, IDD = 23 µA VDD = 0.47 V, IDD = 2 µA
FoM = 3.51 fJ/[Link] FoM = 2.73 fJ/[Link]
−60 −60

−80 −80
0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz] Frequency [MHz]
(a) (b)
8.5 70
Peak ENOB @ fs/2 [bit]

Magnitude [dB]

8
60
SNDR [dB]
7.5 SFDR [dBc]
80 kS/s
2 MS/s 50
7 20 MS/s
80 MS/s
6.5 40
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 1 2 3 4 5 6 7 8 9 10
VDD [V] Input frequency [MHz]
(c) (d)

Comparing my ADCs to others, we can see that the FOM is similar

to others. Based on the FOM it might not be clear why the paper
was considered state-of-the-art.

The circuit technique mentioned above would not have been

enough to qualify. The big thing was the “Compiled” line. Com-
pared to the other “Compiled” mine was 300 times better, and on
par with other state-of-the-art.
168 12 Oversampling and Sigma-Delta ADCs

Weaver [5] Harpe [9] Patil [10] Liu [11] This work
Technology (nm) 90 90 28 FDSOI 28 28 FDSOI
Fsample (MS/s) 21 2 No sampling 100 2 20
Core area (mm2 ) 0.18 0.047 0.0032 0.0047 0.00312
SNDR (dB) 34.61 57.79 40 64.43 46.43 48.84
SFDR (dBc) 40.81 72.33 30 75.42 61.72 63.11
ENOB (bits) 5.45 6.7 - 9.4 6.35 10.41 7.42 7.82
Supply (V) 0.7 0.7 0.65 0.9 0.47 0.69
Pwr (µW) 1110 1.64 -3.56 24 350 0.94 15.87
Compiled Yes No No No Yes
FoM (fJ/[Link]) 838 2.8 - 6.6 3.7 2.6 2.7 3.5

The big thing was how I made the ADC. I started with a definition
of a transistor, as shown below

Vertical Grid
D
Horizontal Grid
G B
S

OD CO PO M1

And then wrote a compiler (in Perl, later C++ ciccreator) to compile
a object definition file, a SPICE netlist and a technology rule file
into the full ADC layout.

In (a) you can see one of the cells in the SAR logic, (b) is the spice
file, and (c) is the definition of the routing. The numbers to the
right in the routing creates the paths shown in (d).

.SUBCKT SAREMX1_CV P N EI EO CK_N AVDD AVSS

MN0 N3 EI A AVSS NCHDL
MN1 N3 P AVSS AVSS NCHDL
MN2 AVSS N N3 AVSS NCHDL
MN3 EO A AVSS AVSS NCHDL
MP0 AVDD CK_N A AVSS PCHDL
MP1 N2 P EO AVSS PCHDL
MP2 N1 N N2 AVSS PCHDL
MP3 AVDD A N1 AVSS PCHDL
.ENDS
(b)
{ "name": "SAREMX1_CV",
"class" : "Layout::LayoutDigitalCell",
"addConnectivityRoutes": [
["M1","N1|N2","||",""], 1
["M1","N3","-|",""], 2
["M1","EO","--|-","onTopR"] 3
],
"addDirectedRoutes" : [
["PO","P","MN1:G-MP1:G"], 4
["PO","N","MN2:G-MP2:G"], 5
["PO","A","MN3:G-MP3:G"], 6
["M1","A","MN0:S-MP0:S"], 7
["M1","A","MP0:S-|--MP3:G"] 8
]
}
(a) } (c)

MN3 6 MP3

1 8

MN2 5 MP2
N
1
2

MN1 4 MP1
P 3
EO

MN0 MP0
EI 7 CK

V SS V DD

OD CO PO M1 M2 M3 M4
(d)

The implementation is the SPICE netlist, and the object definition

file (JSON) and the rule file.
 12.1 ADC state-of-the-art 169

What I really like is the fact that the compilation could generate
GDSII or SKILL, or these days, Xschem schematics and Magic
layout.

Architecture Implementation Compilation

Hand Analysis SPICE netlist

Schematic Initial netlist Object definition file Compiler

Testbench Technology file

Simulation GDSII SKILL

Physical Simulation Initial Loading

Compiled cells

verification Visual
visual SKILL into
Testbench LVS DRC inspection Cadence
inspection (seconds) Virtuoso
(minutes)
Parasitic netlist

Compiled schematics and layout (OpenAccess database)

The cool thing with a compiled ADC is that it’s easy to port
between technologies. Since the original ADC, I’ve ported the ADC
to multiple closed PDKs (22 nm FDSOI, 22 nm, 28 nm, 55 nm, 65
nm and 130nm). In the summer of 2022 I made an open source
port to skywater 130nm.

SUN_SAR9B_SKY130NM

One of my Ph.D students built on-top on my work, and made a

noise-shaped compiled SAR ADC, shown below, more on that
later.
 November 4 – 6, 2019
The Parisian Macao, Macao SAR, China
170 12 Oversampling and Sigma-Delta ADCs

|NTF|0→BW -27.8 dB
Fig. 3. Die photo and ADC layout.
+ (g − 2)z −1 + z −2
a1 − 2) + (a2 − a1 + 1)z −2 12.1.2 High resolution FOM
Corrected on-chip: Corrected offline:
M SNDR 68.2 dB Uncal. Cal.
SNR 68.3 dB SNDR 64.3 dB 67.7
For high-resolution ADCs, it’s more common to use the Schreier dB
SFDR 84.6 dB SFDR
figure of merit, which can also be found in 69.6 dB 83.9 dB
0 0
and noise SNDR
transfer
68.2function.
dB
Cal. Uncal.
Power [dBFS]

Power [dBFS]

SNR 68.3 dB -25 -25

SFDR 84.6 dB Cal. (ISSCC & VLSI
B. Murmann, ADC Performance Survey 1997-2022
-50 Symposium) -50
e-effective solution because -75 -75
uffered or resampled. -100
The Walden figure of merit assumes -100 that thermal noise does not
10k 100k the power
constrain 1M 5M 20M
consumption of 10k
the ADC,100kwhich1M 5M 20M
is usually
NT RESULTS Frequency
true for [Hz]
low-to-medium resolution ADCs. To Frequency
keep the[Hz]Walden
n 28 nm FDSOI, and Fig. 3 FOM you(a) can double the power for a one-bit increase
(b) in ENOB.
If the ADC is limited by thermal noise, however, then you must
mensions. The entire region Fig. 4. Measured
quadrupleresults and power (reduce
the capacitance spectrums:
𝑘𝑇/𝐶(a):noise
On-chip correction,
power) for each (b):
rom a netlist, rule file, and offline correction. The power spectra have 212 bins from DC to f /2.
1-bit ENOB increase. Accordingly, the power must also go up s four
ut compiler presented in [7]. times.
pectrum with on-chip code TABLE I
module cannot be disabled, C OMPARISON
For higherTO ADC -the
PRIOR STATE
resolution - THE - ART
OF power NOISE - SHAPING
consumption SAR S .
is set by thermal
noise, and the Schreier FOM allows for a 4x power consumption
pectrums from another ADC increase for each
[1] added[2]
bit. [3] [4] This work
eight measured chips, mean
CDAC correction None DWA Off-chip cal None On-chip cal
SFDR are 65.6 dB/67.3 dB,
NTF type 1z, 2p 1z, 2p 2z opt  𝑓𝑠1z,
/2 1p
 2z opt, 2p
y. The ADC is compared OSR 4𝐹𝑂 𝑀𝑆13.2
= 𝑆𝑁 𝐷𝑅 + 810 log
𝑃4 4
o the best of the authors’
Technology (nm) 65 28 40 14 28
5.2 fJ/[Link] is currently Area (mm )
2 0.03 0.0049 0.024 0.0021 0.0234
Above 180 dB is extreme
aping SAR. Supply (V) 1.2 1 1.1 0.9 0.8
Bandwidth (MHz) 11 5 0.625 40 5
CES
SNDR (dB) 62.0 79.7 79.0 66.6 68.2
MS/s 11-MHz-Bandwidth 62-dB SFDR (dB) 72.5 92.6 89.0 77.4 84.6
EE Journal of Solid-State Circuits, Power (µW) 806 .0 460.0 84.0 1250.0 108.7
 12.2 Quantization 171

190
ISSCC 2021
VLSI 2021
180 ISSCC 1997-2020
VLSI 1997-2020
Envelope
170
FOMS,hf [dB]

160

150

140

130

120
1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12
fsnyq [Hz]

12.2 Quantization

Sampling turns continuous time into discrete time. Quantization

turns continuous value into discrete value. Any complete ADC is
always a combination of sampling and quantization.

In our mathematical drawings of quantization we often define 𝑦[𝑛]

as the output, the quantized signal, and 𝑥[𝑛] as the discrete time,
continuous value input, and we add some “noise”, or “quantization

D
X
noise” 𝑒[𝑛], where 𝑥[𝑛] = 𝑦[𝑛] − 𝑒[𝑛].

een
XED o En
g
Maybe you’ve even heard the phrase “Quantization noise is white”
or “Quantization noise is a random Gaussian process”?

I’m here to tell you that you’ve been lied to. Quantization noise is
not white, nor is it a Gaussian process. Those that have lied to you
may say “yes, sure, but for high number of bits it can be considered
white noise”. I would say that’s similar to saying “when you look at
the earth from the moon, the surface looks pretty smooth without
bumps, so let’s say the earth is smooth with no mountains”.

I would claim that it’s an unnecessary simplification. It’s obvious

to most that the earth would appear smooth from really far away,
 172 12 Oversampling and Sigma-Delta ADCs

but they would not be surprised by Mount Everest, since they

know it’s not smooth. An Alien that has been told that the earth is
smooth, would be surprised to see Mount Everest.

But if Quantization noise is not white, what is it?

The figure below shows the input signal x and the quantized signal
y.

a
XD y
een
gEn
XED o
It

É
To see the quantization noise, first take a look at the sample and
held version of 𝑥 in green in the figure below. The difference
between the green ( 𝑥 at time n) and the red ( 𝑦 ) would be our
quantization noise 𝑒
d a
y
x
The quantization noise is contained between + 12 Least Significant
Bit (LSB) and − 12 LSB.

This noise does not look random to me, but I can’t see what it is,
É
and I’m pretty sure I would not be able to work it out either.

I 1 i t t t t t t t
 É
12.2 Quantization 173

d a
y
x

I 1 i t t t t t t t
EBI
een
Else I
TIFFT
Luckily, there are people in this world that love mathematics,
and that can delve into the details and figure out what 𝑒[𝑛] is. A
guy called Blachman wrote a paper back in 1985 on quantization
noise.

See The intermodulation and distortion due to quantization of

sinusoids for details

In short, quantization noise is defined as

∞
X
𝑒 𝑛 (𝑡) = 𝐴 𝑝 sin 𝑝𝜔𝑡
𝑝=1

where p is the harmonic index, and

( P∞
𝛿 𝑝1 𝐴 + 𝑚=1 𝑚𝜋 𝐽𝑝 (2𝑚𝜋𝐴)
2
, 𝑝 = odd
𝐴𝑝 =
0 , 𝑝 = even

(
1 ,𝑝 =1
𝛿 𝑝1
0 ,𝑝 ≠1

and
𝐽𝑝 (𝑥)
is a Bessel function of the first kind, A is the amplitude of the input
signal.

If we approximate the amplitude of the input signal as

174 12 Oversampling and Sigma-Delta ADCs

2𝑛 − 1
𝐴= ≈ 2𝑛−1
2

where n is the number of bits, we can rewrite as

∞
X
𝑒 𝑛 (𝑡) = 𝐴 𝑝 sin 𝑝𝜔𝑡
𝑝=1

∞
2
𝐴 𝑝 = 𝛿 𝑝 1 2𝑛−1 + 𝐽𝑝 (2𝑚𝜋2𝑛−1 ), 𝑝 = 𝑜𝑑𝑑
X
𝑚=1 𝑚𝜋

Obvious, right?

I must admit, it’s not obvious to me. But I do understand the

implications. The quantization noise is an infinite sum of input
signal odd harmonics, where the amplitude of the harmonics is
determined by a sum of a Bessel function.

A Bessel function of the first kind looks like this

So I would expect the amplitude to show signs of oscillatory

behavior for the harmonics. That’s the important thing to remember.
The quantization noise is odd harmonics of the input signal

The mean value is zero

𝑒 𝑛 (𝑡) = 0

and variance (mean square, since mean is zero), or noise power,

can be approximated as

Δ2
𝑒 𝑛 (𝑡)2 =
12
 12.2 Quantization 175

12.2.1 Signal to Quantization noise ratio

Assume we wanted to figure out the resolution, or effective number

of bits for an ADC limited by quantization noise. A power ratio, like
signal-to-quantization noise ratio (SQNR) is one way to represent
resolution.

Take the signal power, and divide by the noise power

𝐴2 /2 6 𝐴2
   
𝑆𝑄𝑁 𝑅 = 10 log 2 = 10 log
Δ /12 Δ2

2𝐴
Δ=
2𝐵

6 𝐴2
 
𝑆𝑄𝑁 𝑅 = 10 log = 20𝐵 log 2 + 10 log 6/4
4𝐴2 /2𝐵

𝑆𝑄𝑁 𝑅 ≈ 6.02𝐵 + 1.76

You may have seen the last equation before, now you know where
it comes from.

12.2.2 Understanding quantization

Below I’ve tried to visualize the quantization process [Link].

The left most plot is a sinusoid signal and random Gaussian noise.
The signal is not a continuous time signal, since that’s not possible
on a digital computer, but it’s an approximation.

The plots are FFTs of a sinusoidal signal combined with noise.

These are complex FFTs, so they show both negative and positive
frequencies. The x-axis is the FFT bin (not the frequency). Notice
that there are two spikes, which should not be surprising, since a
sinusoidal signal is a combination of two frequencies.

𝑒 𝑖𝑥 − 𝑒 −𝑖𝑥
𝑠𝑖𝑛(𝑥) =
2𝑖

The second plot from the left is after sampling, notice that the noise
level increases. The increase in the noise level should be due to
noise folding, and reduced number of points in the FFT, but I have
not confirmed (maybe you could confirm?).

The right plot is after quantization, where I’ve used the function
below.
176 12 Oversampling and Sigma-Delta ADCs

def adc(x,bits):
levels = 2**bits
y = [Link](x*levels)/levels
return y

I really need you to internalize a few things from the right most
plot. Really think through what I’m about to say.

Can you see how the noise (what is not the two spikes) is not white?
White noise would be flat in the frequency domain, but the noise
is not flat.
0 0 0
1-bit
f =127
20 20 20

40 40 40

60 60 60
Frequency Domain

80 80 80

100 100 100

120 120 120

140 140 140

160 160 160

4000 2000 0 2000 4000 1000 500 0 500 1000 1000 500 0 500 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value

If you run the python script you can zoom in and check the highest
spikes. The fundamental is at 127, so odd harmonics would be
381, 635, 889, and from the function of the quantization noise we
would expect those to be the highest harmonics (at least when we
look at the Bessel function), however, we can see that it’s close, but
that bin 396 is the highest. Is the math’s wrong?

No, the math is correct. Never bet against mathematics. If you

change the python script to reduce the frequency, fdivide=2**9,
and increase number of points, N=2**16, as in the plot below, you’ll
see it’s the 11’th harmonic that is highest.

All the other spikes are the odd harmonics above the sample rate
that fold. The infinite sum of harmonics will fold, some in-phase,
some out of phase, depending on the sign of the Bessel function.
 12.2 Quantization 177

From the function for the amplitude of the quantization noise for
harmonic indices higher than 𝑝 = 1

∞
2
𝐽𝑝 (2𝑚𝜋2𝑛−1 ), p=odd
X
𝐴𝑝 =
𝑚=1 𝑚𝜋

we can see that the input to the Bessel function increases faster
for a higher number of bits 𝑛 . As such, from the Bessel function
figure above, I would expect that the sum of the Bessel function
is a lower value. Accordingly, the quantization noise reduces at
higher number of bits.

A consequence is that the quantization noise becomes more and

more uniform, as can be seen from the plot of a 10-bit quantizer be-
low. That’s why people say “Quantization noise is white”, because
for a high number of bits, it looks white in the FFT.
0 0 0
10-bit
f =127
20 20 20

40 40 40

60 60 60
Frequency Domain

80 80 80

100 100 100

120 120 120

140 140 140

160 160 160

4000 2000 0 2000 4000 1000 500 0 500 1000 1000 500 0 500 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value

12.2.3 Why you should care about quantization noise

So why should you care whether the quantization noise looks white,
or actually is white? A class of ADCs called oversampling and
sigma-delta modulators rely on the assumption that quantization
noise is white. In other words, the cross-correlation between noise
components at different time points is zero. As such the noise power
sums as a sum of variance, and we can increase the signal-to-noise
ratio.

We know that assumption to be wrong though, quantization noise

is not white. For noise components at harmonic frequencies the
cross-correlation will be high. As such, when we design oversam-
pling or sigma-delta based ADC we will include some form of
dithering (making quantization noise whiter). For example, before
the actual quantizer we inject noise, or we make sure that the
thermal noise is high enough to dither the quantizer.

Everybody that thinks that quantization noise is white will design

non-functioning (or sub-optimal) oversampling and sigma-delta
178 12 Oversampling and Sigma-Delta ADCs

ADCs. That’s why you should care about the details around
quantization noise.

12.3 Oversampling

Assume a signal 𝑥[𝑛] = 𝑎[𝑛] + 𝑏[𝑛] where 𝑎 is a sampled sinusoid

and 𝑏 is a random process where cross-correlation is zero for any
time except for 𝑛 = 0. Assume that we sum two (or more) equally
spaced signal components, for example

𝑦 = 𝑥[𝑛] + 𝑥[𝑛 + 1]

What would the signal to noise ratio be for 𝑦 ?

12.3.1 Noise power

Our mathematician friends have looked at this, and as long the

noise signal 𝑏 is random then the noise power for the oversampled
signal 𝑏 𝑜𝑠𝑟 = 𝑏[𝑛] + 𝑏[𝑛 + 1] will be

𝑏 2𝑜𝑠𝑟 = 𝑂𝑆𝑅 × 𝑏 2

where OSR is the oversampling ratio. If we sum two time points

the 𝑂𝑆𝑅 = 2, if we sum 4 time points the 𝑂𝑆𝑅 = 4 and so on.

For fun, let’s go through the mathematics

Define 𝑏 1 = 𝑏[𝑛] and 𝑏 2 = 𝑏[𝑛 + 1] and compute the noise power

(𝑏1 + 𝑏2 )2 = 𝑏12 + 2𝑏 1 𝑏2 + 𝑏22

Let’s replace the mean with the actual function

𝑁
1 X
𝑏12 + 2𝑏1 𝑏2 + 𝑏22


𝑁 𝑛=0

which can be split up into

𝑁 𝑁 𝑁
1 X 1 X 1 X
𝑏12 + 2𝑏 1 𝑏 2 + 𝑏2
𝑁 𝑛=0 𝑁 𝑛=0 𝑁 𝑛=0 2

we’ve defined the cross-correlation to be zero, as such

𝑁 𝑁
1 X 1 X
(𝑏1 + 𝑏2 )2 = 𝑏12 + 𝑏 2 = 𝑏12 + 𝑏22
𝑁 𝑛=0 𝑁 𝑛=0 2
 12.3 Oversampling 179

but the noise power of each of the 𝑏 ’s must be the same as 𝑏 , so

(𝑏 1 + 𝑏2 )2 = 2𝑏 2

12.3.2 Signal power

For the signal 𝑎 we need to calculate the increase in signal power

as OSR increases.

I like to think about it like this. 𝑎 is low frequency, as such, samples

𝑛 and 𝑛 + 1 is pretty much the same value. If the sinusoid has
an amplitude of 1, then the amplitude would be 2 if we sum two
samples. As such, the amplitude must increase with the OSR.

The signal power of a sinusoid is 𝐴2 /2, accordingly, the signal

power of an oversampled signal must be (𝑂𝑆𝑅 × 𝐴)2 /2.

12.3.3 Signal to Noise Ratio

Take the signal power to the noise power

(𝑂𝑆𝑅 × 𝐴)2 /2 𝐴2 /2
= 𝑂𝑆𝑅 ×
𝑂𝑆𝑅 × 𝑏 2 𝑏2

We can see that the signal to noise ratio increases with increased
oversampling ratio, as long as the cross-correlation of the noise
is zero

12.3.4 Signal to Quantization Noise Ratio

The in-band quantization noise for a oversampling ratio (OSR)

Δ2
𝑒 𝑛 (𝑡)2 =
12𝑂𝑆𝑅

And the improvement in SQNR can be calculated as

6 𝐴2 6 𝐴2
   
𝑆𝑄𝑁 𝑅 = 10 log 2 = 10 log + 10 log(𝑂𝑆𝑅)
Δ /𝑂𝑆𝑅 Δ2

𝑆𝑄𝑁 𝑅 ≈ 6.02𝐵 + 1.76 + 10 log(𝑂𝑆𝑅)

For an OSR of 2 and 4 the SQNR improves by

10 log(2) ≈ 3 𝑑𝐵
180 12 Oversampling and Sigma-Delta ADCs

and for OSR=4

10 log(4) ≈ 6 𝑑𝐵

which is roughly equivalent to a 0.5-bit per doubling of OSR

12.3.5 Python oversample

There are probably more elegant (and faster) ways of implementing

oversampling in python, but I like to write the dumbest code I can,
simply because dumb code is easy to understand.

Below you can see an example of oversampling. The oversample

function takes in a vector and the OSR. For each index it sums OSR
future values.

def oversample(x,OSR):
N = len(x)
y = [Link](N)

for n in range(0,N):
for k in range(0,OSR):
m = n+k
if (m < N):
y[n] += x[m]
return y

Below we can see the plot for OSR=2, the right most plot is the
oversampled version.

The noise has all frequencies, and it’s the high frequency compo-
nents that start to cancel each other. An average filter (sometimes
called a sinc filter due to the shape in the frequency domain) will
have zeros at ± 𝑓 𝑠/2 where the noise power tends towards zero.
0 0 0 0
10-bit OSR=2
20 20 20 20

40 40 40 40

60 60 60 60
Frequency Domain

80 80 80 80

100 100 100 100

120 120 120 120

140 140 140 140

160 160 160 160

0 2000 4000 6000 8000 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Oversampled

The low frequency components will add, and we can notice how
the noise power increases close to the zero frequency (middle of
the x-axis).

For an OSR of 4 we can notice how the noise floor has 4 zero’s.
 12.4 Noise Shaping 181

0 0 0 0
10-bit OSR=4
20 20 20 20

40 40 40 40

60 60 60 60
Frequency Domain

80 80 80 80

100 100 100 100

120 120 120 120

140 140 140 140

160 160 160 160

0 2000 4000 6000 8000 0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Oversampled

The code for the plots is [Link]. I would encourage you to play a
bit with the code, and make sure you understand oversampling.

12.4 Noise Shaping

Look at the OSR=4 plot above. The OSR=4 does decrease the noise
compared to the discrete time discrete value plot, however, the
noise level of the discrete time continuous value is much lower.

What if we could do something, add some circuitry, before the

quantization such that the quantization noise was reduced?

That’s what noise shaping is all about. Adding circuits such that we
can “shape” the quantization noise. We can’t make the quantization
noise disappear, or indeed reduce the total noise power of the
quantization noise, but we can reduce the quantization noise power
for a certain frequency band.

But what circuitry can we add?

12.4.1 The magic of feedback

A generalized feedback system is shown below, it could be a

regulator, a unity-gain buffer, or something else.

The output 𝑉𝑜 is subtracted from the input 𝑉𝑖 , and the error 𝑉𝑥 is

shaped by a filter 𝐻(𝑠).

If we make 𝐻(𝑠) infinite, then 𝑉𝑜 = 𝑉𝑖 . If you’ve never seen such a

circuit, you might ask “Why would we do this? Could we not just
use 𝑉𝑖 directly?”. There are many reasons for using a circuit like
this, let me explain one instance.

Imagine we have a VDD of 1.8 V, and we want to make a 0.9 V

voltage for a CPU. The CPU can consume up to 10 mA. One way to
make a divide by two circuit is with two equal resistors connected
between VDD and ground. We don’t want the resistive divider to
consume a large current, so let’s choose 1 MOhm resistors. The
182 12 Oversampling and Sigma-Delta ADCs

current in the resistor divider would then be about 1 𝜇A. We can’t

connect the CPU directly to the resistor divider, the CPU can draw
10 mA. As such, we need a copy of the voltage at the mid-point of
the resistor divider that can drive 10 mA.

Do you see now why a circuit like the one below is useful? If not,
you should really come talk to me so I can help you understand.

VI VX Hcs V0

Ux Vo VxHCS
VI Vo
VI Vo E
YE
12.4.2 Sigma-delta principle

VI V
Let’s modify the feedback circuit into the one below. I’ve added
Hes ADCand theDAC
𝐷𝑜 is now the
VI
an ADC and a DAC to the feedback loop,
VX Hcs
output we’re interested V0
in. The equation for the loop would be
Do
HCS𝑜 ) − 𝑉𝑖 )]
Ux Vo Vx
𝐷𝑜 = 𝑎𝑑𝑐 [𝐻(𝑠) (𝑑𝑎𝑐(𝐷
VI Vo
But how can we now calculate the transfer function 𝐷
Vo E 𝑉 ? Both 𝑎𝑑𝑐
𝑜

VI YE
𝑖
and 𝑑𝑎𝑐 could be non-linear functions, so we can’t disentangle the
equation. Let’s make assumptions.

VI V
Hes ADC DAC

Do

[Link] The DAC assumption

Assumption 1: the 𝑑𝑎𝑐 is linear, such that 𝑉𝑜 = 𝑑𝑎𝑐(𝐷𝑜 ) = 𝐴𝐷𝑜 + 𝐵,

where 𝐴 and 𝐵 are scalar values.
 12.4 Noise Shaping 183

The DAC must be linear, otherwise our noise-shaping ADC will

not work.

One way to force linearity is to use a 1-bit DAC, which has only
two points, so should be linear. For example

𝑉𝑜 = 𝐴 × 𝐷𝑜

, where 𝐷𝑜 ∈ (0 , 1). Even a 1-bit DAC could be non-linear if 𝐴 is

time-variant, so 𝑉𝑜 [𝑛] = 𝐴(𝑡) × 𝐷𝑜 [𝑛], this could happen if the
reference voltage for the DAC changed with time.

I’ve made a couple noise shaping ADCs, and in the first one I
made I screwed up the DAC. It turned out that the DAC current
had a signal dependent component which lead to a non-linear
behavior.

[Link] The ADC assumption

Assumption 2: the 𝑎𝑑𝑐 can be modeled as a linear function 𝐷𝑜 =

𝑎𝑑𝑐(𝑥) = 𝑥 + 𝑒 , where e is white noise source

We’ve talked about this, the 𝑒 is not white, especially for low-bit
ADCs, so we usually have to add noise. Sometimes it’s sufficient
with thermal noise, but often it’s necessary to add a random, or
pseudo-random noise source at the input of the ADC.

[Link] The modified equation

With the assumptions we can change the equation into

𝐷𝑜 = 𝑎𝑑𝑐 [𝐻(𝑠) (𝑉𝑖 − 𝑑𝑎𝑐(𝐷𝑜 ))] = 𝐻(𝑠) (𝑉𝑖 − 𝐴𝐷𝑜 ) + 𝑒

In noise-shaping texts it’s common to write the above equation

as

𝑦 = 𝐻(𝑠)(𝑢 − 𝑦) + 𝑒

or in the sample domain

𝑦[𝑛] = 𝑒[𝑛] + ℎ ∗ (𝑢[𝑛] − 𝑦[𝑛])

which could be drawn in a signal flow graph as below.

 tf tf
184 12 Oversampling and Sigma-Delta ADCs

to yen
I o Ha

in the Z-domain the equation would turn into

een
YET 𝑌(𝑧) HA
= 𝐸(𝑧) + 𝐻(𝑧) [𝑈(𝑧) −UET
𝑌(𝑧)] YET
YG ECz HE UG 4
The whole point of this exercise was to somehow shape the z quan-
tization noise, and we’re almost at the point, but to show how it
works we need to look at the transfer function for the signal 𝑈 and
ECHO for the noise 𝐸 .
y HU HY
t function
12.4.3 Signal transfer
STF
Assume U and E are uncorrelated, and E is zero

𝑌 = 𝐻𝑈 − 𝐻𝑌

𝑌 𝐻 1
𝑆𝑇𝐹 = = =
𝑈 1+𝐻 1 + 𝐻1

Imagine what will happen if H is infinite. Then the signal transfer

function (STF) is 1, and the output 𝑌 is equal to our input 𝑈 . That’s
exactly what we wanted from the feedback circuit.

12.4.4 Noise transfer function

Assume U is zero

1
𝑌 = 𝐸 + 𝐻𝑌 → 𝑁𝑇𝐹 =
1+𝐻

Imagine again what happens when H is infinite. In this case the

noise-transfer function becomes zero. In other words, there is no
added noise.
 12.5 First-Order Noise-Shaping 185

12.4.5 Combined transfer function

In the combined transfer function below, if we make 𝐻(𝑧) infinite,

then 𝑌 = 𝑈 and there is no added quantization noise. I don’t
know how to make 𝐻(𝑧) infinite everywhere, so we have to choose
at what frequencies it’s “infinite”.

𝑌(𝑧) = 𝑆𝑇𝐹(𝑧)𝑈(𝑧) + 𝑁𝑇𝐹(𝑧)𝐸(𝑧)

There are a large set of different 𝐻(𝑧) and I’m sure engineers
will invent new ones. We usually classify the filters based on the
number of zeros in the NTF, for example, first-order (one zero),
second order (two zeros) etc. There are books written about sigma-
delta modulators, and I would encourage you to read those to
get a deeper understanding. I would start with Delta-Sigma Data
Converters: Theory, Design, and Simulation.

12.5 First-Order Noise-Shaping

We want an infinite 𝐻(𝑧). One way to get an infinite function is an

accumulator, for example

𝑦[𝑛 + 1] = 𝑥[𝑛] + 𝑦[𝑛]

or in the Z-domain

𝑧𝑌 = 𝑋 + 𝑌 → 𝑌(𝑧 − 1) = 𝑋

which has the transfer function

1
𝐻(𝑧) =
𝑧−1

The signal transfer function is

1/(𝑧 − 1) 1
𝑆𝑇𝐹 = = = 𝑧 −1
1 + 1/(𝑧 − 1) 𝑧

and the noise transfer function

1 𝑧−1
𝑁 𝐹𝑇 = = = 1 − 𝑧 −1
1 + 1/(𝑧 − 1) 𝑧

In order calculate the Signal to Quantization Noise Ratio we need to

have an expression for how the NTF above filters the quantization
noise.
186 12 Oversampling and Sigma-Delta ADCs

In the book they replace the 𝑧 with the continuous time variable

𝑠=𝑗𝜔
𝑧 = 𝑒 𝑠𝑇 → 𝑒 𝑗𝜔𝑇 = 𝑒 𝑗 2𝜋 𝑓 / 𝑓𝑠

inserted into the NTF we get the function below.

𝑁𝑇𝐹( 𝑓 ) = 1 − 𝑒 −𝑗 2𝜋 𝑓 / 𝑓𝑠

𝑒 𝑗𝜋 𝑓 / 𝑓𝑠 − 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
= × 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
2𝑗

𝜋𝑓
= sin × 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠
𝑓𝑠

The arithmetic magic is really to extract the 2 𝑗 × 𝑒 −𝑗𝜋 𝑓 / 𝑓𝑠 from the

first expression such that the initial part can be translated into a
sinusoid.

When we take the absolute value to figure out how the NTF changes
with frequency the complex parts disappears (equal to 1)

𝜋𝑓
 
|𝑁 𝐹𝑇( 𝑓 )| = 2 sin
𝑓𝑠

The signal power for a sinusoid is

𝑃𝑠 = 𝐴2 /2

The in-band noise power for the shaped quantization noise is

𝑓0 2
Δ2 1 𝜋𝑓
∫  
𝑃𝑛 = 2 sin 𝑑𝑡
− 𝑓0 12 𝑓𝑠 𝑓𝑠

and with a bunch of tedious maths, we can get to the conclusion

..
.

𝑆𝑄𝑁 𝑅 = 6.02𝐵 + 1.76 − 5.17 + 30 log(𝑂𝑆𝑅)

If we compare to pure oversampling, where the SQNR improves by

10 log(𝑂𝑆𝑅), a first order sigma-delta improves by 30 log(𝑂𝑆𝑅).
That’s a significant improvement.
 12.6 Examples 187

12.5.1 SQNR and ENOB

Below is the signal-to-quantization noise ratio’s for Nyquist up to

second order sigma-delta.

𝑆𝑄𝑁 𝑅 𝑛 𝑦𝑞𝑢𝑖𝑠𝑡 ≈ 6.02𝐵 + 1.76

𝑆𝑄𝑁 𝑅 𝑜𝑣𝑒𝑟𝑠 𝑎𝑚𝑝𝑙𝑒 ≈ 6.02𝐵 + 1.76 + 10 log(𝑂𝑆𝑅)

𝑆𝑄𝑁 𝑅ΣΔ1 ≈ 6.02𝐵 + 1.76 − 5.17 + 30 log(𝑂𝑆𝑅)

𝑆𝑄𝑁 𝑅ΣΔ2 ≈ 6.02𝐵 + 1.76 − 12.9 + 50 log(𝑂𝑆𝑅)

We could compute an effective number of bits, as shown below.

𝐸𝑁 𝑂𝐵 = (𝑆𝑄𝑁 𝑅 − 1.76)/6.02

The table below shows the effective number of bits for oversam-
pling, and sigma-delta modulators. For a 1-bit quantizer, pure
oversampling does not make sense at all. For first-order and second-
order sigma delta modulators, and a OSR of 1024 we can get high
resolution ADCs.

Assume 1-bit quantizer, what would be the maximum ENOB?

OSR Oversampling First-Order Second Order

4 2 3.1 3.9
64 4 9.1 13.9
1024 6 15.1 23.9

12.6 Examples

12.6.1 Python noise-shaping

I want to demystify noise-shaping modulators. I think one way to

do that is to show some code. You can find the code at sd_1st.py

Below we can see an excerpt. Again pretty stupid code, and I’m
sure it’s possible to make a faster version (for loops in python are
notoriously slow).

For each sample in the input vector 𝑢 I compute the input to the
quantizer 𝑥 , which is the sum of the previous input to the quantizer
and the difference between the current input and the previous
output 𝑦 𝑠𝑑 .
188 12 Oversampling and Sigma-Delta ADCs

The quantizer generates the next 𝑦 𝑠𝑑 and I have the option to add
dither.

# u is discrete time, continuous value input

M = len(u)
y_sd = [Link](M)
x = [Link](M)
for n in range(1,M):
x[n] = x[n-1] + (u[n]-y_sd[n-1])
y_sd[n] = [Link](x[n]*2**bits
+ dither*[Link]()/4)/2**bits

The right-most plot is the one with noise-shaping. We can observe

that the noise seems to tend towards zero at zero frequency, as we
would expect. The accumulator above would have an infinite gain
at infinite time (it’s the sum of all previous values), as such, the
NTF goes towards zero at 0 frequency.

If we look at the noise we can also see the non-white quantization

noise, which will degrade our performance. I hope by now, you’ve
grown tired of me harping on the point that quantization noise is
not white
0 0 0 0
1-bit
20 20 20 20

40 40 40 40

60 60 60 60
Frequency Domain

80 80 80 80

100 100 100 100

120 120 120 120

140 140 140 140

dither=0
160 160 160 160
0 1000 2000 3000 4000 0 250 500 750 1000 0 250 500 750 1000 0 250 500 750 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Noise-shaped

In the figure below I’ve turned on dither, and we can see how the
noise looks “better”, which I know is not a qualitative statement,
but ask anyone that’s done 1-bit quantizers. It’s important to have
enough random noise.

0 0 0 0
1-bit
20 20 20 20

40 40 40 40

60 60 60 60
Frequency Domain

80 80 80 80

100 100 100 100

120 120 120 120

140 140 140 140

dither=1
160 160 160 160
0 1000 2000 3000 4000 0 250 500 750 1000 0 250 500 750 1000 0 250 500 750 1000
Continuous time, continuous value Discrete time, continuous value Discrete time, Discrete value Noise-shaped
 12.6 Examples 189

In papers it’s common to use a logarithmic x-axis for the power

spectral density, as shown below. In the plot I only show the
positive frequencies of the FFT. From the shape of the quantization
noise we can also see the first order behavior.

20

40
Magnitude [dB20]

60

80

100

120
10 3 10 2 10 1
Normalized frequency

12.6.2 The wonderful world of SD modulators

[Link] Open-Loop Sigma-Delta

On my Ph.D I did some work on

Resonators in Open-Loop Sigma-Delta Modulators

which was a pure theoretical work. The idea was to use modulo
integrators (local control of integrator output swing) in front of
large latency multi-bit quantizers to achieve a high SNR.

The plot below shows a fifth order NFT where there are two
complex conjugate zeros, and a zero at zero frequency. With a
higher order filter one can use a lower OSR, and still achieve high
ENOB.
190 12 Oversampling and Sigma-Delta ADCs

A=−3dB ENOB=13.8 SNDR=84.9dB M=32768

0

−20

−40

−60

Magnitude [dB]
−80

−100

−120

−140

−160
Output
Bandwidth
−180
−4 −3 −2 −1
10 10 10 10
Normalized Frequency, fs = 1

[Link] Noise Shaped SAR

One of my Ph.d students made a

A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip

CDAC Calibration

In a SAR ADC, once the bit-cycling is complete, the analog value

on the capacitors is the actual quantization error. That error can
be fed to a loop filter, H(z), and amplified in the next conversion,
accordingly a combination of SAR and noise-shaping.

In the paper the SD modulator was also used to calibrate the

non-linearity in the CDAC, as the MSB capacitor won’t be exactly
N times larger than the smallest capacitor.

The loop filter was a switched cap loop filter, and we can see the
NTF below. The first OTA made use of chopping to reduce the
offset.
 12.6 Examples 191

[Link] Control-Bounded ADCs

One of my current Ph.D students is working an even more advanced

type of sigma-delta ADC. Actually, it’s more a super-set of SD
ADCs called control-bounded ADCs.

Design Considerations for a Low-Power Control-Bounded A/D

Converter

A block diagram of a Leapfrog ADC version of a control-bounded

ADC is shown below.

Here we’re walking into advanced maths territory, but to simplify,

I think it’s correct to say that a control-bounded ADC seeks to
control the local analog state, 𝑥 𝑛 (𝑡) such that no voltage is saturated.
The digital control signals 𝑠 𝑛 (𝑡) are used to infer the state of the
input 𝑢(𝑡)
High-Level using a form of Bayesian Statistics.
Architecture

↵2 ↵3 ··· ↵N

1
x1 (t) 2
x2 (t) 3
x3 (t) N
xN (t)
u(t) + s+⇢1 + s+⇢2 + s+⇢3
··· + s+⇢N
1 fclk 2 fclk 3 fclk N fclk
< < < <
s1 (t) s2 (t) s3 (t) sN (t)

Figure 3.1: The general structure of the Leapfrog ADC

by A0i = /⇢i . i
Below we can see a power spectral density plot of the ADC, and
The Leapfrog
we can observe ADChow di↵ers
thefrom the Chain-of-integrators
quantization by the addi-
noise is shaped. I think it’s
tional feedback paths between neighboring states. The feedback from xi
atothird
xi 1 is achieved through ↵i , feeding a portion of xi back to the input complex
order NTF with a zero at zero frequency and a of
conjugate
integrator (ipole
1). at 8 MHzish.
Each integrator is stabilized by a local digital control,
which is represented by a clocked comparator in figure 3.1. The output of
comparator i is the control-contribution si (t) which is scaled by a factor
i before entering the integrator input.

3.2 Parametrization
192 12 Oversampling and Sigma-Delta ADCs

0
û(t)
20 NTF
40

60

PSD [dB]
80

100

120

140

160
105 106 107
Frequency [Hz]

Figure 5.6: Estimated PSD of û(t) plotted together with corresponding

theoretical NTF. Obtained from an ideal circuit simulation of a 4th order
Leapfrog
12.6.2.4ADC with LNA
Complex driven, passive integrator and floating-gate
Sigma-Delta
voltage summation

There are cool sigma-delta modulators with crazy configurations

and that may look like an exercise in “Let’s make something
complex”, however, most of them have a reasonable application.
One example is the one below for radio recievers

A 56 mW Continuous-Time Quadrature Cascaded Sigma-Delta

Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

58

[Link] My first Sigma-Delta

The first sigma-delta modulator I made in “real-life” was similar

to the one shown below.
 12.7 Want to learn more? 193

The input voltage is translated into a current, and the current is

integrated on capacitor 𝐶 . The 𝑅 𝑜 𝑓 𝑓 𝑠𝑒𝑡 is to change the mid-level
voltage, while 𝑅 𝑟𝑒 𝑓 is the 1-bit feedback DAC. The comparator is
the quantizer. When the clock strikes the comparator compares the
𝑉𝑜 and 𝑉𝑟𝑒 𝑓 /2 and outputs a 1-bit digital output 𝐷
The complete ADC is operated in a “incremental mode”, which is
a fancy way of saying

Reset your sigma-delta modulator, run the sigma delta

modulator for a fixed number of cycles (i.e 1024), and
count the number of ones at 𝐷

The effect of an “incremental mode” is to combine the modulator

and a output filter so the ADC appears to be a slow Nyquist
ADC.
For more information, ask me, or see the patent at Analogue-to-
digital converter

12.7 Want to learn more?

The design of sigma-delta modulation analog-to-digital convert-

ers
Delta-sigma modulation in fractional-N frequency synthesis
A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy
of ± 0.15 C (3sigma) From -55 Cto 125 C
A 20-mW 640-MHz CMOS Continuous-Time Sigma-Delta ADC
With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit
ENOB
A Micro-Power Two-Step Incremental Analog-to-Digital Con-
verter
 Voltage regulation 13
13.1 Voltage source . . . 195
13.1.1 Core voltage . . . . . 199
13.1.2 IO voltage . . . . . . 199
Keywords: Battery, Vreg, LDOP, LDON, Flipped voltage follower, 13.1.3 Supply planning . . 200
Buck, Boost, Load, Line, PSRR, MAX C, Quiescent, Settling, Effi- 13.2 Linear Regulators . 201
ciency, PWM, PFM 13.2.1 PMOS pass-fet . . . 201
13.2.2 NMOS pass-fet . . . 202
13.2.3 Control of pass-fet . 203
13.3 Switched Regulators 204
13.3.1 Principles of
switched regula-
tors . . . . . . . . . . 205
13.3.2 Inductive DC/DC
converter details . . 208
13.1 Voltage source 13.3.3 Pulse width modula-
tion (PWM) . . . . . 209
13.3.4 Real world use . . . 212
13.3.5 Pulsed Frequency
Mode (PFM) . . . . . 212
13.4 Want to learn more? 214
Most, if not all, integrated circuits need a supply and ground to
13.4.1 Linear regulators . . 215
work. 13.4.2 DC-DC converters . 215

Assume a system is AC powered. Then there will be switched

regulator to turn wall AC into DC. The DC might be 48 V, 24 V, 12
V, 5 V, 3 V 1.8 V, 1.0 V, 0.8 V, or who knows. The voltage depends
on the type of IC and the application.

Many ICs are battery operated, whether it’s your phone, watch,
heart rate monitor, mouse, keyboard, game controller or car.

For batteries the voltage is determined by the difference in Fermi

level on the two electrodes, and the Fermi level (chemical potential)
is a function of the battery chemistry. As a result, we need to know
the battery chemistry in order to know the voltage.

Linden’s Handbook of Batteries is a good book if you want to

dive deep into primary (non-chargeable) or secondary (chargeable)
batteries and their voltage curves.
196 13 Voltage regulation

Some common voltage sources are listed below.

Chemistry Voltage [V]

Primary Cell LiFeS2 , Zn/Alk/MnO2 , LiMnO2 0.8 - 3.6
Secondary Cell Li-Ion 2.5 - 4.3
USB - 4.0 - 6.5 (20)

The battery determines the voltage of the “electron source”, how-

ever, can’t we just run everything directly off the battery? Why do
we need DC to DC converters or voltage regulators?

Turns out, transistors can die.

Today’s transistor, as shown below, are a complicated three dimen-

sional structure. Dimensions are measured in nano-meter, which
makes the transistors fragile.

In Analog Circuit Design in Nanoscale CMOS Technologies Lanny

explains how to design around some of the breakdown effects.
 13.1 Voltage source 197

The transistors in a particular technology (from GlobalFoundries,

TSMC, Samsung or others) have a maximum voltage that they can
survive for a certain time. Exceed that time, or voltage, and the
transistors die.

[Link] Why transistors die

A gate oxide will break due to Time Dependent Dielectric Break-

down (TDDB) if the voltage across the gate oxide is too large. Silicon
oxide can break down at approximately 5 MV/cm. The breakdown
forms a conductive channel from the gate to the channel and is
permanent. After breakdown there will be a resistor of kOhms
between gate and channel.

A similar breakdown phenomena is used in Metal-Oxide RRAM

and the SkyWater ReRAM

Below is an example of ReRAM. In the Pristine state the conduc-

tance is low, resistance is in the hundreds of mega Ohm. In a
transistor we want the oxide to stay high resistive. In ReRAM,
however, we apply a high voltage across the oxide, which forms a
conductive channel across the oxide. Turns out, that the conductive
channel can be flipped back and forth between a high resistive
state, and a low resistive state to store a 1 or a 0 in a non-volatile
manner.
198 13 Voltage regulation

The threshold voltage of a transistor can shift excessively over time

caused by Hot-Carrier Injection (HCI) or Negative Bias Tempera-
ture Instability.

Hot-Carrier injection is caused by electrons, or holes, accelerated

to high velocity in the channel, or drain depletion region , causing
impact ionization (breaking a co-valent bond releasing an elec-
tron/hole pair). At a high drain/source field, and
medium gate/(source or drain) field, the channel minority carriers
can be accelerated to high energy and transition to traps in the
oxide, shifting the threshold voltage.

Negative Bias Temperature Instability is a shift in threshold voltage

due to a physical change in the oxide. A strong electric field across
the oxide for a long time can break co-valent, or ionic bonds, in
the oxide. The bond break will change the forces (stress) in the
amorphous silicon oxide which might not recover. As such, there
might be more traps (states) than before. See Simultaneous Extrac-
tion of Recoverable and Permanent Components Contributing to
Bias-Temperature Instability for more details.

For a long time, I had trouble with “traps in the oxide”“. I had a
hard time visualizing how electrons wandered down the channel
and got caught in the oxide. I was trying to imagine the electric
field, and that the electron needed to find a positive charge in the
oxide to cancel. Diving a bit deeper into quantum mechanics, my
mental image improved a bit, so I’ll try to give you a more accurate
mental model for how to think about traps.

Quantum mechanics tells us that bound electrons can only occupy

fixed states. The probability of finding an electron in a state is given
by the Fermi function, but if there is no energy state at a point in
space, there cannot be an electron there.

For example, there might be a 50 % probability of finding an

electron in the oxide, but if there is no state there, then there will
not be any electron , and thus no change to the threshold voltage.
 13.1 Voltage source 199

What happens when we make “traps”, through TDDB, HCI, or

NBTI is that we create new states that can potentially be occupied
by electrons. For example one, or more, broken silicon co-valent
bonds and a dislocation of the crystal lattice.

If the Fermi-Dirac statistics tells us the probability of an electron

being in those new states is 50 %, then there will likely be electrons
there.

The threshold voltage is defined as the voltage at which we can

invert the channel, or create the same density of electrons in the
channel (for NMOS) as density of dopant atoms (density of holes)
in the bulk.

If the oxide has a net negative charge (because of electrons in

new states), then we have to pull harder (higher gate voltage) to
establish the channel. As a result, the threshold voltage increases
with electrons stuck in the oxide.

In quantum mechanics the time evolution, and the complex proba-

bility amplitude of an electron changing state, could, in theory, be
computed with the Schrodinger equation. Unfortunately, for any
real scenario, like the gate oxide of a transistor, using Schrodinger
to compute exactly what will happen is beyond the capability of
the largest supercomputers.

13.1.1 Core voltage

The voltage where the transistor can survive is estimated by the

foundry, by approximation, and testing, and may be like the table
below.

Node [nm] Voltage [V]

180 1.8
130 1.5
55 1.2
22 0.8

13.1.2 IO voltage

Most ICs talk to other ICs, and they have a voltage for the general
purpose input/output. The voltage reduction in I/O voltage does
not need to scale as fast as the core voltage, because foundries have
thicker oxide transistors that can survive the voltage.

Voltage [V]
5.0
3.0
1.8
1.2
200 13 Voltage regulation

13.1.3 Supply planning

For any IC, we must know the application. We must know where
the voltage comes from, the IO voltage, the core voltage, and any
other requirements (like charging batteries).

One example could be an IC that is powered from a Li-Ion battery,

with a USB to provide charging capability.

Between each voltage we need an analog block, a regulator, to

reduce the voltage in an effective manner. What type of regulator
depends again on the application, but the architecture of the analog
design would be either a linear regulator, or a switched regulator.

5 OV
VBUS

BAT O 2.50 4.30

10 1.8 V

IO BIASIANA
In 50m In loom
0.80
CORE
RISC V ADC RADIO
In 50M In Im In 300m

The dynamic range of the power consumed by an IC can be large.

From nA when it’s not doing anything, to hundreds of mA when
there is high computation load.

As a result, it’s not necessarily possible, or effective, to have one

regulator from 1.8 V to 0.8 V. We may need multiple regulators.
Some that can handle low load (nA - 𝜇A) effectively, and some that
can handle high loads.

For example, if you design a regulator to deliver 500 mA to the

load, and the regulator uses 5 mA, that’s only 1 % of the current,
which may be OK. The same regulator might consume 5 mA even
though the load is 1 uA, which would be bad. All the current flows
in the regulator at low loads.

Name Voltage Min [nA] Max [mA] PWR DR [dB]

VDD_VBUS 5 10 500 77
VDD_VBAT 4 10 400 76
VDD_IO 1.8 10 50 67
VDD_CORE 0.8 10 350 75

Most product specifications will give you a view into what type of
regulators there are on an IC. The picture below is from nRF5340
(page 23)
 13.2 Linear Regulators 201

13.2 Linear Regulators

13.2.1 PMOS pass-fet

One way to make a regulator is to control the current in a PMOS

with a feedback loop, as shown below. The OTA continuously
adjusts the gate-source voltage of the PMOS to force the input
voltages of the OTA to be equal.

IN W
it 1,5

0,8V
0,8V

TI LOAD
I

For digital loads, where 𝐼 𝑙𝑜𝑎𝑑 is a digital current, with high current
every rising edge of the clock, it’s an option to place a large external
decoupling capacitor (a reservoir of charge) in parallel with the
load. Accordingly, the OTA would supply the average current.

The device between supply (1.5 V) and output voltage (0.8 V) is

often called a pass-fet. A PMOS pass-fet regulator is often called

Dos for IEEE

202 13 Voltage regulation

a LDO, or low dropout regulator, since we only need a 𝑉𝐷𝑆𝑆𝐴𝑇

across the PMOS, which can be a few hundred mV.

Key parameters of regulators are

Parameter Description Unit

Load regulation How much does the output voltage change with load current V/A
Line regulation How much does the output voltage change with input voltage V/V
Power supply What is the transfer function from input voltage to output dB
rejection ratio voltage? The PSRR at DC is the line regulation
Max current How much current can be delivered through the pass-fet? A
Quiescent What is the current used by the regulator A
current
Settling time How fast does the output voltage settle at a current step s

A disadvantage of a PMOS is the hole mobility, which is lower

than for NMOS. If the maximum current of an LDO is large, then
the PMOS can be big. Maybe even 50 % of the IC area.

13.2.2 NMOS pass-fet

An NMOS pass-fet will be smaller than a PMOS for large loads.

The disadvantage with an NMOS is the gate-source voltage needed.
For some scenarios the needed gate voltage might exceed the input
voltage (1.5 V). A gate voltage above input voltage is possible,
but increases complexity, as a charge pump (switched capacitor
regulator) is needed to make the gate voltage.

Another interesting phenomena with NMOS pass-fet is that the

PSRR is usually better, but we do have a common gate amplifier,
as such, high frequency voltage ripple on output voltage will be
amplified to the input voltage, and may cause issues for others
using the input voltage.

W
it 1,5

0,8V
0,8V

TI LOAD
II LOAD
 13.2 Linear Regulators 203

13.2.3 Control of pass-fet

The large dynamic range in power management systems can make

it challenging to have a single pass-fet.

The size of the pass-fet is set by the maximum Vgs, and the current
that needs to be delivered.

Assume we need 500 mA from the LDO. If we assume that the

maximum Vgs is 1.5 V, then we can simulate to try and find a
size.

I’ve made a testbench at

Testbench for LDO pass-fet

Below is an excerpt from the testbench. The pass-fet size has been
determined by iteration.

The OTA in the LDO is modeled by the B source. Notice the use of
the tanh function in order to keep the G voltage within the rails.

* Pass-fet
XM1 OUT G VDD VDD sky130_fd_pr__pfet_01v8 L=0.252 W=11.52 nf=2 ... m=1000

* Reference
VREF VREF 0 dc 0.8

* OTA
BOTA G 0 V=(1 + tanh(-1000*(v(vref) -v(out) )))/2*{AVDD}

* Load cap
CL OUT 0 1u

* Current load
ILOAD OUT 0 pwl 0 0 1u 0 50u 0.5

Below is a plot of the current on the y-axis as a function of the Vgs

on the x-axis. Although it’s possible to have almost 6 orders of
magnitude change in current in the transistor it does become hard
to make the loop stable over such a large range.

Sometimes it’s easier to split the range into multiple ranges.

204 13 Voltage regulation

v(il) output_loadreg/loadreg_SchGtKttTtVt.raw

10 1

10 2

10 3

10 4

10 5

0.6 0.8 1.0 1.2 1.4

As such, there are multiple control options for the pass-fet. Below
is a summary of a few methods.

We can control the Vgs, or we can switch the number of instances,

or we can turn the pass-fet on and off dynamically. What we choose
will depend on the application.

1 1 1 DutyCycle
Control

or

ILOAD ILOAD ILOAD

13.3 Switched Regulators

VinLinear regulatorVoat Vin

have poor power [Link]
Linear regulators have
the same current in the load, as from the input.

For some applications a poor efficiency might be OK, but for most
battery operated systems we’re interested in using the electrons
from the battery in the most effective manner.

Another challenge is temperature. A linear regulator with a 5 V

input voltage, and 1 V output voltage will have a maximum power
efficiency of 20 % (1/5). 80 % of the power is wasted in the pass-fet
as heat.

Imagine a LDO driving an 80 W CPU at 1 V from a 5 V power

supply. The power drawn from the 5 V supply is 400 W, as such,
320 W would be wasted in the LDO. A quad flat no-leads (QFN)
package usually have a thermal resistance of 20 ◦ C/W, so if it
 13.3 Switched Regulators 205

would be possible, the temperature of the LDO would be 6400 ◦ C.

Obviously, that cannot work.

For increased power efficiency, we must use switched regulators.

Imagine a switched regulator with 93 % power efficiency. The

power from the 5 V supply would be 80 W/0.93 = 86 W, as
such, only 6 W is wasted as heat. A temperature increase of
6 W × 20 ◦ C/W = 120◦ C is still high, but not impossible with a
small heat-sink.

All switched regulators are based on devices that store electric

field (capacitors), or magnetic field (inductors).

13.3.1 Principles of switched regulators

There is a big difference between the idea for a cir-

cuit, and the actual implementation. A real DC/DC
implementation may seem overwhelming.

Just look at figure 7 in A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak

Efficiency Time-Based Buck Converter With Seamless Transition
Between PWM/PFM Modes

So before we go into details, let’s have a look at the principles.

[Link] Inductive BUCK DC/DC

Below is a common illustration of a inductive DC/DC to step down

the voltage.

Imagine Vout is at our desired output voltage, for example 0.8 V.

Assume Vin is 1.8 V.

When we close the switch, the inductor will begin to integrate

the voltage across the inductor, and the current from Vin to Vout
increases.

When we turn off the switch, the inductor current will not stop
immediately, it cannot, that’s what

𝑑𝐼
𝑉=𝐿
𝑑𝑡

tells us. As a result, the current continues, but now the current is
pulled from ground through the diode.

Since we’re pulling current from ground, it should be intuitive that

the current from Vin is less than the load current at Vout, assuming
Vin > Vout.
206 13 Voltage regulation

The output voltage can be controlled by how long we turn on the

switch. Each time we turn on the switch the inductor will inject a
charge packet into the load capacitance.

If we have a control loop on the output voltage, then we can get an

output voltage that is independent of the input voltage.

Vin Voat Vin

[Link] Capacitive BUCK DC/DC

In a capacitive buck below what we’re doing is charging two

capacitors in series to a high voltage, Vin, and then re-configuring
the capacitors to be in parallel.

If the capacitors are the same size, then the output voltage would
be half the input voltage.

To re-configure the circuit we’d use switches.

A disadvantage with capacitive bucks is that the output voltage

is always a factor of the input voltage. When the input voltage
changes, the output voltages changes proportionally.

Often we have to insert an LDO after a capacitive buck to make

the output voltage independent of input voltage.
 13.3 Switched Regulators 207

1 1 1 DutyCycle
Control
A
or
Vink
Vin A C
OAD ILOAD ILOAD

b B D

[Link] Inductive BOOST DC/DC

Consider the circuit below. Here we setup a current from Vin to

ground when the switch is on. When the switch is off push the
current through the diode, and thus, the Vout can be higher than
Vin.

In a similar manner to the Buck, the output voltage will be impacted

by how long we turn on the switch for.

at Vin Voat

[Link] Capacitive BOOST DC/DC

In a capacitive boost we start with a parallel connection, charge the

capacitors to Vin, then reconfigure the circuit to a series combina-
208 13 Voltage regulation

tion.

As such, the output voltage would be two times the input voltage,
assuming the capacitors are equal.

The configuration below is quite often called a “Charge pump”, and

can be configured to generate both positive, or negative voltages.

A
Vin
Vin 3 20in
A C C
Vin

B b b

13.3.2 Inductive DC/DC converter details

I’ve found that people struggle with inductive DC/DCs. They see
a circuit inductors, capacitors, and transistors and think filters,
Laplace and steady state. The path of Laplace and steady state will
lead you astray and you won’t understand how it works.

Hopefully I can put you on the right path to understanding.

In the figure below we can see a typical inductive switch mode

DC/DC converter. The input voltage is 𝑉𝐷𝐷𝐻 , and the output is
𝑉𝑂 .

Most DC/DCs are feedback systems, so the control will be adjusted

to force the output to be what is wanted, however, let’s ignore
closed loop for now.
 13.3 Switched Regulators 209

Buch
Mott Ex
Vo
Ix C R
Vo
Control B

To see what happens I find the best path to understanding is to

look at the integral equations. Vx
I The current in theL
Cdg Idt is given by
inductor

∫
1
V
LEI I
Efrat
𝐼 𝑥 (𝑡) =
𝐿
𝑉𝑥 (𝑡)𝑑𝑡
t T t
t

Ix by
and the voltage on the capacitor is given
I Ct I CDHVodt I In
I1 ∫
III Salt 𝑉𝑜 (𝑡) =
𝐶 II (𝐼 (𝑡) − 𝐼 (𝑡))𝑑𝑡
𝑥 𝑜
t
NII tx t
Before you dive into Matlab, Mathcad, Maple, SymPy or another
Ialt If
Vodtmath software, it helps to think a bit.
A favorite
ofI your
it
Vo TSIM
VIIIT t
qt is not great, but I don’t think there is any closed
My mathematics I VIA I
form solution to the output voltage of the DC/DC, especially since
ME
t state
the VEII th [Link] t
of thet NMOS and PMOS is time-dependent.

The output voltage also affect the voltage across the inductor, which
affects the current, which affects the output voltage, etc, etc.

The equations can be solved numerically, but a numerical solution

to the above integrals needs initial conditions.

There are many versions of the control block, let’s look at two.

13.3.3 Pulse width modulation (PWM)

Assume 𝐼 𝑥 = 0 and 𝐼 𝑜 = 0 at 𝑡 = 0. Assume the output voltage

is 𝑉𝑂 = 0. Imagine we set 𝐴 = 1 for a fixed time duration. The
voltage at 𝑉1 = 𝑉𝐷𝐷𝐻 , and 𝑉𝑥 = 𝑉𝑉 𝐷𝐷𝐻 − 𝑉𝑂 . As 𝑉𝑥 is positive,
and roughly constant, the current 𝐼 𝑥 would increase linearly, as
given by the equation of the current above.

Since the 𝐼 𝑥 is linear, then the increase in 𝑉𝑜 would be a second

order, as given by the equation of the output voltage above.
210 13 Voltage regulation

Let’s set 𝐴 = 0 and 𝐵 = 1 for fixed time duration (it does not need
to be the same as duration as we set 𝐴 = 1). The voltage across the
inductor would be 𝑉𝑥 = 0 − 𝑉𝑜 . The output voltage would not have
increased much, so the absolute value of 𝑉𝑥 during 𝐴 = 1 would
be higher than the absolute value of 𝑉𝑥 during the first 𝐵 = 1.

The 𝑉𝑥 is now negative, so the current will decrease, however, since

𝑉𝑥 is small, it does not decrease much.

I’ve made a

Jupyter PWM BUCK model

that numerically solves the equations.

In the figure below we can see how the current during A increases
fast, while during B it decreases little. The output voltage increases
similarly to a second order function.

0.25 Ix
0.20 Io
0.15
0.10
0.05
0.00

0.03
0.02
vo

0.01
0.00
1
A

0
0.00 0.05 0.10 0.15 0.20 0.25
Time [us]

If we run the simulation longer, see plot below, the DC/DC will
start to settle into a steady state condition.

On the top we can see the current 𝐼 𝑥 and 𝐼 𝑜 , the second plot you
can see the output voltage. Turns out that the output voltage will
be

𝑉𝑜 = 𝑉𝑖𝑛 × Duty-Cycle

, where the duty-cycle is the ratio between the duration of 𝐴 = 1

and 𝐵 = 1.
 13.3 Switched Regulators 211

0.6
Ix
Io
0.4

0.2

0.0

1.00
0.75
vo

0.50
0.25
0.00
1
A

0
0 2 4 6 8 10
Time [us]

Once the system has fully settled, see figure below, we can see the
reason for why DC/DC converters are useful.

During 𝐴 = 1 the current 𝐼 𝑥 increases fast, and it’s only during

𝐴 = 1 we pull current from 𝑉𝐷𝐷𝐻 . At the start of 𝐴 = 0 the current
is still positive, which means we pull current from ground. The
average current in the inductor is the same as the average current
in the load, however, the current from 𝑉𝐷𝐷𝐻 is lower than the
average inductor current, since some of the current comes from
ground.

If the DC/DC was 100% efficient, then the current from the 4
V input supply would be 1/4’th of the 1 V output supply. 100%
efficient DC/DC converters violate the laws of nature, as such, we
can expect to get up to 9X% under optimal conditions.

0.06
0.04 Ix
Io
0.02
0.00
0.02
0.04
0.06
0.990

0.989
vo

0.988

0.987
1
A

0
13.60 13.65 13.70 13.75 13.80 13.85 13.90 13.95 14.00
Time [us]
212 13 Voltage regulation

13.3.4 Real world use

DC/DC converters are used when power efficiency is important.

Below is a screenshot of the hardware description in the nRF5340
Product Specification.

We can see 3 inductor/capacitor pairs. One for the “VDDH”, and

two for “DECRF” and “DECD”, as such, we can make a good guess
there are three DC/DC converters inside the nRF5340.

13.3.5 Pulsed Frequency Mode (PFM)

Power efficiency is key in DC/DC converters. For high loads, PWM,

as explained above, is usually the most efficient and practical. For
lighter loads, other configurations can be more efficient.

In PWM we continuously switch the NMOS and PMOS, as such,

the parasitic capacitance on the 𝑉1 node is charged and discharged,
consuming power. If the load is close to 0 A, then the parasitic
load’s can be significant.

In pulsed-frequency mode we switch the NMOS and PMOS when

it’s needed. If there is no load, there is no switching, and 𝑉1 or
𝐷𝐶𝐶 in figure below is high impedant.
IEEE DC DC 13.3 Switched Regulators 213

I
Vo
CK FSM Da

Vz

Vol
REF

Imagine 𝑉𝑜 is at 1 V, and we apply a constant output load. According

to the integral equations the 𝑉𝑜 would decrease linearly.

In the figure above we observe 𝑉𝑜 with a comparator that sets 𝑉𝑂𝐿

high if the 𝑉𝑜 < 𝑉𝑅𝐸𝐹 . The output from the comparator could be
the inputs to a finite state machine (FSM).

Consider the FSM below. On 𝑣𝑜𝑙 = 1 we transition to “UP” state

where turn on the PMOS for a fixed number of clock cycles. The
inductor current would increase linearly. From the “UP” state
we go to the “DOWN” state, where we turn on the NMOS. The
inductor current would decrease roughly linearly.

The “zero-cross” comparator observes the voltage across the NMOS

drain/source. As soon as we turn the NMOS on the current
direction in the inductor is still from 𝐷𝐶𝐶 to 𝑉𝑜 . Since the current
is pulled from ground, the 𝐷𝐶𝐶 must be below ground. As the
current in the inductor decreases, the voltage across the NMOS
will at some point be equal to zero, at which point the inductor
current is zero.

When 𝑣𝑧 = 1 happens in the state diagram, or the zero cross

comparator triggers, we transition from the “DWN” state back to
“IDLE”. Now the FSM wait for the next time 𝑉𝑜 < 𝑉𝑅𝐸𝐹 .
214 13 Voltage regulation

count < up_cycles

UP
vol = 0 a=1 vz = 0
b=0 count = up_cycles
vol = 1 count++
IDLE DWN
a=0 a=0
b=0
vz = 1 b=1
count=0 count=0

I think the name “pulsed-frequency mode” refers to the fact that

the frequency changes according to load current, however, I’m
not sure of the origin of the name. The name is not important.
What’s important is that you understand that mode 1 (PWM) and
mode 2 (PFM) are two different “operation modes” of a DC/DC
converter.

I made a jupyter model for the PFM mode. I would encourage you
to play with them.

Below you can see a period of the PFM buck. The state can be seen
in the bottom plot, the voltage in the middle and the current in the
inductor and load in the top plot.

Jupyter PFM BUCK model

0.08 Ix
0.06 Io
0.04
0.02
0.00

1.03
1.02
vo

1.01
1.00
0.99
2
STATE

0=IDLE, 1=UP, 2=DWN

0
98 99 100 101 102 103 104 105
Time [us]

13.4 Want to learn more?

Search terms: regulator, buck converter, dc/dc converter, boost

converter
 13.4 Want to learn more? 215

13.4.1 Linear regulators

A Scalable High-Current High-Accuracy Dual-Loop Four-Phase

Switching LDO for Microprocessors Overview of fancy LDO
schemes, digital as well as analog
Development of Single-Transistor-Control LDO Based on Flipped
Voltage Follower for SoC In capacitor less LDOs a flipped voltage
follower is a common circuit, worth a read.
A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual
Loop in Mobile Application Processor Some insights into large
power systems.

13.4.2 DC-DC converters

Design Techniques for Fully Integrated Switched-Capacitor DC-DC

Converters Goes through design of SC DC-DC converters. Good
place to start to learn the trade-offs, and the circuits.
High Frequency Buck Converter Design Using Time-Based Control
Techniques I love papers that challenge “this is the way”. Why
should we design analog feedback loops for our bucks, why not
design digital feedback loops?
Single-Inductor Multi-Output (SIMO) DC-DC Converters With
High Light-Load Efficiency and Minimized Cross-Regulation for
Portable Devices Maybe you have many supplies you want to
drive, but you don’t want to have many inductors. SIMO is then
an option
A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based
Buck Converter With Seamless Transition Between PWM/PFM
Modes Has some lovely illustrations of PFM and PWM and the
trade-offs between those two modes.
A monolithic current-mode CMOS DC-DC converter with on-
chip current-sensing technique In bucks converters there are two
“religious” camps. One hail to “voltage mode” control loop, another
hail to “current mode” control loops. It’s good to read about both
and make up your own mind.
 Clocks and PLLs 14
14.1 Why clocks? . . . . . 217
Keywords: Systems, Feedback, PLL, Integer Divider, SD, SD PLL,
14.1.1 A customer story . . 217
Modulation, linear phase model 14.1.2 Frequency . . . . . . 219
14.1.3 Noise . . . . . . . . . 219
14.1.4 Stability . . . . . . . 219
14.1.5 Conclusion . . . . . . 219
14.1 Why clocks? 14.2 A typical System-
On-Chip clock
system . . . . . . . . 220
Virtually all integrated circuits have some form of clock system. 14.2.1 32 MHz crystal . . . 220
14.2.2 32 KiHz crystal . . . 221
For digital we need clocks to tell us when the data is correct. For 14.2.3 PCB antenna . . . . . 221
Radio’s we need clocks to generate the carrier wave. For analog 14.2.4 DC/DC inductor . . 221
we need clocks for switched regulators, ADCs, accurate delay’s or 14.3 PLL . . . . . . . . . . 223
indeed, long delays. 14.3.1 Integer PLL . . . . . 224
14.3.2 Fractional PLL . . . 224
14.3.3 Modulation in PLLs 225
The principle of a clock is simple. Make a 1-bit digital signal that
14.4 PLL Example . . . . 226
toggles with a period 𝑇 and a frequency 𝑓 = 1/𝑇 .
14.4.1 Loop gain . . . . . . 227
14.4.2 Controlled oscillator 227
The implementation is not necessarily simple. 14.4.3 Phase detector and
charge pump . . . . 229
The key parameters of a clock are the frequency of the fundamental, 14.4.4 Loop filter . . . . . . 230
noise of the frequency spectrum, and stability over process and 14.4.5 Divider . . . . . . . . 230
enviromental conditions. 14.4.6 Loop transfer func-
tion . . . . . . . . . . 231
When I start a design process, I want to know why, how, what (and 14.5 Want to learn more? 233
sometimes who). If I understand the problem from first principles
it’s more likely that the design will be suitable.

But proving that something is suitable, or indeed optimal, is not

easy in the world of analog design. Analog design is similar to
physics. An hypothesis is almost impossible to prove “correct”, but
easier to prove wrong.

14.1.1 A customer story

Take an example.

[Link] Imagine a world

“I have a customer that needs an accurate clock to count

seconds”. – Some manager that talked to a customer,
but don’t understand details.
218 14 Clocks and PLLs

As a designer, I might latch on to the word “accurate clock”, and

translate into “most accurate clock in the world”, then I’d google
atomic clocks, like Rubidium standard that I know is based on
the hyperfine transition of electrons between two energy levels in
rubidium-87.

I know from quantum mechanics that the hyperfine transition

between two energy levels will produce an precise frequency, as the
frequency of the photons transmitted is defined by 𝐸 = ℏ𝜔 = ℎ 𝑓 .

I also know that quantum electro dynamics is the most precise

theory in physics, so we know what’s going on.

As long as the Rubidium crystal is clean (few energy states in the

vicinity of the hyperfine transition), the distance between atoms
stay constant, the temperature does not drift too much, then the
frequency will be precise. So I buy a rubidium oscillator at a cost
of $ 3k.

I design a an ASIC to count the clock ticks, package it plastic, make

a box, and give my manager.

Who will most likely say something like

“Are you insane? The customer want’s to put the clock

on a wristband, and make millions. We can’t have a
cost of $ 3k per device. You must make it smaller an it
must cost 10 cents to make”

Where I would respond.

“What you’re asking is physically impossible. We can’t

make the device that cheap, or that small. Nobody can
do that.”

And both my manager and I would be correct.

[Link] Imagine a better world

Most people in this world have no idea how things work. Very
few people are able to understand the full stack. Everyone of us
must simplify what we know to some extent. As such, as a circuit
designer, it’s your responsibility to fully understand what is asked
of you.

When someone says

” I have a customer that needs an accurate clock to

count seconds”
 14.1 Why clocks? 219

Your response should be “Why does the customer need an accurate

clock? How accurate? What is the customer going to use the clock
for?”. Unless you understand the details of the problem, then your
design will be sub-optimal. It might be a great clock source, but it
will be useless for solving the problem.

14.1.2 Frequency

The frequency of the clock is the frequency of the fundamental. If

it’s a digital clock (1-bit) with 50 % duty-cycle, then we know that
a digital pulse train is an infinite sum of odd-harmnoics, where
the fundamental is given by the period of the train.

14.1.3 Noise

Clock noise have many names. Cycle-to-cycle jitter is how the

period changes with time. Jitter may also mean how the period
right now will change in the future, so a time-domain change in
the amount of cycle-to-cycle jitter. Phase noise is how the period
changes as a function of time scales. For example, a clock might
have fast period changes over short time spans, but if we average
over a year, the period is stable.

What type of noise you care about depends on the problem. Digital
will care about the cycle-to-cycle jitter affects on setup and hold
times. Radio’s will care about the frequency content of the noise
with an offset to the carrier wave.

14.1.4 Stability

The variation over all corners and enviromental conditions is

usually given in a percentage, parts per million, or parts per
billion.

For a digital clock to run a Micro-Controller, maybe it’s sufficient

with 10% accuracy of the clock frequency. For a Bluetooth radio
we must have +-50 ppm, set by the standard. For GPS we might
need parts-per-billion.

14.1.5 Conclusion

Each “clock problem” will have different frequency, noise and

stability requirements. You must know the order of magnitude
of those before you can design a clock source. There is no “one-
solution fits all” clock generation IP.
220 14 Clocks and PLLs

14.2 A typical System-On-Chip clock system

On the nRF52832 development kit you can see some components

that indicate what type of clock system must be inside the IC.

In the figure below you can see the following items.

1. 32 MHz crystal
2. 32 KiHz crystal
3. PCB antenna
4. DC/DC inductor

14.2.1 32 MHz crystal

Any Bluetooth radio will need a frequency reference. We need to

generate an accurate 2.402 MHz - 2.480 MHz carrier frequency
for the gaussian frequency shift keying (GFSK) modulation. The
Bluetooth Standard requires a +- 50 ppm accurate timing reference,
and carrier frequency offset accuracy.

I’m not sure it’s possible yet to make an IC that does not have some
form of frequency reference, like a crystal. The ICs I’ve seen so far
that have “crystal less radio” usually have a resonator (crystal or
bulk-accustic-wave or MEMS resonator) on die.

The power consumption of a high frequency crystal will be pro-

portional to frequency. Assuming we have a digital output, then
the power of that digital output will be 𝑃 = 𝐶𝑉 2 𝑓 , for exam-
ple 𝑃 = 100 fF × 1 V2 × 32 MHz = 3.2 𝜇W is probably close to a
minimum power consumption of a 32 MHz clock.
 14.2 A typical System-On-Chip clock system 221

14.2.2 32 KiHz crystal

Reducing the frequency, we can get down to minimum power

consumption of 𝑃 = 100 fF × 1 V2 × 32 KiHz = 3.2 nW for a
clock.

For a system that sleeps most of the time, and only wakes up at
regular ticks to do something, then a low-frequency crystal might
be worth the effort.

14.2.3 PCB antenna

Since we can see the PCB antenna, we know that the IC includes a
radio. From that fact we can deduce what must be inside the SoC.
If we read the Product Specification we can understand more.

14.2.4 DC/DC inductor

Since we can see a large inductor, we can also make the assumption
that the IC contains a switched regulator. That switched regulator,
especially if it has a pulse-width-modulated control loop, will need
a clock.

From our assumptions we could make a guess what must be inside

the IC, something like the picture below.

There will be a crystal oscillator connected to the crystal. We’ll

learn about those later.

These crystal oscillators generate a fixed frequency, 32 MHz, or 32

KiHz, but there might be other clocks needed inside the IC.

To generate those clocks, there will be phase-locked loops (PLL),

frequency locked loops (FLL), or delay-locked loops (DLL).

PLLs take a reference input, and can generate a higher frequency,

(or indeed lower frequency) output. A PLL is a magical block. It’s
one of the few analog IPs where we can actually design for infinite
gain in our feedback loop.
222 14 Clocks and PLLs

32MHz
Xo
RADIO

PLL PLL Lo

MCU
XO
32768 Hz
RC

Most of the digital blocks on an IC will be synchronous logic, see

figure below. A fundamental principle of sychnronous logic is that
the data at the flip-flops (DFF, rectangles with triangle clock input,
D, Q and Q) only need to be correct at certain times.

The sequence of transitions in the combinatorial logic is of no

consequence, as long as the B inputs are correct when the clock
goes high next time.

The registers, or flip-flops, are your SystemVerilog “always_ff”

code. While the blue cloud is your “always_comb” code.

In a SoC we have to check, for all paths between a Y[N] and B[M]
that the path is fast enough for all transients to settle before the
clock strikes next time. How early the B data must arrive in relation
to the clock edge is the setup time of the DFFs.

We also must check for all paths that the B[M] are held for long
enough after the clock strikes such that our flip-flop does not
change state. The hold time is the distance from the clock edge
to where the data is allowed to change. Negative hold times are
common in DFFs, so the data can start to change before the clock
edge.

In an IC with millions of flip-flops there can be billions of paths.

The setup and hold time for every single one must be checked.
One could imagine a simulation of all the paths on a netlist with
parasitics (capacitors and resistors from layout) to check the delays,
but there are so many combinations that the simulation time
becomes unpractical.

Static Timing Analysis (STA) is a light-weight way to check all

the paths. For the STA we make a model of the delay in each cell
(captured in a liberty file), the setup/hold times of all flip-flops,
 14.3 PLL 223

wire propagation delays, clock frequency (or period), and the

variation in the clock frequency. The process, voltage, temperature
variation must also be checked for all components, so the number
of liberty files can quickly grow large.
Enable Clk out
Logic D Q

Lo
For an analog designer the constraints from digital will tell us
what’s the maximumClkfrequency
in we can have at any point in time,
and what is the maximum cycle-to-cycle variation in the period.

Alo yo XXX Bos x o3

BED XD
AID

Clk out

14.3 PLL

PLL, or it’s cousins FLL and DLL are really cool. A PLL is based
on the familiar concept of feedback, shown in the figure below. As
long as we make 𝐻(𝑠) infinite we can force the output to be an
exact copy of the input.

VI VX
Hs
V0

Vo Vx H s
VI Vo Ux
Vo I
VI Vo YE
224 14 Clocks and PLLs

14.3.1 Integer PLL

For a frequency loop the figure looks a bit different. If we want a

higher output frequency we can divide the frequency by a number
VI
(N) and compare V0example the 32 MHz
VXwith our reference (for
Hs
reference from the crystal oscillator).

apply Vx
error, Vo
theUx H function 𝐻(𝑠) with high
s
VI
We then takeVo a transfer
gain, and control our oscillator frequency.
Vo Vo I
VI YE frequency is too high, we force the os-
If the down-divided output
cillator to a lower frequency. If the down-divided output frequency
is too low we force the oscillator to a higher frequency.

If we design the 𝐻(𝑠) correctly, then we have 𝑓𝑜 = 𝑁 × 𝑓𝑖𝑛

fin to
yes

Sometimes you want a finer frequency resolution, in that case

𝑓𝑖𝑛
you’d add a divider on the reference and get 𝑓𝑜 = 𝑁 × 𝑀 ..

fin M Hcs
to

14.3.2 Fractional PLL

ED N
Trouble is that dividing down the input frequency will reduce your
fin to
loop bandwidth, as the low-pass filter needs to be about 1/10’th of
yes
the reference frequency. As such, the PLL will respond slower to a
frequency change.

We can also use a fractional divider, where we swap between two,

or more, integeres in a sigma-delta fashion in the divider.
 14.3 PLL 225

ED N

fin to
yes

14.3.3 Modulation in PLLs

From your signal processing, or communication courses, you may

recognize the equation below.

𝐴𝑚 (𝑡) × 𝑐𝑜𝑠 2𝜋 𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 𝑡 + 𝜙 𝑚 (𝑡)

The 𝐴𝑚 is the amplitude modulation, while the 𝜙 𝑚 is the phase

ED
modulation. Bluetooth Low Energy is constant
N envelope, so the
𝐴𝑚 is a constant. The phase modulation is applied to the carrier,
fin
but how is it done? to
yes
One option is shown below. We could modulate our frequency
reference directly. That could maybe be a sigma-delta divider on
the reference, or directly modulating the oscillator.

Amos N

fin to
His N

Most modern radios, however, will have a two-point modulation.

The modulation signal is applied to the VCO (or DCO), and the
opposite signal is applied to the feedback divider. As such, the
modulation is not seen by the loop.

food

ED N

fin to
yes
fmod
226 14 Clocks and PLLs

14.4 PLL Example

I’ve made an example PLL that you can download and play with.
I make no claims that it’s a good PLL. Actually, I know it’s a bad
PLL. The ring-oscillator frequency varies to fast with the voltage
control. But it does give you a starting point.

A PLL can consist of a oscillator (SUN_PLL_ROSC) that generates

our output frequency. A divider (SUN_PLL_DIVN) that generates a
feedback frequency that we can compare to the reference. A Phase
and Frequency Detector (SUN_PLL_PFD) and a charge-pump
/Users/wulff/pro/aicex/ip/sun_pll_sky130nm/design/SUN_PLL_SKY130NM/SUN_PLL.sch
(SUN_PLL_CP) that model the +, or the comparison function
in our previous picture. And a loop filter (SUN_PLL_LPF and
SUN_PLL_BUF) that is our 𝐻(𝑠).

CK_REF x 32 PLL (max 512 MHz)

AVDD

VDD_ROSC
CP_UP_N

xa1 xa5
xa0
AVDD

AVDD
AVDD

Kcp = Ibp/2pi xa4

AVDD
VLPF

CK_REF CK_REF CP_UP_N CP_UP_N VO VDD_ROSC

PWRUP_1V8

CK_FB CP_DOWN CP_DOWN LPF VI CK CK

PWRUP_1V8
VFB
CP_DOWN

xd0
VLPF
AVSS

AVSS

LPFZ
AVSS
KICK
VBN

VBN

AVSS
VLPFZ

SUN_PLL_PFD SUN_PLL_CP SUN_PLL_BUF

VLPFZ
SUN_PLL_ROSC

KICK
AVSS

xaa6

AVDD
SUN_PLL_LPF
IBPSR_1U CK_FB 1
CK

PWRUP_1V8
CK_FB 32

AVSS
xbb1
xaa3

BIAS
IBPSR_1U

AVDD KICK SUN_PLL_DIVN

PWRUP_1V8 KICK_N
AVSS

AVSS PWRUP_1V8_N PWRUP_1V8_N

PWRUP_1V8_N

SUN_PLL_KICK
SUN_PLL_BIAS
PWRUP_1V8

Designer Carsten Wulff

AVSS Updated wulff
Modified 2024-02-29 [Link]
Copyright Carsten Wulff Software
Library/Cell SUN_PLL

Read any book on PLLs, talk to any PLL designer and they will all
tell you the same thing. PLLs require calculation. You must setup
a linear model of the feedback loop, and calculate the loop transfer
function to check the stability, and the loop gain. This is the way!
(to quote Mandalorian).

But how can we make a linear model of a non-linear system? The

voltages inside a PLL must be non-linear, they are clocks. A PLL is
not linear in time-domain!

I have no idea who first thought of the idea, but it turns out, that
one can model a PLL as a linear system if one consider the phase
of the voltages inside the PLL, especially when the PLL is locked
(phase of the output and reference is mostly aligned). Where the
phase is defined as

∫ 𝑡
𝜙(𝑡) = 2𝜋 𝑓 (𝑡)𝑑𝑡
0

As long as the bandwidth of the 𝐻(𝑠) is about 10

1
of the reference
frequency, then the linear model below holds (at least is good
enough).
 14.4 PLL Example 227

The phase of our input is 𝜙 𝑖𝑛 (𝑠), the phase of the output is 𝜙(𝑠),
the divided phase is 𝜙 𝑑𝑖𝑣 (𝑠) and the phase error is 𝜙 𝑑 (𝑠).

The 𝐾 𝑝𝑑 is the gain of our phase-frequency detector and charge-

pump. The 𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) is our loop filter 𝐻(𝑠). The 𝐾 𝑜𝑠𝑐 /𝑠 is our
oscillator transfer function. And the 1/𝑁 is our feedback divider.

Girls OÉpd 0 s
Kuhns Kosel

Oldies
YN

14.4.1 Loop gain

ked Koeller Kosel
OdeThe0in
loop transfer function can then be analyzed and we get.

𝜙𝑑 1
Old din
It [Link] 𝜙𝑖𝑛 = 1 + 𝐿(𝑠)
𝐾 𝑜𝑠𝑐 𝐾 𝑝𝑑 𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠)

IE
𝐿(𝑠) =
ILG 𝑁𝑠

Here is the magic of PLLs. Notice what happens when 𝑠 = 𝑗𝜔 = 𝑗 0,

or at zero frequency. If we assume that 𝐻𝑙𝑝 (𝑠) is a low pass
filter, then 𝐻𝑙𝑝 (0) = constant. The loop gain, however, will have a
𝐿(0) ∝ 01 which approaces infinity at 0.
That means, we have an infinite DC gain in the loop transfer
function. It is the only case I know of in an analog design where we
can actually have infinite gain. Infinite gain translate can translate
to infinite precision.

If the reference was a Rubidium oscillator we could generate

any frequency with the same precision as the frequency of the
Rubidium oscillator. Magic.

For the linear model, we need to figure out the factors, like 𝐾 𝑣𝑐𝑜 ,
which must be determined by simulation.

14.4.2 Controlled oscillator

The gain of the oscillator is the change in output frequency as a

function of the change of the control node. For a voltage-controlled
oscillator (VCO) we could sweep the control voltage, and check the
frequency. The derivative of the f(V) would be proportional to the
𝐾 𝑣𝑐𝑜 .
 228 14 Clocks and PLLs

The control node does not need to be a voltage. Anything that

changes the frequency of the oscillator can be used as a control node.
There exist PLLs with voltage control, current control, capacitance
control, and digital control.

For the SUN_PLL_ROSC it is the VDD of the ring-oscillator (VDD_-

ROSC) that is our control node.

𝑑𝑓
𝐾 𝑜𝑠𝑐 = 2𝜋
𝑑𝑉𝑐𝑛𝑡𝑙
VDD_ROSC

AVDD xaa5

xaa4

VO VDD_ROSC
CK
PWRUP_1V8

VFB
AVSS

SUN_PLL_BUF
SUN_PLL_ROSC

xaa6
[Link] SUN_PLL_SKY130NM/sim/ROSC/
AVDD
CK_FB

I simulate the ring oscillator in ngspice with a transient simulation

1
and get the oscillator frequency as a function of voltage.

[Link] CK
PWRUP_1V8

let start_v = 1.1

CK_FB 32
let stop_v = 1.7
let delta_v = 0.1
AVSS

let v_act = start_v

* loop
while v_act le stop_v
alter VROSC v_act
tran 1p 40n
meas tran vrosc avg v(VDD_ROSC) SUN_PLL_DIVN
meas tran tpd trig v(CK) val='0.8' rise=10 targ v(CK) val='0.8' rise=11
let v_act = v_act + delta_v
end
 14.4 PLL Example 229

I use [Link] to extract the time-domain signal from ngspice into

a CSV file.
Then I use a python script to extract the 𝐾 𝑜𝑠𝑐
[Link]
df = pd.read_csv(f)
freq = 1/df["tpd"]
kvco = [Link]([Link]()/df["vrosc"].diff())

Below I’ve made a plot of the oscillation frequency over corners.

tran_LayGtVtKttTt
1200 tran_LayGtVtKssTt
tran_LayGtVtKffTt
tran_LayGtVtKttTh
1000 tran_LayGtVtKssTh
tran_LayGtVtKffTh
Frequency [MHz]

tran_LayGtVtKttTl
tran_LayGtVtKssTl
800 tran_LayGtVtKffTl

600
/Users/wulff/pro/aicex/ip/sun_pll_sky130nm/work/../design/SUN_PLL_SKY130NM/SUN_PLL.sch
400

1.1 1.2 1.3 1.4 1.5 1.6

VDD_ROSC [V]

14.4.3 Phase detector and charge pump

The gain of the phase-detector and charge pump is the current we

feed into the loop filter over a period. I don’t remember why, check
in the book for a detailed description.
16 MHz x 32 = 512 MHz PLL
The two blocks compare our reference clock to our feedback clock,
AVDD
and produce an error signal.

𝐼 𝑐𝑝
𝐾 𝑝𝑑 =
2𝜋
VDD_ROSC
CP_UP_N

xaa1
xaa0
AVDD

AVDD
AVDD

Kcp = Ibp/2pi xaa4

AVDD
VLPF

CK_REF CK_REF CP_UP_N CP_UP_N VO VDD_ROSC

PWRUP_1V8

CK_FB CP_DOWN CP_DOWN LPF VI

PWRUP_1V8

VFB
CP_DOWN

xbb0
VLPF
AVSS

AVSS

LPFZ
AVSS
KICK
VBN

VBN

AVSS
VLPFZ

SUN_PLL_PFD SUN_PLL_CP SUN_PLL_BUF

VLPFZ
SU

KICK
AVSS

SUN_PLL_LPF
CK_FB

IBPSR_1U

xbb1
xaa3

BIAS
IBPSR_1U

AVDD KICK
PWRUP_1V8 KICK_N
SS

AVSS PWRUP_1V8_N PWRUP_1V8_N

 230 14 Clocks and PLLs
_sky130nm/work/../design/SUN_PLL_SKY130NM/SUN_PLL.sch

14.4.4 Loop filter

In the book you’ll find a first order loop filter, and a second order
loop filter. Engineers are creative, so you’ll likely find other loop
filters in the literature.

I would start with the “known to work” loop filters before you
explore on your own.

If you’re really interested in PLLs, you should buy Design of CMOS

Phase-Locked Loops by Behzad Razavi.
16 MHz x 32 = 512 MHz PLL The loop filter has a unity gain buffer. My oscillator draws current,
while the VPLF node is high impedant, so I can’t draw current
from the loop filter without changing the filter transfer function.

 
1 1
𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) = 𝐾 𝑙𝑝 +
𝑠 𝜔𝑧

1 1 + 𝑠𝑅𝐶1
𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠) =
𝑠(𝐶1 + 𝐶2 ) 1 + 𝑠𝑅 𝐶1 𝐶2
𝐶1 +𝐶2

VDD_ROSC
CP_UP_N

xaa1
xaa0
AVDD

AVDD
Kcp = Ibp/2pi xaa4
AVDD
VLPF

CP_UP_N CP_UP_N VO VDD_ROSC

PWRUP_1V8

CP_DOWN CP_DOWN LPF VI

PWRUP_1V8
VFB
CP_DOWN

xbb0
VLPF
AVSS

LPFZ
AVSS
KICK
VBN

VBN

AVSS
VLPFZ

_PLL_PFD SUN_PLL_CP SUN_PLL_BUF

VLPFZ
SUN_P

KICK
AVSS

x
SUN_PLL_LPF
CK_FB

CK_

xbb1
14.4.5 Divider
xaa3

BIAS
IBPSR_1U

AVDD KICK SUN

PWRUP_1V8 KICK_N
The divider is modelled as
AVSS

AVSS PWRUP_1V8_N PWRUP_1V8_N

PWRUP_1V8_N

SUN_PLL_KICK
SUN_PLL_BIAS
1
𝐾 𝑑𝑖𝑣 =
𝑁
B

PWRUP_1
AVSS
14.4 PLL Example 231
UF
SUN_PLL_ROSC

xaa6

AVDD
CK_FB

1
CK

PWRUP_1V8
CK_FB 32

AVSS
SUN_PLL_DIVN

14.4.6 Loop transfer function

Designer Carsten Wulff
Updated wulff
With the loop transfer function we can start to model what happens
Modified 2023-01-22 [Link]
in the linear loop. What is the phase response, and what is the gain
Copyright Carsten Wulff Software
response.

𝐾 𝑜𝑠𝑐 𝐾 𝑝𝑑 𝐾 𝑙𝑝 𝐻𝑙𝑝 (𝑠)

𝐿(𝑠) =
𝑁𝑠

[Link] Python model

I’ve made a python model of the loop, you can find it at sun_pll_-
sky130nm/jupyter/pll

In the jupyter notbook below you can find some more information
on the phase/frequency detector, and charge pump.

sun_pll_sky130nm/jupyter/pfd

Below is a plot of the loop gain, and the transfer function from
input phase to divider phase.

We can see that the loop gain at low frequency is large, and
proportional to 1/𝑠 . As such, the phase of the divided down
feedback clock is the same as our reference.

The closed loop transfer function 𝜙 𝑑𝑖𝑣 /𝜙 𝑖𝑛 shows us that the

divided phase at low frequency is the same as the input phase.
Since the phase is the same, and the frequency must be the same,
then we know that the output clock will be N times reference
frequency.
232 14 Clocks and PLLs

100 Lg
div/ in

Magnitude [dB]
50
0
50
103 104 105 106 107 108
0 Frequency [Hz]
Lg
div/ in

Phase [Degrees]
50
Phase margin = 55.0
100
150

103 104 105 106 107 108

Frequency [Hz]

The top testbench for the PLL is [Link].

I power up the PLL and wait for the output clock to settle. I use
[Link] to plot the frequency as a function of time. The orange curve
is the average frequency. We can see that the output frequency
settles to 256 MHz.

tran_LayGtVtKttTt.raw
mid,end: 259.270,256.04 MHz
500

400
Frequency [MHz]

300

200

100

0
2 4 6 8 10 12 14
Time [us]

You can find the schematics, layout, testbenches, python script etc
at SUN_PLL_SKY130NM

Below are a couple layout images of the finished PLL

 14.5 Want to learn more? 233

14.5 Want to learn more?

Back in 2020 there was a Master student at NTNU on PLL. I would

recommend looking at that thesis to learn more, and to get inspired
Ultra Low Power Frequency Synthesizer.
234 14 Clocks and PLLs

A Low Noise Sub-Sampling PLL in Which Divider Noise is Elimi-

nated and PD/CP Noise is Not Multiplied by N2
All-digital PLL and transmitter for mobile phones
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase
Detector and 560-fsrms Integrated Jitter at 4.5-mW Power
 Oscillators 15
15.1 Atomic clocks . . . . 235
Keywords: Crystal model, Pierce, Temperature, Controlled oscilla-
15.1.1 Microchip 5071B
tor, Ring osc, Ictrl Rosc, DCO Ring, LCOSC, RCOSC Cesium Primary
Time and Frequency
The world depends on accurate clocks. From the timepiece on your Standard . . . . . . . 235
wrist, to the phone in your pocket, they all have a need for an 15.1.2 Rubidium standard 236
accurate way of counting the passing of time. 15.2 Crystal oscillators . 238
15.2.1 Impedance . . . . . . 239
Without accurate clocks an accurate GPS location would not be 15.2.2 Circuit . . . . . . . . 241
possible. In GPS we even correct for Special and General Relativity 15.2.3 Temperature behav-
to the tune of about +38.6𝜇s/day . ior . . . . . . . . . . . 243
15.3 Controlled Oscilla-
Let’s have a look at the most accurate clocks first. tors . . . . . . . . . . 244
15.3.1 Ring oscillator . . . . 244
15.3.2 Capacitive load . . . 245
15.3.3 Realistic . . . . . . . 246
15.1 Atomic clocks 15.3.4 Digitally controlled
oscillator . . . . . . . 248
15.3.5 Differential . . . . . 248
15.3.6 LC oscillator . . . . . 249
Cesium standard
15.4 Relaxation oscilla-
tors . . . . . . . . . . 251
The second is defined by taking the fixed numerical value of the
15.5 Want to learn more? 251
cesium frequency Cs, the unperturbed ground-state hyper-fine
15.5.1 Crystal oscillators . 251
transition frequency of the cesium 133 atom, to be 9 192 631 770 15.5.2 CMOS oscillators . . 252
when expressed in the unit Hz, which is equal to s–1

As a result, by definition, the cesium clocks are exact. That’s how

the second is defined. When we make a real circuit, however, we
never get a perfect, unperturbed system.

15.1.1 Microchip 5071B Cesium Primary Time and

Frequency Standard

One example of a ultra precise time piece is shown below. The

bullets in the list below is from the marketing blurb.

Why would the thing take 30 minutes to start up? Does the tem-
perature need to settle? Is it the loop bandwidth of the PLL that is
low? Who knows, but 30 minutes is too long for a IC startup time.
And we can’t really pack the big box onto a chip.

▶ < 5E-13 accuracy high-performance models

▶ Accuracy levels achieved within 30 minutes of startup
▶ < 8.5E-13 at 100s high-performance models
▶ < 1E-14 flicker floor high-performance models
236 15 Oscillators

Also, when they say

“Ask for a quote” => The price is really high, and we don’t want to
tell you yet

15.1.2 Rubidium standard

Rubidium standard, use the rubidium hyper-fine transition of 6.8

GHz (6834682610.904 Hz)

and can actually be made quite small. Below is a picture of a tiny

atomic clock. According to the marketing blurb:

The MAC is a passive atomic clock, incorporating the interrogation

technique of Coherent Population Trapping (CPT) and operating upon
the D1 optical resonance of atomic Rubidium Isotope 87.

A rubidium clock is basically a crystal oscillator locked to an

atomic reference.
 15.1 Atomic clocks 237

But how do the clocks work? According to Wikipedia, the picture

below, is a common way to operate a rubidium clock.

A light passing through the Rubidium gas will be affected if the

frequency injected is at the hyper-fine energy levels (E = hf). The
change in brightness can be detected by the photo detector, and
we can adjust the frequency of the crystal oscillator, we’ll see later
how that can be done. The crystal oscillator is used as reference
for a PLL (freqency synthesizer ) to generate the exact frequency
needed.

The negative feedback loop ensures that the 5 MHz clock coming
out is proportional to the hyper-fine energy levels in the Rubidium
atoms. Negative feedback is cool! Especially when we have a pole
at DC and infinite gain.
238 15 Oscillators

15.2 Crystal oscillators

For accuracy’s of parts per million, which is sufficient for your

wrist watch, or most communication, it’s possible to use crystals.

A quartz crystal can resonate at specific frequencies. If we apply

a electric field across a crystal, we will induce a vibration in the
crystal, which can again affect the electric field. For some history,
see Crystal Oscillators

The vibrations in the crystal lattice can have many modes, as

illustrated by figure below.

All we need to do with a crystal is to inject sufficient energy to

sustain the oscillation, and the resonance of the crystal will ensure
we have a correct enough frequency.
 15.2 Crystal oscillators 239

15.2.1 Impedance

The impedance of a crystal is usually modeled as below. A RLC

circuit with a parallel capacitor.

Our job is to make a circuit that we can connect to the two pins
and provide the energy we will loose due to 𝑅 𝑠 .
240
I
15 Oscillators

D Rst Sh t IE Zin
Rs
Gp sCp

L Cp

CF

Gin
pkg
Assuming zero series resistance t SCP

SCP
Gin
Eye
𝑍 𝑖𝑛 =
𝑠 2 𝐶 𝐹 𝐿 + t1
𝑠 3 𝐶𝑃 𝐿𝐶 𝐹 + 𝑠𝐶𝑃 + 𝑠𝐶 𝐹

L
É tsar
Notice that at 𝑠 = 0 the impedance goes to infinity, so a crystal is
high impedant at DC.
CF
Cp
fstet
Since the 1/(sCp) does not change much at resonance, then

[Link]
𝐿𝐶 𝐹 𝑠 2 + 1
𝑍 𝑖𝑛 ≈
𝐿𝐶 𝐹 𝐶 𝑝 𝑠 2 + 𝐶 𝐹 + 𝐶𝑃
so
See Crystal oscillator impedance for a detailed explanation.
zm

In the impedance plot below we can clearly see that there are
two “resonance” points. Usually noted by series and parallel
resonance.

I would encourage you to read The Crystal Oscillator for more

details.
 15.2 Crystal oscillators 241

15.2.2 Circuit

Below is a common oscillator circuit, a Pierce Oscillator. The crystal

is the below the dotted line, and the two capacitance’s are the
on-PCB capacitance’s.

Above the dotted line is what we have inside the IC. Call the left
side of the inverter XC1 and right side XC2. The inverter is biased
by a resistor, 𝑅 1 , to keep the XC1 at a reasonable voltage. The XC1
and XC2 will oscillate in opposite directions. As XC1 increases, XC2
will decrease. The 𝑅 2 is to model the internal resistance (on-chip
wires, bond-wire).

n n
242 15 Oscillators

Negative transconductance compensate crystal series resis-

tance

The transconductance of the inverter must compensate for the

energy loss caused by 𝑅 𝑠 in the crystal model. The transconductor
also need to be large enough for the oscillation to start, and build
up.

I’ve found that sometimes people get confused by the negative

transconductance. There is nothing magical about that. Imagine
the PMOS and the NMOS in the inverter, and that the input voltage
is exactly the voltage we need for the current in the PMOS and
NMOS to be the same. If the current in the PMOS and NMOS is
the same, then there can be no current flowing in the output.

Imagine we increase the voltage. The PMOS current would de-

crease, and the NMOS current would increase. We would pull
current from the output.

Imagine we now decrease the voltage instead. The PMOS current

would increase, and the NMOS current would decrease. The
current in the output would increase.

As such, a negative transconductance is just that as we increase

the input voltage, the current into the output decreases, and visa
versa.

Long startup time caused by high Q

The Q factor has a few definitions, so it’s easy to get confused.

Think of Q like this, if a resonator has high Q, then the oscillations
die out slowly.

Imagine a perfect world without resistance, and an inductor and

capacitor in parallel. Imagine we initially store some voltage across
the capacitor, and we let the circuit go. The inductor shorts the
plates of the capacitor, and the current in the inductor will build up
until the voltage across the capacitor is zero. The inductor still has
stored current, and that current does not stop, so the voltage across
the capacitor will become negative, and continue decreasing until
the inductor current is zero. At that point the negative voltage will
flip the current in the inductor, and we go back again.

The LC circuit will resonate back and forth. If there was no resis-
tance in the circuit, then the oscillation would never die out. The
system would be infinite Q.

The Q of the crystal oscillator can be described as 𝑄 = 1/(𝜔𝑅 𝑠 𝐶 𝑓 ),

assuming some common values of 𝑅 𝑠 = 50, 𝐶 𝑓 = 5 𝑒 −15 and
𝜔 = 2𝜋 × 32 MHz then 𝑄 ≈ 20 k.

That number may not tell you much, but think of it like this, it
will take 20 000 clock cycles before the amplitude falls by 1/e.
For example, if the amplitude of oscillation was 1 V, and you stop
 15.2 Crystal oscillators 243

introducing energy into the system, then 20 000 clock cycles later,
or 0.6 ms, the amplitude would be 0.37 V.

The same is roughly true for startup of the oscillator. If the crystal
had almost no amplitude, then an increase 𝑒 would take 20 k
cycles. Increasing the amplitude of the crystal to 1 V could take
milliseconds.

Most circuits on-chip have startup times on the order of microsec-

onds, while crystal oscillators have startup time on the order of
milliseconds. As such, for low power IoT, the startup time of crystal
oscillators, or indeed keeping the oscillator running at a really low
current, are key research topics.

Can fine tune frequency with parasitic capacitance

The resonance frequency of the crystal oscillator can be modified by

the parasitic capacitance from XC1 and XC2 to ground. The tunabil-
ity of crystals is usually in ppm/pF. Sometimes micro-controller
vendors will include internal load capacitance’s to support multiple
crystal vendors without changing the PCB.

15.2.3 Temperature behavior

One of the key reasons for using crystals is their stability over
temperature. Below is a plot of a typical temperature behavior.
The cutting angle of the crystal affect the temperature behavior,
as such, the closer crystals are to “no change in frequency over
temperature”, the more expensive they become.

In communication standards, like Bluetooth Low Energy, it’s com-

mon to specify timing accuracy’s of +- 50 ppm. Have a look in
the Bluetooth Core Specification 5.4 Volume 6, Part A, Chapter 3.1
(page 2653) for details.
244 15 Oscillators

15.3 Controlled Oscillators

On an integrated circuit way may need multiple clocks, and we

can’t have crystal oscillators for all of them. We can use frequency
locked loops, phase locked loops and delay locked loops to make
N r frequency.
multiples of the crystal reference
d
All phase locked loops contain an oscillator where we control the
frequency of oscillation.

15.3.1 Ring oscillator

The simplest oscillator is a series of inverters biting their own tail,

a ring oscillator.

The delay of each stage can be thought of as a RC time constant,

where the R is the transconductance of the inverter, and the C is
the gate capacitance of the next inverter.

𝑡 𝑝𝑑 ≈ 𝑅𝐶

1 1
𝑅≈ ≈
𝑔𝑚 𝜇𝑛 𝐶 𝑜𝑥 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑊
𝐿

2
𝐶≈ 𝐶 𝑜𝑥 𝑊 𝐿
3

tpd
tp

One way to change the oscillation frequency is to change the VDD

of the ring oscillator. Based on the delay of a single inverter we
can make an estimate of the oscillator gain. How large change in
C
frequency do we get for a change in VDD.

2/3𝐶 𝑜𝑥 𝑊 𝐿
𝑡 𝑝𝑑 ≈ 𝑊
𝐿 𝜇𝑛 𝐶 𝑜𝑥 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ ) Erd
1 𝜇𝑛 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 = =
2 𝑁𝑡 𝑝𝑑 3 𝑁𝐿
4 2
 15.3 Controlled Oscillators 245

𝜕𝑓 2𝜋𝜇𝑛
𝐾 𝑣𝑐𝑜 = 2𝜋 = 4
𝜕𝑉 𝐷𝐷 3 𝑁𝐿
2

The 𝐾 𝑣𝑐𝑜 is proportional to mobility, and inversely proportional to

the number of stages and the length of the transistor squared. In
most PLLs we don’t want the 𝐾 𝑣𝑐𝑜 to be too large. Ideally we want
the ring oscillator to oscillate close to the frequency we want, i.e 512
MHz, and a small 𝐾 𝑣𝑐𝑜 to account for variation over temperature
(mobility of transistors decreases with increased temperature, the
threshold voltage of transistors decrease with temperature), and
changes in VDD.

To reduce the 𝐾 𝑣𝑐𝑜 of the standard ring oscillator we can increase

the gate length, and increase the number of stages.

I think it’s a good idea to always have a prime number of stages in

the ring oscillator. I have seen some ring oscillators with 21 stages
oscillate at 3 times the frequency in measurement. Since 21 = 7 × 3
it’s possible to have three “waves” of traveling through the ring
oscillator at all times, forever. If you use a prime number of stages,
then sustained oscillation at other frequencies cannot happen.

As such, then number of inverter stages should be ∈

[3, 5, 7, 11, 13, 17, 19, 23, 29, 31]

15.3.2 Capacitive load

The oscillation frequency of the ring oscillator can also be changed

by adding capacitance.

𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 =
2𝑁 3 𝐶 𝑜𝑥 𝑊 𝐿
2
+𝐶

2𝜋𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿
𝐾 𝑣𝑐𝑜 =
2𝑁 3 𝐶 𝑜𝑥 𝑊 𝐿
2
+𝐶

Assume that the extra capacitance is much larger than the gate
capacitance, then

𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑡 ℎ )
𝑓 =
2𝑁 𝐶

2𝜋𝜇𝑛 𝐶 𝑜𝑥 𝑊
𝐿
𝐾 𝑣𝑐𝑜 =
2𝑁 𝐶

And maybe we could make the 𝐾 𝑣𝑐𝑜 relatively small.

246 15 Oscillators f
[Link] Fifty
The power consumption of an oscillator, however, will be similar
to a digital circuit of 𝑃 = 𝐶 × 𝑓 × 𝑉 𝐷𝐷 2 , so increasing capacitance
will also increase the power consumption.

c c e

15.3.3 Realistic
re
[Link]
Assume you wanted to design a phase-locked loop, what type
of oscillator should you try first? If the noise of the clock is not
too important, so you don’t need an LC-oscillator, then I’d try the
oscillator below, although I’d expand the number of stages to fit
the frequency.

t
ggEYeI tam
The circuit has a capacitance loaded ring oscillator fed by a current.
The 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 will give a coarse control of the frequency, while the
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 can give a more precise control of the frequency.
Since the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 can only increase the frequency it’s important
that the 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is set such that the frequency is below the target.

Most PLLs will include some form of self calibration at startup. At

startup the PLL will do a coarse calibration to find a sweet-spot for
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 , and then use 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 to do fine tuning.
Since PLLs always have a reference frequency, and a phase and
frequency detector, it’s possible to sweep the calibration word for
𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and then check whether the output frequency is above or
below the target based on the phase and frequency detector output.
Although we don’t know exactly what the oscillator frequency is,
we can know the frequency close enough.

It’s also possible to run a counter on the output frequency of the

VCO, and count the edges between two reference clocks. That way
we can get a precise estimate of the oscillation frequency.

Another advantage with the architecture below is that we have

some immunity towards supply noise. If we decouple both the
current mirror, and the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 towards VDD, then any change to
VDD will not affect the current into the ring oscillator.

Maybe a small side track, but inject a signal into an oscillator from
an amplifier, the oscillator will have a tendency to lock to the
 15.3 Controlled Oscillators 247

injected signal, we call this “injection locking”, and it’s common

to do in ultra high frequency oscillators (60 - 160 GHz). Assume
we allow the PLL to find the right 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 that corresponds to the
injected frequency. Assume that the injected frequency changes,
for example frequency shift keying (two frequencies that mean 1
or 0), as in Bluetooth Low Energy. The PLL will vary the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙
of the PLL to match the frequency change of the injected signal, as
such, the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is now the demodulated frequency change.

Still today, there are radio recievers that use a PLLs to directly de-
modulate the incoming frequency shift keyed modulated carrier.

c c e

We can calculate the 𝐾 𝑣𝑐𝑜 of the oscillator as shown below. The

Ijt
inverters mostly act as switches, and when the PMOS is on, then the

cog
[Link]
I
rise time is controlled by the PMOS current mirror, the additional
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and the capacitor. For the calculation below we assume
that the pull-down of the capacitor by the NMOS does not affect
the frequency much.

The advantage with the above ring-oscillator is that we can control

the frequency of oscillation with 𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 and have a independent
𝐾 𝑣𝑐𝑜 based on the sizing of the 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 transistors.

𝑑𝑉
𝐼=𝐶
𝑑𝑡

𝐼 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 + 12 𝜇𝑝 𝐶 𝑜𝑥 𝑊
𝐿 (𝑉 𝐷𝐷 − 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 − 𝑉𝑡 ℎ )
2
𝑓 ≈
𝐶 𝑉 𝐷𝐷
2 𝑁

𝜕𝑓
𝐾 𝑣𝑐𝑜 = 2𝜋
𝜕𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙
248 15 Oscillators

𝜇𝑝 𝐶 𝑜𝑥 𝑊/𝐿
𝐾 𝑣𝑐𝑜 = 2𝜋
𝐶 𝑉 𝐷𝐷
2 𝑁

15.3.4 Digitally controlled oscillator

We can digitally control the oscillator frequency as shown below

by adding capacitors.

Today there are all digital loops where the oscillator is not really
a “voltage controlled oscillator”, but rather a “digital control
oscillator”. DCOs are common in all-digital PLLs.

Another reason to use digital frequency control is to compensate for

process variation. We know that mobility affects the 𝐾 𝑣𝑐𝑜 , as such,
for fast transistors the frequency can go up. We could measure
the free-running frequency in production, and compensate with a
digital control word.

Do Di De

C 2C 4C

15.3.5 Differential

[Link]
Differential circuits are potentially less sensitive to supply noise

Imagine a single ended ring oscillator. If I inject a voltage onto the

input of one of the inverters that was just about to flip, I can either
m
delay the flip, or speed up the flip, depending on whether the
voltage pulse increases or decreases the input voltage for a while.
Such voltage pulses will lead to jitter.

Imagine the same scenario on a differential oscillator (think diff

pair). As long as the voltage pulse is the same for both inputs, then
no change will incur. I may change the current slightly, but that
depends on the tail current source.
[Link] m
Another cool thing about differential circuits is that it’s easy to
15.3 Controlled Oscillators 249

multiply by -1, just flip the wires, as a result, I can use a 2 stage
ring differential ring oscillator.

15.3.6 LC oscillator

Most radio’s are based on modulating information on-to a carrier

frequency, for example 2.402 GHz for a Bluetooth Low Energy
Advertiser. One of the key properties of the carrier waves is that it
must be “clean”. We’re adding a modulated signal on top of the
carrier, so if there is noise inherent on the carrier, then we add
noise to our modulation signal, which is bad.

Most ring oscillators are too high noise for radio’s, we must use a
inductor and capacitor to create the resonator.

Inductors are huge components on a IC. Take a look at the nRF51822

below, the two round inductors are easily identifiable. Actually,
based on the die image we can guess that there are two oscillators
in the nRF51822. Maybe it’s a multiple conversion superheterodyne
reciever
250 15 Oscillators

Below is a typical LC oscillator. The main resonance is set by the

L and C, while the tunability is provided by a varactor, a voltage
variable capacitor. Or with less fancy words, the gate capacitance
of a transistor, since the gate capacitance of a transistor depends
on the effective voltage, and is thus a “varactor”

The NMOS at the bottom provide the “negative transconductance”

to compensate for the loss in the LC tank.

I 1

C fate
Vent
 15.4 Relaxation oscillators 251

1
𝑓 ∝√
𝐿𝐶

15.4 Relaxation oscillators

A last common oscillator is the relaxation oscillator, or “RC” oscil-

lator. By now you should be proficient enough to work through
the equations below, and understand how the circuit works. If not,
ask me.

o n
V
I U
R C

𝑉1 = 𝐼𝑅

V RI 𝑑𝑉
𝐼=𝐶
𝑑𝑡

V2 I 𝐶𝑉2
𝑑𝑡 =
𝐼
CLE
=
𝐶𝐼𝑅
𝐼
re
dt
𝑓 =
1
𝑑𝑡
=
1
𝑅𝐶 EI
1 1
𝑓𝑜 = 𝑓 =
2 2𝑅𝐶

15.5 Want to learn more?

15.5.1 Crystal oscillators

The Crystal Oscillator - A Circuit for All Seasons

High-performance crystal oscillator circuits: theory and applica-

tion

Ultra-low Power 32kHz Crystal Oscillators: Fundamentals and

Design Techniques
252 15 Oscillators

A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection

Crystal Oscillator

15.5.2 CMOS oscillators

The Ring Oscillator - A Circuit for All Seasons

A Study of Phase Noise in CMOS Oscillators
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscil-
lator in 0.18-um CMOS
Ultra Low Power Frequency Synthesizer
 Low Power Radio 16
Keywords: Range, Antenna Size, Modulation, OFDM, GFSK, pi/4- 16.1 Data Rate . . . . . . 253
qpsk, 8-psk, 16 QAM, Bluetooth LE, LP RX, LNA, MIxer, AAF, 16.1.1 Data . . . . . . . . . . 253
ADC, BB 16.1.2 Rate . . . . . . . . . . 254
16.1.3 Data Rate . . . . . . 254
Radio’s are all around us. In our phone, on our wrist, in our house, 16.2 Carrier Frequency &
there is Bluetooth, WiFi, Zigbee, LTE, GPS and many more. Range . . . . . . . . . 254
16.2.1 ISM (industrial, sci-
A radio is a device that receives and transmits light encoded with entific and medical)
information. The frequency of the light depends on the standard. bands . . . . . . . . . 254
How the information is encoded onto the light depends on the 16.2.2 Antenna . . . . . . . 255
standard. 16.2.3 Range (Friis) . . . . . 256
16.2.4 Range (Free space) . 256
Assume that we did not know any standards, what would we do if 16.2.5 Range (Real world) . 257
we wanted to make the best radio IC for gaming mice? 16.3 Power supply . . . . 257
16.3.1 Battery . . . . . . . . 258
There are a few key concepts we would have to know before we
16.4 Decisions . . . . . . 258
decide on a radio type: Data Rate, Carrier Frequency and range,
16.4.1 Modulation . . . . . 258
and the power supply. 16.4.2 BPSK . . . . . . . . . 259
16.4.3 Single carrier, or
multi carrier? . . . . 265
16.1 Data Rate 16.4.4 Use a Software
Defined Radio . . . . 266
16.5 Bluetooth . . . . . . 267
16.1.1 Data 16.5.1 Bluetooth Basic
Rate/Extended Data
A mouse reports on the relative X and Y displacement of the mouse rate . . . . . . . . . . 268
as a function of time. A mouse has buttons. There can be many 16.5.2 Bluetooth Low En-
mice in a room, as such, they must have an address , so PCs can ergy . . . . . . . . . . 268
tell them apart. 16.6 Algorithm to design
state-of-the-art LE
A mouse must be low-power. As such, the radio cannot be on all radio . . . . . . . . . 269
the time. The radio must start up and be ready to receive quickly. 16.6.1 LNTA . . . . . . . . . 270
16.6.2 MIXER . . . . . . . . 271
We don’t know how far away from the PC the mice might be, as 16.6.3 AAF . . . . . . . . . . 273
such, we don’t know the dB loss in the communication channel. As 16.6.4 ADC . . . . . . . . . 273
a result, the radio needs to have a high dynamic range, from weak 16.6.5 AD-PLL . . . . . . . 275
signals to strong signals. In order for the radio to adjust the gain 16.6.6 Baseband . . . . . . . 275
of the reciever we should include a pre-amble, a known sequence, 16.7 What do we really
for example 01010101, such that the radio can adjust the gain, and want, in the end? . . 276
also, recover the symbol timing. 16.8 Want to learn more? 277

All in all, the packets we send from the mouse may need to have
the following bits.

What Bits Why

X displacement 8
Y displacement 8
CRC 4 Bit errors
Buttons 16 One-hot coding. Most mice have buttons
Preamble 8 Synchronization
254 16 Low Power Radio

What Bits Why

Address 32 Unique identifier
Total 76

16.1.2 Rate

Gamers are crazy for speed, they care about milliseconds. So our
mice needs to be able to send and receive data quite often.

Assume 1 ms update rate

16.1.3 Data Rate

To compute the data rate, let’s do a back of the envelope estimate

of the data, and the rate.

Application Data Rate > 76 bits/ms = 76 kbps

Assume 30 % packet loss

Raw Data Rate > 228 kbps

Multiply by 3.14 > 716 kbps

Round to nearest nice number = 1Mbps

The above statements are a exact copy of what happens in industry

when we start design of something. We make an educated guess
and multiply by a number. More optimistic people would multiply
with 𝑒 .

16.2 Carrier Frequency & Range

16.2.1 ISM (industrial, scientific and medical) bands

There are rules and regulations that prevent us from transmitting

and receiving at any frequency we want. We need to pick one of the
ISM bands, or we need to get a license from governments around
the world.

For the ISM bands, there are regions, as seen below.

 16.2 Carrier Frequency & Range 255

▶ Yellow: Region 1
▶ Blue: Region 2
▶ Pink: Region 3

Below is a table of the available frequencies, but how should we

pick which one to use? There are at least two criteria that should
be investigated. Antenna and Range.

Flow Fhigh Bandwidth Description

40.66 MHz 40.7 MHz 40 kHz Worldwide
433.05 MHz 434.79 MHz 1.74 MHz Region 1
902 MHz 928 MHz 26 MHz Region 2
2.4 GHz 2.5 GHz 100 MHz Worldwide
5.725 GHz 5.875 GHz 150 MHz Worldwide
24 GHz 24.25 GHz 250 MHz Worldwide
61 GHz 61.5 GHz 500 MHz Subject to local acceptance

16.2.2 Antenna

For a mouse we want to hold in our hand, there is a size limit to

the antenna. There are many types of antenna, but

assume wavelength/4 is an OK antenna size (wavelength = light-

speed/frequency)

The below table shows the ISM band and the size of a quarter
wavelength antenna. Any frequency above 2.4 GHz may be OK
from a size perspective.

ISM band 𝜆/4 Unit OK/NOK

40.68 MHz 1.8 m :x:
433.92 MHz 17 cm :x:
915 MHz 8.2 cm
2450 MHz 3.06 cm :white_check_mark:
5800 MHz 1.29 cm :white_check_mark:
24.125 GHz 3.1 mm :white_check_mark:
61.25 GHz 1.2 mm :white_check_mark:
256 16 Low Power Radio

16.2.3 Range (Friis)

One of the worst questions a radio designer can get is “What is

the range of your radio?”, especially if the people asking are those
that don’t understand physics, or the real world. The answer to the
question is incredibly complicated, as it depends on exactly what
is between two devices talking.

If we assume, however, that there is only free space, and no real

reflections from anywhere, then we can make an estimate of the
range.

Assume no antenna gain, power density p at distance D is

𝑃𝑇𝑋
𝑝=
4𝜋𝐷 2

Assume reciever antenna has no gain, then the effective aperture

is

𝜆2
𝐴𝑒 =
4𝜋

Power received is then

2
𝑃𝑇𝑋 𝜆

𝑃𝑅𝑋 = 2
𝐷 4𝜋

Or in terms of distance

 
𝑃𝑇𝑋 −𝑃𝑅𝑋 +20𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 20

16.2.4 Range (Free space)

If we take the ideal equation above, and use some realistic numbers
for TX and RX power, we can estimate a range.

Assume TX = 0 dBm, assume RX sensitivity is -80 dBm

20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓 [dB]

Freq D [m] OK/NOK
915 MHz -31.7 260.9 :white_check_mark:
2.45 GHz -40.2 97.4 :white_check_mark:
5.80 GHz -47.7 41.2 :white_check_mark:
24.12 GHz -60.1 9.9 :x:
61.25 GHz -68.2 3.9 :x:
160 GHz -76.52 1.5 :x:
 16.3 Power supply 257

16.2.5 Range (Real world)

In the real world, however, the

path loss factor,

𝑛 ∈ [1.6, 6]
,  
𝑃𝑇𝑋 −𝑃𝑅𝑋 +20 𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 𝑛×10

So the real world range of a radio can vary more than an order of
magnitude. Still, 2.4 GHz seems like a good choice for a mouse.

20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓

Freq [dB] D@n=2 [m] D@n=6 [m] OK/NOK

2.45 GHz -40.2 97.4 4.6 :white_-
check_mark:
5.80 GHz -47.7 41.2 3.45 :white_-
check_mark:
24.12 GHz -60.1 9.9 2.1 :x:

16.3 Power supply

We could have a wired mouse for power, but that’s boring. Why
would we want a wired mouse to have wireless communication?
It must be powered by a battery, but what type of battery?

There exists a bible of batteries, see picture below. It’s worth a

read if you want to dive deeper into chemistry and properties of
primary (non-chargeable) and secondary (chargeable) cells.
258 16 Low Power Radio

16.3.1 Battery

Mouse is maybe AA, 3000 mAh

Cell Chemistry Voltage (V) Capacity (Ah)

AA LiFeS2 1.0 - 1.8 3
2xAA LiFeS2 2.0 - 3.6 3
AA Zn/Alk/MnO2 0.8 - 1.6 3
2xAA Zn/Alk/MnO2 1.6 - 3.2 3

16.4 Decisions

Now we know that we need a 1 Mbps radio at 2.4 GHz that runs
of a 1.0 V - 1.8 V or 2.0 V - 3.6 V supply.
Next we need to decide what modulation scheme we want for our
light. How should we encode the bits onto the 2.4 GHz carrier
wave?

16.4.1 Modulation

Any modulation can be described by the function below.

𝐴𝑚 (𝑡) × 𝑐𝑜𝑠 2𝜋 𝑓𝑐𝑎𝑟𝑟𝑖𝑒𝑟 (𝑡)𝑡 + 𝜙 𝑚 (𝑡)

The amplitude of the carrier can be modulated, or the phase of the

carrier.
 16.4 Decisions 259

People have been creative over the last 50 years in terms of encoding
bits onto carriers. Below is a small excerpt of some common
schemes.

Scheme Acronym Pro Con

Binary phase shift BPSK Simple Not constant
keying envelope
Quadrature QPSK 2bits/symbol Not constant
phase-shift keying envelope
Offset QPSK OQPSK 2bits/symbol Constant envelope
with half-sine pulse
shaping
Gaussian GFSK 1 bit/symbol Constant envelope
Frequency Shift
Keying
Quadrature QAM > 1024 bits/symbol Really non-constant
amplitude envelope
modulation

16.4.2 BPSK

In binary phase shift keying the 1 and 0 is encoded in the phase

change. Change the phase 180 degrees and we’ve transitioned from
a 0 to a 1. Do another 180 degrees and we’re back to where we
were.

It’s common to show modulation schemes in a constellation dia-

gram with the real axis and the complex axis. For the real light we
send the phase and amplitude is usually real.

I say usually, because in quantum mechanics, and the time evolution

of a particle, the amplitude of the wave function is actually a
complex variable. As such, nature is actually complex at the most
fundamental level.

But for now, let’s keep it real in the real world.

Still, the maths is much more elegant in the complex plane.

The equation for the unit circle is 𝑦 = 𝑒 𝑖(𝜔𝑡+𝜙) where 𝜙 is the phase,
and 𝜔 is the angular frequency.

Imagine we spin a bike wheel around at a constant frequency

(constant 𝜔 ), on the bike wheel there is a red dot. If you keep your
eyes open all the time, then the red dot would go round and round.
But imagine that you only opened your eyes every second for a
brief moment to see where the dot was. Sometimes it could be on
the right side, sometimes on the left side. If our “eye opening rate”,
or your sample rate, matched how fast the “wheel rotator” changed
the location of the dot, then you could receive information.

Now imagine you have a strobe light matched to the “normal” car-
rier frequency. If one rotation of the wheel matched the frequency
of the strobe light, then the red dot would stay in exactly the same
place. If the wheel rotation was slightly faster, then the red dot
would move one way around the circle at every strobe. If the wheel
 A
260 16 Low Power Radio

X X Ae
R
rotation was slightly slower, the red dot would move the other way
around the circle.

X
That’s exactly how we can change the position in the constellation.
We increase the carrier frequency for a bit to rotate 180 degrees,
and we can decrease the frequency to go back 180 degrees. In
this example the dot would move around the unit circle, and the
amplitude of the carrier can stay constant.

X X
R

There is another way to change phase 180 degrees, and that’s simply
to swap the phase in the transmitter circuit. Imagine as below we
have a local oscillator driving pseudo differential common source
stages with switches on top. If we flip the switches we can change
the phase 180 degrees pretty fast.

A challenge is, however, that the amplitude will change. In general,

constant envelope (don’t change amplitude) modulation is less
bandwidth efficient (slower) than schemes that change both phase
and amplitude.
 16.4 Decisions 261

met IR 10 10

bo Jo bo I t

j
t
Lo

Standards like Zigbee used offset quadrature phase shift keying,

with a constellation as shown below. With 4 points we can send 2
bits per symbol.

jo pa
I
A É Fret B

q A
R
LO pi

D
ti
Be it
LEE
In ZigBee, or 802.15.4 as the standard is called, the phase changes I
is actually done with a constant envelope.
p
The nice thing about constant envelope is that the radio transmitter
can be simple. We don’t need to change the amplitude. If we
Q
have a PLL as a local oscillator, where we can change the phase
(or frequency), then we only need a power amplifier before the
antenna.
LO
 262 16 Low Power Radio

jo pa
I
A É Fret B

q jo
For phase and amplitude modulation, or complex transmitters, we
need a way to change the amplitude and Aphase. What a shocker.
pa
There are two ways to do that. A polar architecture where phase
R
I pi
É Fret B LO
change is done in the PLL, and amplitude in the power amplifier.

ti
Be it
LEE A
q
R
I
jo
LO
pa
pi
I
A É Fret B
pa
ti
Be it
LEE Q
q A
Or a Cartesian architecture where we make the in-phase compo-
R
I
digital to analog converters, pi
nent, and quadrature-phase components in digital, then use two
LOLO and a set of complex mixers to encode
onto the carrier. The power amplifier would not need to change

D
ti
Be it
LEE the amplitude, but it does need to be linear. pa
Q
I
pa
Q LO

LO

We can continue to add constellation points around the unit circle.

Below we can see 8-PSK, where we can send 3-bits per symbol.
Assuming we could shift position between the constellation points
at a fixed rate, i.e 1 mega symbols per second. With 1-bit per symbol
we’d get 1 Mbps. With 3-bits per symbol we’d get 3 Mbps.

We could add 16 points, 32 points and so on to the unit circle,

however, there is always noise in the transmitter, which will create
a cloud around each constellation point, and it’s harder and harder
to distinguish the points from each other.
 16.4 Decisions 263

IR

Bluetooth Classic uses 𝜋/4-DQPSK and 8DPSK.

DPSK means differential phase shift keying. Think about DPSK

like this. In the QPSK diagram above the symbols (00,01,10,11) are
determined by the constellation point 1 + 𝑗 , 1 − 𝑗 and so on. What
would happen if the constellation rotated slowly? Would 1 + 𝑗 turn
into 1 − 𝑗 at some point? That might screw up our decoding if
the received constellation point was at 1 + 0 𝑗 , we would not know
what it was.

If we encoded the symbols as a change in phase instead (differen-

tial), then it would not matter if the constellation rotated slowly. A
change from 1 + 𝑗 to 1 − 𝑗 would still be 90 degrees.

Why would the constellation rotate you ask? Imagine the trans-
mitter transmits at 2 400 000 000 Hz. How does our reciever
generate the same frequency? We need a reference and a PLL.
The crystal-oscillator reference has a variation of +-50 ppm, so
2.4 𝑒 9 × 50/1 𝑒 6 = 120 kHz.

Assume our receiver local oscillator was at 2 400 120 000 Hz. The
transmitter sends 2 400 000 000 Hz + modulation. At the reciever we
multiply with our local oscillator, and if you remember your math,
multiplication of two sine creates a sum and a difference between
the two frequencies. As such, the low frequency part (the difference
between the frequencies) would be 120 kHz + modulation. As a
result, our constellation would rotate 120 000 times per second.
Assuming a symbol rate of 1MS/s our constellation would rotate
roughly 1/10 of the way each symbol.

In DPSK the rotation is not that important. In PSK we have to

264 16 Low Power Radio

measure the carrier offset, and continuously de-rotate the constel-

lation.

Most radios will de-rotate somewhat based on the preamble, for

example in Bluetooth Low Energy there is an initial 10101010
sequence that we can use to estimate the offset between TX and
RX carriers, or the frequency offset.

The 𝜋/4 part of 𝜋/4 − 𝐷𝑄𝑃𝑆𝐾 just means we actively rotate

the constellation 45 degrees every symbol, as a consequence, the
amplitude never goes through the origin. In the transmitter circuit,
it’s difficult to turn the carrier off, so we try to avoid the zero point
in the constellation.

I don’t think 16PSK is that common, at 4-bits per symbol it’s

common to switch to Quadrature Amplitude Modulation (QAM),
as shown below. The goal of QAM is to maximize the distance
between each symbol. The challenge with QAM is the amplitude
modulation. The modulation scheme is sensitive to variations in
the transmitter amplitude. As such, more complex circuits than
8PSK could be necessary.

If you wanted to research “new fancy modulation schemes” I’d

think about Sphere packing.
 16.4 Decisions 265

Irx

Ei
16.4.3 Single carrier, or multi carrier? a

Assume we wanted to send 1024 Mbps over the air. We could

choose a bandwidth of aAD about free
PLL 1 GHz with 1-bit per symbol, or
have a bandwidth of 1 MHz if we sent 1024 QAM at 1MS/s. Both
cases would look like the figure below.

In both cases we get problems with the physical communication

channel, the change in phase and amplitude affect what is received.
For a 1 GHz bandwidth at 2.4 GHz carrier we’d have problems with
the phase. At 1024 QAM we’d have problems with the amplitude.

And I I Ault
Q
TX RX a S
9m glt

Back in 1966 Orthogonal frequency division multiplexing was

introduced to deal with the communication channel. In OFDM we
modulate a number of sub-carriers in the frequency space with
our witta
wanted modulation scheme (BPSK, PSK, QAM), [Link]
Af e I I A f then do an
inverse fourier transform to get the time domain signal, mix on
IFFT and
to the carrier, TX RX a FFT
transmit. At the reciever we take an FFT and
do demodulation Q in the frequency space. See example in figure
below. outta
[Link]
wt94 actei
266 16 Low Power Radio And I I Ault
Q
TX RX a S
9m glt
The name “multiple carriers” is a bit misleading. Although there
are multiple carriers on the left and right side of the figure, there
is normally still just one carrier in the TX/RX.

witta [Link]
Af e I I Af

IFFT TX RX a FFT
Q
outta
[Link]
wt94 actei

There are more details in OFDM than the simple statement above,
but the details are just to fix challenges, such as “How do I recover
the symbol timing? How do I correct for frequency offset? How do
I ensure that my time domain signal terminates correctly for every
FFT chunk”

The genius with OFDM is that we can pick a few of the sub-carriers
to be pilot tones that carry no new information. If we knew exactly
what was sent in phase and amplitude, then we could measure the
phase and amplitude change due to the physical communication
channel, and we could correct the frequency space before we tried
to de-modulate.

It’s possible to do the same with single carrier modulation also.

Imagine we made a 128-QAM modulation on a single carrier. As
long as we constructed the time domain signal correctly (cyclic
prefix to make the FFT work nicely, some preamble to measure the
communication channel, then we could take an FFT at the reciever,
correct the phase and amplitude, do an IFFT and demodulate the
time-domain signal as normal.

In radio design there are so many choices it’s easy to get lost.

16.4.4 Use a Software Defined Radio

For our mouse, what radio scheme should we choose? One common
instances of “how to make a choice” in industry is “Delay the choice
as long as possible so your sure the choice is right”.

Maybe the best would be to use a software defined radio reciever?

Something like the picture below, an antenna, low noise amplifier,
and a analog-to-digital converter. That way we could support any
transmitter. Fantastic idea, right?
 16.5 Bluetooth 267

LNA ADC

Well, lets check if it’s a good idea. We know we’ll use 2.4 GHz, so
we need about 2.5 GHz bandwidth, at least. We know we want
good range, so maybe 100 dB dynamic range. In analog to digital
converter design there are figure of merits, so we can actually
compute a rough power consumption for such an ADC.

ADC FOM
𝑃
=
2𝐵𝑊 2𝑛

State of the art FOM

≈ 5 fJ/step

𝐵𝑊 = 2.5 GHz

𝐷𝑅 = 100 dB = (96 − 1.76)/6.02 ≈ 16 bit

𝑃 = 5 fF × 5 GHz × 216 = 1.6 W

At 1.6 W our mouse would only last for 2 hours. That’s too short.
It will never be a low power idea to convert the full 2.5 GHz
bandwidth to digital, we need some bandwidth selectivity in the
receive chain.

16.5 Bluetooth

Bluetooth was made to be a “simple” standard and was introduced

in 1998. The standard has continued to develop, with Low Energy
introduced in 2010. The latest planned changes can be seen at
Specifications in Development.
268 16 Low Power Radio

16.5.1 Bluetooth Basic Rate/Extended Data rate

▶ 2.400 GHz to 2.4835 GHz

▶ 1 MHz channel spacing
▶ 78 Channels
▶ Up to 20 dBm
▶ Minimum -70 dBm sensitivity (1 Mbps)
▶ 1 MHz GFSK (1 Mbps), pi/4-DQPSK (2 Mbps), 8DPSK (3
Mbps)

You’ll find BR/EDR in most audio equipment, cars and legacy

devices. For new devices (also audio), there is now a transition to
Bluetooth Low Energy.

16.5.2 Bluetooth Low Energy

▶ 2.400 GHz to 2.480 GHz

▶ 2 MHz channel spacing
▶ 40 Channels (3 primary advertising channels)
▶ Up to 20 dBm
▶ Minimum -70 dBm sensitivity (1 Mbps)
▶ 1 MHz GFSK (1 Mbps, 500 kbps, 125 kbps), 2 MHz GFSK (2
Mbps)

Below are the Bluetooth LE channels. The green are the advertiser
channels, the blue are the data channels, and the yellow is the WiFi
channels.

The advertiser channels have been intentionally placed where there

is space between the WiFi channels to decrease the probability of
collisions.

Any Bluetooth LE peripheral will advertise it’s presence, it will

wake up once in a while (every few hundred milliseconds, to
seconds) and transmit a short “I’m here” packet. After transmitting
it will wait a bit in receive to see if anyone responds.

A Bluetooth LE central will camp in receive on a advertiser channel

and look for these short messages from peripherals. If one is
observed, the Central may choose to respond.
 16.6 Algorithm to design state-of-the-art LE radio 269

Take any spectrum analyzer anywhere, and you’ll see traffic on

2402, 2426, and 2480 MHz.

In a connection a central and peripheral (the master/slave names

below have been removed from the spec, that was a fun update
to a 3500 page document) will have agreed on an interval to talk.
Every “connection interval” they will transmit and receive data.
The connection interval is tunable from 7.5 ms to seconds.

Bluetooth LE is the perfect standard for wireless mice.

png further information Building a Bluetooth application on nRF

Connect SDK

Bluetooth Specifications in Development

16.6 Algorithm to design state-of-the-art LE

radio

▶ Find most recent digest from International Solid State Circuit

Conference (ISSCC)
▶ Find Bluetooth low energy papers
▶ Pick the best blocks from each paper

A typical Bluetooth radio may look something like the picture

below. There would be a single antenna for both RX and Tx. There
270 16 Low Power Radio

will be some way to combine the transmit and receive path in a

match, or balun.

The receive chain would have a LNA, mixer, anti-alias filter and
analog-to-digital converters. It’s likely that the receive path would
be complex (in-phase and quadrature phase) after mixer.

There would be a local oscillator (all-digital phase-locked-loop)

to provide the frequency to the mixers and transmit path, which
could be either polar or Cartesian.

AAF ADC
IRX
MIX
LNA
AAF ADC QRX

I
MATCH
FREE
ADPLL
ITX
TX QTX

In the typical radio we’ll need the blocks below. I’ve added a column
for how many people I would want if I was to lead development
of a new radio.

Complexity (nr
Blocks Key parameter Architecture people)
Antenna Gain, impedance lambda/4 <1
RF match loss, input impedance PI-match <1
Low noise amp NF, current, linearity LNTA 1
Mixer NF, current, linearity Passive 1
Anti-alias filter NF, current, linearity Active-RC 1
ADC Sample rate, dynamic range, NS-SAR 1-2
linearity
PLL Phase noise, current AD-PLL 2-3
Baseband Eb/N0, gate count, current. SystemVerilog > 10

16.6.1 LNTA

The first thing that must happen in the radio is to amplify the noise
as early as possible. Any circuit has inherent noise, be it thermal-,
flicker-, burst-, or shot-noise. The earlier we can amplify the input
noise, the less contribution there will be from the radio circuits.

The challenges in the low noise amplifier is to provide the right

gain. If there is a strong input signal, then reduce the gain. If there
is a low input signal, then increase the gain.

One way to implement variable gain is to reconfigure the LNA. For

an example, see
 16.6 Algorithm to design state-of-the-art LE radio 271

30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm

Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset
in 22nm FDSOI

A typical Low Noise Transconductance Amplifier is seen below.

It’s a combination of both a common source, and a common gate
amplifier. The current in the NMOS and PMOS is controlled by
Vgp and Vgn. Keep in mind that at RF frequencies the signals are
weak, so it’s easy to provide the DC for the LNA with a resistor to
a diode connected PMOS or NMOS.

In a LNA the input impedance must be matched to what is required

by the antenna/match in order to have maximum power transfer,
that’s the role of the inductors/capacitors.

Vge Mixer
puttin un

16.6.2 MIXER

In the mixer we multiply the input signal with our local oscillator.
Most often a complex mixer is used. There is nothing complex
about complex signal processing, just read

Complex signal processing is not complex

In order to reduce power, it’s most common with a passive mixer

as shown below. A passive mixer is just MOS that we turn on and
off with 25% duty-cycle. See example in

A 370uW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver

with >63dB Adjacent Channel Rejection at >2 Channels Offset in
22nm FDSOI
272 16 Low Power Radio

I
m
Is

Q2
Vn
I

LNA Un

a
Q2
un
Q

To generate the quadrature and in-phase clock signals, which must

be 90 degrees phase offset, it’s common to generate twice the
frequency in the local oscillator (4.8 GHz), and then divide down
to 4 2.4 GHz clock signals.

If the LO is the same as the carrier, then the modulation signal will
be at DC, often called direct conversion.

The challenge at DC is that there is flicker noise, offset, and burst

noise. The modulation type, however, can impact whether low
frequency noise is an issue. In OFDM we can choose to skip
the sub-carriers around 0 Hz, and direct conversion works well.
An advantage with direct conversion is that there is no “image
frequency” and we can use the full complex bandwidth.

For FSK and direct conversion the low frequency noise can cause
issues, as such, it’s common to offset the LO from the transmitted
signal, for example 4 MHz offset. The low frequency noise problem
disappears, however, we now have a challenge with the image
frequency (-4 MHz) that must be rejected, and we need an increased
bandwidth.

There is no “one correct choice”, there are trade-offs that both ways.
KISS (Keep It Simple Stupid) is one of my guiding principles when
working on radio architecture.

These days most de-modulation happens in digital, and we need

to convert the analog signal to digital, but first AAF.
 16.6 Algorithm to design state-of-the-art LE radio 273

16.6.3 AAF

The anti alias filter rejects frequencies that can fold into the band
of interest due to sampling. A simple active-RC filters is often good
enough.

We often need gain in the AAF, as the LNA does not have sufficient
gain for the weakest signals. -100 dBm in 50 ohm is 6.2 nV RMS,
while input range of an ADC may be 1 V. Assume we place
the lowest input signal at 0.1 V, so we need a voltage gain of
20 log(0.1/6.2 𝑒 − 9) = 76dB in the reciever.

Gy
G Gs
or
Ca
L
CB
Vi G
63
Vo

16.6.4 ADC

Aaah, ADCs, an IP close to my heart. I did my Ph.d and Post-Doc

on ADCs, and the Ph.D students I’ve co-supervised have worked
on ADCs.

At NTNU there have been multiple students through the years that
have made world-class ADCs, and there’s still students at NTNU
working on state-of-the-art ADCs.

These days, a good option is a SAR, or a Noise-Shaped SAR.

If I were to pick, I’d make something like A 68 dB SNDR Compiled

Noise-Shaping SAR ADC With On-Chip CDAC Calibration as
shown in the figure below.

Or if I did not need high resolution, I’d choose my trusty A

Compiled 9-bit 20-MS/s 3.5-fJ/[Link] SAR ADC in 28-nm
FDSOI for Bluetooth Low Energy Receivers.
274 16 Low Power Radio

The main selling point of that ADC was that it’s compiled from a
JSON file, a SPICE file and a technology file into a DRC/LVS clean
layout.

I also included a few circuit improvements. The bottom plate of

the SAR capacitor is in the clock loop for the comparator (DN0,
DP1 below), as such, the delay of the comparator automatically
adjusts with capacitance corner, so it’s more robust over corners

CK D8 CK D7 CK D6 CK D5 CK D4 CK D3 CK D2 CK D1 CK D0
DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N

CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO
LOGIC[8] LOGIC[7] LOGIC[6] LOGIC[5] LOGIC[4] LOGIC[3] LOGIC[2] LOGIC[1] LOGIC[0] CK
CK EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO
DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 X1

X2
CK
CK CM P
VP +
P

VN −
Bootstrapped 28 · CU N IT 27 · CU N IT 26 · CU N IT 25 · CU N IT 24 · CU N IT 23 · CU N IT 22 · CU N IT 21 · CU N IT 20 · CU N IT N
NMOS switches
(a)

VDD VDD VDD VDD

VREF VREF VDD VDD

CK MP 0 MP 3 CK MP 4 CK MP 5

MP 6 MP 7
DP 0 DN 0 DN 1 DP 1
N MP 2 EI MN 6 EI MN 9
A

EI MN 0 P MP 1 MN 5 MN 8
EO B

P MN 1 N MN 2 MN 3 P MN 4 N MN 7 CK MN 10
CI CO

(b) (c) (d)

The compiled nature also made it possible to quickly change

the transistor technology. Below is a picture with 180 nm FDSOI
transistors on the left, and 28 nm FDSOI transistors on the right.

I detest doing anything twice, so I love the fact that I never have to
re-draw that ADC again. I just fix the technology file (and maybe
some tweaks to the other files), and I have a completed ADC.

Comparator

Logic
106µm

CDAC
80µm

Switch

39µm
40µm
(a) (b)
 16.6 Algorithm to design state-of-the-art LE radio 275

16.6.5 AD-PLL

The phase locked loop is the heart of the radio, and it’s probably
the most difficult part to make. Depends a bit on technology, but
these days, All Digital PLLs are cool. Start by reading Razavi’s PLL
book.

You can spend your life on PLLs.

food

ED N

fin to
yes
fmod

AD-PLL with Bang-Bang phase detector for steady-state

Freq. offset estimator Cal
n
z -n CLK estimator delay cal?

- ferror
DCO Cal. Engine
lf_state fine mode coarse

+
CLK Loop Filter
1 coarse
enable set_state
Sync. Phase Error
0 a0 + + DCO OUT
z -1 0
Counter Logic 1 + +
a1
BB-PD z -1
SS
D Q Detect
Q
enable

16.6.6 Baseband

Once the signal has been converted to digital, then the de-
modulation, and signal fixing start. That’s for another course, but
there are interesting challenges.

Baseband block Why

Mixer? If we’re using low intermediate frequency
to avoid DC offset problems and flicker
noise
Channel filters? If the AAF is insufficient for adjacent
channel
Power detection To be able to control the gain of the radio
Phase extraction Assuming we’re using FSK
Timing recovery Figure out when to slice the symbol
Bit detection single slice, multi-bit slice, correlators etc
Address detection Is the packet for us?
Header detection What does the packet contain
CRC Does the packet have bit errors
Payload de-crypt Most links are encrypted by AES
Memory access Payload need to be stored until CPU can do
something
276 16 Low Power Radio

16.7 What do we really want, in the end?

The reciever part can be summed up in one equation for the

sensitivity. The noise in a certain bandwidth. The Noise Figure
of the analog reciever. The Energy per bit over Noise of the de-
modulator.

𝑃𝑅𝑋𝑠𝑒𝑛𝑠 = −174 𝑑𝐵𝑚 + 10 × 𝑙𝑜 𝑔 10(𝐷𝑅) + 𝑁 𝐹 + 𝐸𝑏/𝑁 0

for example, for nRF5340

𝑃𝑅𝑋𝑠𝑒𝑛𝑠 + 174 − 60 = 𝑁 𝐹 + 𝐸𝑏/𝑁 0 = 17𝑑𝐵

In the block diagram of the device the radio might be a small box,
and the person using the radio might not realize how complex the
radio actually is.

I hope you understand now that it’s actually complicated.

 16.8 Want to learn more? 277

16.8 Want to learn more?

A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm

Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in
22nm FDSOI, M. Tamura, Sony Semiconductor Solutions, Atsugi,
Japan, 30.5, ISSCC 2020
A 370uW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver
with >63dB Adjacent Channel Rejection at >2 Channels Offset in
22nm FDSOI, B. J. Thijssen, University of Twente, Enschede, The
Netherlands
A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip
CDAC Calibration, H. Garvik, C. Wulff, T. Ytterdal
A Compiled 9-bit 20-MS/s 3.5-fJ/[Link] SAR ADC in 28-nm
FDSOI for Bluetooth Low Energy Recievers, C. Wulff, T. Ytterdal
Cole Nielsen, [Link]
ns
“Python Framework for Design and Simulation of Integer-N AD-
PLLs”, Cole Nielsen, [Link]
t/blob/master/[Link]
Design of CMOS Phase-Locked Loops, Behzad Razavi, University
of California, Los Angeles
 Energy Sources 17
17.1 Thermoelectric . . . 281
17.1.1 Radioisotope Thermo-
Integrated circuits are wasteful of energy. Digital circuits charge electric generator . . 285
17.1.2 Thermoelectric
transistor gates to change states, and when discharged, the charges
generators . . . . . . 285
are dumped to ground. In analog circuits the transconductance
17.2 Photovoltaic . . . . . 286
requires a DC current, a continuous flow of charges from positive
17.3 Piezoelectric . . . . . 289
supply to ground.
17.4 Electromagnetic . . 291
17.4.1 “Near field” harvest-
ing . . . . . . . . . . . 291
17.4.2 Ambient RF Harvest-
Integrated circuits are incredibly useful though. Life without would
ing . . . . . . . . . . . 292
be different.
17.5 Triboelectric genera-
tor . . . . . . . . . . . 293
17.6 Comparison . . . . . 296
A continuous effort from engineers like me have reduced the 17.7 Want to learn more? 297
power consumption of both digital and analog circuits by order of
magnitudes since the invention of the transistor 75 years ago.

One of the first commercial ADCs, the DATRAC on page 24, was
a 11-bit 50 kSps that consumed 500 W. That’s Walden figure of
merit of 4 𝜇J/[Link]. Today’s state-of-the-art ADCs in the same
sampling range have a Walden figure of merit of 0.6 fJ/[Link].

4 𝜇 / 0.6 f = 8.1e9, a difference in power consumption of almost 10

billion times !!!

Improvements to power consumption have become harder and

harder, but I believe there is still far to go before we cannot reduce
power consumption any more.

Towards a Green and Self-Powered Internet of Things Using Piezo-

electric Energy Harvesting [1] has a nice overview of power con-
sumption of technologies, seen in the next figures below.

In the context of energy harvesting, there is energy in electromag-

netic fields, temperature, and mechanical stress, and there are ways
to translate between them the energy forms.
280 17 Energy Sources

Below we can see a figure of the potential energy that can be

harvested per volume, and the type power consumption of tech-
nologies [1].

As devices approach average power consumption of 𝜇𝑊 it becomes

possible to harvest the energy from the environment, and do away
with the battery.

For wireless standards, there are some that can be run on en-
ergy harvesting. Below is an overview from [1]. Many of us will
have a NFC card in our pocket for payment, or entry to build-
ings. NFC card has a integrated circuit that is powered from the
electromagnetic field from the NFC reader.

Other standards, like Bluetooth, WiFi, LTE are harder to run battery
less, because the energy requirement above 1 mW.
 17.1 Thermoelectric 281

Technologies like Bluetooth LE, however, can approach < 10 𝜇W

for some applications, although the burst power may still be 10
mW to 100 mW. As such, although the average power is low, the
energy harvesting cannot support peak loads and a charge storage
device is required (battery, super-capacitor, large capacitor).

I’d like to give you an introduction to the possible ways of harvest-

ing energy. I know of five methods: - thermoelectric - photovoltaic
- piezoelectric - electromagnetic - triboelectric

17.1 Thermoelectric

Apply heat to one end of a metal wire, what happens to the free
electrons? As we heat the material we must increase the energy
of the free electrons at the hot end of the wire. The atoms wiggle
more, and when the free electrons scatter off the atomic structure
there should be an exchange of energy. Think of the electrons at
the hot side as high energy electrons, while on the cold side there
are low energy electrons, I think.

There will be diffusion current of electrons in both directions in

the material, however, if the mobility of electrons in the material is
dependent on the energy, then we would get a difference in current
of low energy electrons and high energy electrons. A difference in
current would lead to a charge difference at the hot end and cold
end, which would give a difference in voltage.

Take a copper wire, bend it in half, heat the end with the loop, and
measure the voltage at the cold end. Would we measure a voltage
difference?

NO, there would not be a voltage difference between the two ends
of the wire. The voltage on the loop side would be different, but on
the cold side, where we have the ends, there would be no voltage
difference.

Gauss law tell us that inside a conductor there cannot be a static

field without a current. As such, if there was a voltage difference
282 17 Energy Sources

between the cold ends, it would quickly dissipated, and no DC

current would flow.

The voltage difference in the material between the hot and cold
end will create currents, but we can’t use them if we only have one
type of material.

Imagine we have Iron and copper wires, as shown below, and we

heat one end. In that case, we can draw current between the cold
ends.

The voltage difference at the hot and cold end is described by the

Seebeck coefficient

Imagine two parallel wires with different Seebeck coefficients, one

of copper (6.5 𝜇𝑉/𝐾 ) and one of iron (19 𝜇/𝐾 ). We connect them
at the hot end. The voltage difference between hot and cold would
be higher in the iron, than in the copper. At the cold end, we would
now measure a difference in voltage between the wires!

In silicon, the Seebeck coefficient can be modified through doping.

A model of Seebeck coefficient is shown below. The value of the
Seebeck coefficient depends on the location of the Fermi level in
relation to the Conduction band or the V valence band.
 17.1 Thermoelectric 283

In the picture below we have a silicon (the cyan and yellow col-
ors).

Assume we dope with acceptors (yellow, p-type), that shifts the

Fermi level closer to the Valence band (𝐸𝑉 ), and the dominant
current transport will be by holes, maybe we get 1 mV/K from the
picture above.

For the material doped with donors (cyan, n-type) the Fermi level
is shifted towards the Conduction band (𝐸𝐶 ), and the dominant
charge transport is by electrons, maybe we get -1 mV/K from the
picture above.
284 17 Energy Sources

Assume we have a temperature difference of 50 degrees, then

maybe we could get a voltage difference at the cold end of 100 mV.
That’s a low voltage, but is possible to use.

The process can be run in reverse. In the picture below we force a

current through the material, we heat one end, and cool the other.
Maybe you’ve heard of Peltier elements.
 17.1 Thermoelectric 285

17.1.1 Radioisotope Thermoelectric generator

Maybe you’ve heard of a nuclear battery. Sounds fancy, right? Must

be complicated, right?

Not really, take some radioactive material, which generates heat,

stick a thermoelectric generator to the hot side, make sure you can
cool the cold side, and we have a nuclear battery.

Nuclear batteries are “simple”, and ultra reliable. There’s not

really a chemical reaction. The nucleus of the radioactive material
degrades, but not fast. In the thermoelectric generator, there are
no moving parts.

In a normal battery there is a chemical reaction that happens when

we pull a current. Atoms move around. Eventually the chemical
battery will change and degrade.

Nuclear batteries were used in Voyager, and they still work to this
day. The nuclear battery is the round thing underneath Voyager
in the picture below. The radioisotopes provide the heat, space
provides the cold, and voila, 470 W to run the electronics.

17.1.2 Thermoelectric generators

Assume a we wanted to drive a watch from a thermoelectric

generator (TEG). The skin temperature is maybe 33 degrees Celsius,
while the ambient temperature is maybe 23 degrees Celsius on
average.

From the model of a thermoelectric generator below we’d get a

voltage of 10 mV to 500 mV, too low for most integrated circuits.

In order to drive an integrated circuit we’d need to boost the voltage

to maybe 1.8 V.
286 17 Energy Sources

The main challenge with thermoelectric generators is to provide a

cold-boot function where the energy harvester starts up at a low
voltage.

In silicon, it is tricky to make anything work below some thermal

voltages (kT/q). We at least need about 3 – 4 thermal voltages to
make anything function.

The key enabler for an efficient, low temperature differential, energy

harvester is an oscillator that works at low voltage (i.e 75 mV). If
we have a clock, then we can boost with capacitors

In A 3.5-mV Input Single-Inductor Self-Starting Boost Converter

With Loss-Aware MPPT for Efficient Autonomous Body-Heat En-
ergy Harvesting they use a combination of both switched capacitor
and switched inductor boost.

Ll or

1 50MY

17.2 Photovoltaic

In silicon, photons can knock out electron/hole pairs. If we have

a PN junction, then it’s possible to separate the electron/holes
before they recombine as shown in figure below.

An electron/hole pair knocked out in the depletion region (1) will

separate due to the built-in field. The hole will go to P and the
electron to N. This increases the voltage VD across the diode.

A similar effect will occur if the electron/hole pair is knocked out

in the P region (2). Although the P region has an abundance of
holes, the electron will not recombine immediately. If the electron
diffuses close to the depletion region, then it will be swept across
to the N side, and further increase VD.

Pr
 Ll or 17.2 Photovoltaic 287

On the N-side the same minority carrier effect would further

increase the voltage (3).

50MY B A

P
minorities
imminent 3
up t
Va P
A circuit model of a Photodiode can be seen in figure below, where

Vb P
it is assumed that a single photodiode is used. It is possible to stack
photodiodes to get a higher output voltage.
Vb P

man

p
Pr
As the load current is increased, the voltage VD will drop. As the
photo current is increased, the voltage VD will increase. As such,
there is an optimum current load where there is a balance between
the photocurrent, the voltage VD and the load current.

 𝑉𝐷

𝐼 𝐷 = 𝐼𝑆 𝑒 𝑉𝑇
−1
288 17 Energy Sources

𝐼𝐷 = 𝐼𝑃 ℎ𝑜𝑡𝑜 − 𝐼𝐿𝑜𝑎𝑑

𝐼𝑃 ℎ𝑜𝑡𝑜 − 𝐼𝐿𝑜𝑎𝑑
 
𝑉𝐷 = 𝑉𝑇 𝑙𝑛 +1
𝐼𝑆

𝑃𝐿𝑜𝑎𝑑 = 𝑉𝐷 𝐼𝐿𝑜𝑎𝑑

Below is a model of the power in the load as a function of diode

voltage

#!/usr/bin/env python3
import numpy as np
import [Link] as plt

m = 1e-3
i_load = [Link](1e-5,1e-3,200)

i_s = 1e-12 # saturation current

i_ph = 1e-3 # Photocurrent

V_T = 1.38e-23*300/1.6e-19 #Thermal voltage

V_D = V_T*[Link]((i_ph - i_load)/(i_s) + 1)

P_load = V_D*i_load

[Link](2,1,1)
[Link](i_load/m,V_D)
[Link]("Diode voltage [mA]")
[Link]()
[Link](2,1,2)
[Link](i_load/m,P_load/m)
[Link]("Current load [mA]")
[Link]("Power Load [mW]")
[Link]()
[Link]("[Link]")
[Link]()

From the plot below we can see that to optimize the power we
could extract from the photovoltaic cell we’d want to have a current
of 0.9 mA in the model above.
 17.3 Piezoelectric 289

0.5
Diode voltage [V]

0.4
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0
0.4
Power Load [mW]

0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0
Current load [mA]

Most photovoltaic energy harvesting circuits will include a max-

imum power point tracker as the optimum changes with light
conditions.

In A Reconfigurable Capacitive Power Converter With Capacitance

Redistribution for Indoor Light-Powered Batteryless Internet-of-
Things Devices they include a maximum power point tracker and
a reconfigurable charge pump to optimize efficiency.

17.3 Piezoelectric

I’m not sure I understand the piezoelectric effect, but I think it goes
something like this.

Consider a crystal made of a combination of elements, for example

Gallium Nitride. In GaN it’s possible to get a polarization of the unit
cell, with a more negative charge on one side, and a positive charge
on the other side. The polarization comes from an asymmetry in
the electron and nucleus distribution within the material.

In a polycrystaline substance the polarization domains will usually

be random, and no electric field will observable. The polarization
domains can be aligned by heating the material and applying a
electric field. Now all the small electric fields point in the same
direction.

From Gausses law we know that the electric field through a surface
is determined by the volume integral of the charges inside.

∮ ∭
1
E · 𝑑S = 𝜌 · 𝑑𝑉
𝜕Ω 𝜖 0 𝑉
290 17 Energy Sources

Although there is a net zero charge inside the material, there is an

uneven distribution of charges, as such, some of the field lines will
cross through the surface.

Assume we have a polycrystaline GaN material with polarized

domains. If we measure the voltage across the material we will
read 0 V. Even though the domains are polarized, and we should
observe an external electric field, the free charges in the material
will redistribute if there is a field inside, such that there is no
current flowing, and thus no external field.

If we apply stress, however, all the domains inside the material

will shift. Now the free charges do not exactly cancel the electric
field in the material, the free charges are in the wrong place. If we
have a material with low conductivity, then it will take time for the
free charges to redistribute. As such, for a while, we can measure
an voltage across the material.

Assuming the above explanation is true, then there should not be

piezoelectric materials with high conductivity, and indeed, most
piezoelectric materials have resistance of 1012 to 1014 Ohm.

Vibrations on a piezoelectric material will result in a AC voltage

across the surface, which we can harvest.

A model of a piezoelectric transducer can be seen below.

The voltage on the transducer can be on the order of a few volts,

but the current is usually low (nA – µA). The key challenge is to
rectify the AC signal into a DC signal. It is common to use tricks to
reduce the energy waste due to the rectifier.

An example of piezoelectric energy harvester can be found in A

Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric
Energy Harvesting
 17.4 Electromagnetic 291

17.4 Electromagnetic

17.4.1 “Near field” harvesting

Near Field Communication (NFC) operates at close physical dis-

tances

Reactive near field or inductive near field

𝜆
Inductive <
2𝜋

Within the inductive near field the antenna’s can “feel” each other.
The NFC reader inside the card reader can “feel” the antenna of
the NFC tag. When the tag get’s close it will load down the NFC
292 17 Energy Sources

reader by presenting a load impedance. As the circuit inside the

tag is powered, it can change the impedance of it’s antenna, which
is sensed by the reader, and thus the reader can get data from the
tag. The tag could lock in on the 13.56 MHz frequency and decode
both amplitude and phase modulation from the reader.

Since the NFC or Qi system operates at close distances, then the

coupling factor between antenna’s, or really, inductors, can be
decent, and it’s possible to achieve efficiencies of maybe 70 %.

At Bluetooth frequencies, as can be seen below, it does not really

make sense to couple inductors, as they need to be within 2 cm to be
in the inductive near field. The inductive near field is a significant
problem for the coupling between inductors on chip, but I don’t
think I would use it to transfer power.

Standard Frequency [MHz] Inductive [m]

AirFuel Resonant 6.78 7.03
NFC 13.56 3.52
Qi 0.205 232
Bluetooth 2400 0.02

17.4.2 Ambient RF Harvesting

Extremely inefficient idea, but may find special use-cases at short-

distance.

Will get better with beam-forming and directive antennas

There are companies that think RF harvesting is a good idea.

AirFuel RF

I think that ambient RF harvesting should tingle your science spidy

senses.

Let’s consider the power transmitted in wireless standards. Your

cellphone may transmit 30 dBm, your WiFi router maybe 20 dBm,
and your Bluetooth LE device 10 dBm.

In case those numbers don’t mean anything to you, below is a

conversion to watts.

dBm W
30 1
0 1m
-30 1u
-60 1n
-90 1p

Now ask your self the question “What’s the power at a certain
distance?”. It’s easier to flip the question, and use Friis to calculate
the distance.
 17.5 Triboelectric generator 293

Assume
𝑃𝑇𝑋
= 1 W (30 dBm) and
𝑃𝑅𝑋
= 10 uW (-20 dBm)

then

 
𝑃𝑇𝑋 −𝑃𝑅𝑋 +20 𝑙𝑜 𝑔10 𝑐
4𝜋 𝑓
𝐷 = 10 20

In the table below we can see the distance is not that far!

20 𝑙𝑜 𝑔10 𝑐/4𝜋 𝑓 [dB]

Freq D [m]
915M -31.7 8.2
2.45G -40.2 3.1
5.80G -47.7 1.3

I believe ambient RF is a stupid idea.

Assuming an antenna that transmits equally in all direction, then

the loss on the first meter is 40 dB at 2.4 GHz. If I transmitted
1 W, there would only be 100 µW available at 1 meter. That’s an
efficiency of 0.01 %.

Just fundamentally stupid. Stupid, I tell you!!!

Stupidity in engineering really annoys me, especially when people

don’t understand how stupid ideas are.

17.5 Triboelectric generator

Although static electricity is an old phenomenon, it is only re-

cently that triboelectric nanogenerators have been used to harvest
energy.

An overview can be seen in Current progress on power manage-

ment systems for triboelectric nanogenerators.

A model of a triboelectric generator can be seen in below. Although

the current is low (nA) the voltage can be high, tens to hundreds
of volts.

The key circuit challenge is the rectifier, and the high voltage output
of the triboelectric generator.

Take a look in A Fully Energy-Autonomous Temperature-to-Time

Converter Powered by a Triboelectric Energy Harvester for Biomed-
ical Applications for more details.
294 17 Energy Sources

Below is a custom triboelectric material that converts friction into

a sparse electric field.

The key idea of the triboelectric circuit below is to rectify the sparse
voltage pulses and store the charge on a capacitor. Once the voltage
is high enough, then a temperature sensor is started.
 17.5 Triboelectric generator 295

Below is some more details on the operation of the harvesting

circuit, and the temperature sensor. Notice how the temperature
sensor part of the circuit (PTAT bandgap, capacitor and compara-
tor) produce a pulse width modulated signal that depends on
temperature.

Also notice the “VDD_ext” in the figure. That means the system is
not fully harvested. The paper is a prime example on how we in
academia can ignore key portions of a system. They’ve focused on
the harvesting part, and making the temperature dependent pulse
width modulated signal. Maybe they’ve completely ignored how
the data is transmitted from the system to where it would be used,
and that’s OK.

It’s academia’s job to prove that something could be possible. It’s

industry’s job to make some that could be possible actually work.
296 17 Energy Sources

17.6 Comparison

Imagine you’re a engineer in a company that makes integrated

circuits. Your CEO comes to you and says “You need to make
a power management IC that harvest energy and works with
everything”.

Hopefully, your response would now be “That’s a stupid idea, any

energy harvester circuit must be made specifically for the energy
source”.

Thermoelectric and photovoltaic provide low DC voltage. Piezo-

electric and Triboelectric provide an AC voltage. Ambient RF is
stupid.

For a “energy harvesting circuit” you must also know the applica-
tion (wrist watch, or wall switch) to know what energy source is
available.

Below is a table that show’s a comparison in the power that can be

extracted.

The power levels below are too low for the peak power consumption
of integrated circuits, so most applications must include a charge
storage device, either a battery, or a capacitor.
 17.7 Want to learn more? 297

17.7 Want to learn more?

[1] Towards a Green and Self-Powered Internet of Things Using

Piezoelectric Energy Harvesting
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With
Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy
Harvesting
A Reconfigurable Capacitive Power Converter With Capacitance
Redistribution for Indoor Light-Powered Batteryless Internet- of-
Things Devices
A Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric
Energy Harvesting
Current progress on power management systems for triboelectric
nanogenerators
A Fully Energy-Autonomous Temperature-to-Time Converter Pow-
ered by a Triboelectric Energy Harvester for Biomedical Applica-
tions
 Analog SystemVerilog 18
18.1 Digital simulation . 300
Design of integrated circuits is split in two, analog design, and
18.2 Transient analog
digital design. simulation . . . . . . 303
18.3 Mixed signal simula-
Digital design is highly automated. The digital functions are coded tion . . . . . . . . . . 304
in SystemVerilog (yes, I know there are others, but don’t use those), 18.4 Analog SystemVer-
translated into a gate level netlist, and automatically generated ilog Example . . . . 306
layout. Not everything is push-button automation, but most is. 18.4.1 TinyTapeout TT06_-
SAR . . . . . . . . . . 306
Analog design, however, is manual work. We draw schematic, 18.4.2 SAR operation . . . . 306
simulation with a mathematical model of the real world, draw the 18.5 Want to learn more? 309
analog layout needed for the foundries to make the circuit, verify
that we drew the schematic and layout the same, extract parasitics,
simulate again, and in the end get a GDSII file.

When we mix analog and digital designs, we have two choices,

analog on top, or digital on top.

In analog on top we take the digital IP, and do the top level layout
by hand in analog tools.

In digital on top we include the analog IPs in the SystemVerilog,

and allow the digital tools to do the layout. The digital layout is
still orchestrated by people.

Which strategy is chosen depends on the complexity of the inte-

grated circuit. For medium to low level of complexity, analog on
top is fine. For high complexity ICs, then digital on top is the way
to go.

Below is a description of the open source digital-on-top flow. The

analog is included into GDSII at the OpenRoad stage of the flow.

The GDSII is not sufficient to integrate the analog IP. The digital
needs to know how the analog works, what capacitance is on every
digital input, the propagation delay for digital input to digital
outputs , the relation between digital outputs and clock inputs,
and the possible load on digital outputs.

The details on timing and capacitance is covered in a Liberty file.

The behavior, or function of the analog circuit must be described
in a SystemVerilog file.

But how do we describe an analog function in SystemVerilog?

SystemVerilog is simulated in an digital simulator.
300 18 Analog SystemVerilog

Idea

Analog Design
Xschem

Analog Model Analog Simulation

SystemVerilog ngspice

Digital Design Analog Layout

SystemVerilog Magic

Digital Simulation LVS

iverilog/vpp/verilator/gtkwave netgen

Parasitics
GDSII
Magic

RTL to GDSII
OpenLane

Tapeout

18.1 Digital simulation

Conceptually, the digital simulator is easy.

▶ The order of execution of events at the same time-step do

not matter
▶ The system is causal. Changes in the future do not affect
signals in the past or the now

In a digital simulator there will be an event queue, see below. From

start, set the current time step equals to the next time step. Check
if there are any events scheduled for the time step. Assume that
execution of events will add new time steps. Check if there is
another time step, and repeat.

Since the digital simulator only acts when something is supposed

to be done, they are inherently fast, and can handle complex
systems.
 18.1 Digital simulation 301

It’s a fun exercise to make a digital simulator. On my Ph.D I wanted

to model ADCs, and first I had a look at SystemC, however, I
disliked C++, so I made SystemDotNet

In SystemDotNet I implemented the event queue as a hash table,

so it ran a bit faster. See below.

[Link] Digital Simulators

There are both commercial an open source tools for digital simula-
tion. If you’ve never used a digital simulator, then I’d recommend
you start with iverilog. I’ve made some examples at dicex.

Commercial

▶ Cadence Excelium
302 18 Analog SystemVerilog

▶ Siemens Questa
▶ Synopsys VCS

Open Source - iverilog/vpp - Verilator - SystemDotNet

[Link] Counter

Below is an example of a counter in SystemVerilog. The code can

be found at counter_sv.

In the always_comb section we code what will become the combi-

natorial logic. In the always_ff section we code what will become
our registers.

module counter(
output logic [WIDTH-1:0] out,
input logic clk,
input logic reset
);

parameter WIDTH = 8;

logic [WIDTH-1:0] count;

always_comb begin
count = out + 1;
end

always_ff @(posedge clk or posedge reset) begin

if (reset)
out <= 0;
else
out <= count;
end

endmodule // counter

In the context of a digital simulator, we can think through how the

event queue will look.

When the clk or reset changes from zero to 1, then schedule an

event where if the reset is 1, then out will be zero in the next time
step. If reset is 0, then out will be count in the next time step.

In a time-step where out changes, then schedule an event

to setcounttoout‘ plus one. As such, each positive edge of the
clock at least 2 events must be scheduled in the register transfer
level (RTL) simulation.

For example:

Assume `clk, reset, out = 0`

Assume event with `clk = 1`

0: Set `out = count` in next event (1)

1: Set `count = out + 1` using

logic (may consume multiple events)

X: no further events
 18.2 Transient analog simulation 303

When we synthesis the code below into a netlist it’s a bit harder to
see how the events will be scheduled, but we can notice that clk
and reset are still inputs, and for example the clock is connected to
d-flip-flops. The image below is the synthesized netlist

It should feel intuitive that a gate-level netlist will take longer to

simulate than an RTL, there are more events.

18.2 Transient analog simulation

Analog simulation is different. There is no quantized time step.

How fast “things” happen in the circuit is entirely determined by
the time constants, change in voltage, and change in current in the
system.

It is possible to have a fixed time-step in analog simulation, for

example, we say that nothing is faster than 1 fs, so we pick that
as our time step. If we wanted to simulate 1 s, however, that’s at
least 1e15 events, and with 1 event per microsecond on a computer
it’s still a simulation time of 31 years. Not a viable solution for all
analog circuits.

Analog circuits are also non-linear, properties of resistors, capac-

itors, inductors, diodes may depend on the voltage or current
across, or in, the device. Solving for all the non-linear differential
equations is tricky.

An analog simulation engine must parse spice netlist, and setup

partial/ordinary differential equations for node matrix

The nodal matrix could look like the matrix below, 𝑖 are the currents,
𝑣 the voltages, and 𝐺 the conductances between nodes.

𝐺 𝐺 ··· 𝐺
1𝑁 𝑣 𝑖
© 11 12
ª© 1ª © 1ª
­ 𝐺21 𝐺22 · · · 𝐺2𝑁 ® ­ 𝑣2 ® ­ 𝑖2 ®
­ . .. .. .. ®® ­­ .. ®® = ­­ .. ®®
­ .. . . . ®­ . ® ­ . ®
­
« 𝐺 𝑁 1 𝐺 𝑁 2 · · · 𝐺 𝑁 𝑁 ¬ «𝑣 𝑁 ¬ « 𝑖 𝑁 ¬
304 18 Analog SystemVerilog

The simulator, and devices model the non-linear current/voltage

behavior between all nodes

as such, the 𝐺 ’s may be non-linear functions, and include the 𝑣 ’s

and 𝑖 ’s.

Transient analysis use numerical methods to compute time evolu-

tion

The time step is adjusted automatically, often by proprietary algo-

rithms, to trade accuracy and simulation speed.

The numerical methods can be forward/backward Euler, or the

others listed below.

▶ Euler
▶ Runge-Kutta
▶ Crank-Nicolson
▶ Gear

If you wish to learn more, I would recommend starting with the

original paper on analog transient analysis.

SPICE (Simulation Program with Integrated Circuit Emphasis)

published in 1973 by Nagel and Pederson

The original paper has spawned a multitude of commercial, free

and open source simulators, some are listed below.

If you have money, then buy Cadence Spectre. If you have no

money, then start with ngspice.

Commercial - Cadence Spectre - Siemens Eldo - Synopsys

HSPICE

Free - Aimspice - Analog Devices LTspice - xyce

Open Source - ngspice

18.3 Mixed signal simulation

It is possible to co-simulate both analog and digital functions. An

illustration is shown below.

The system will have two simulators, one analog, with transient
simulation and differential equation solver, and a digital, with
event queue.

Between the two simulators there would be analog-to-digital, and

digital-to-analog converters.

To orchestrate the time between simulators there must be a global

event and time-step control. Most often, the digital simulator will
end up waiting for the analog simulator.
 18.3 Mixed signal simulation 305

The challenge with mixed-mode simulation is that if the digital

circuit becomes to large, and the digital simulation must wait for
analog solver, then the simulation would take too long.

Most of the time, it’s stupid to try and simulate complex system-
on-chip with mixed-signal , full detail, simulation.

For IPs, like an ADC, co-simulation works well, and is the best way
to verify the digital and analog.

But if we can’t run mixed simulation, how do we verify analog

with digital?

Digital Analog
Simulator Simulator

Event Timester Control

306 18 Analog SystemVerilog

18.4 Analog SystemVerilog Example

18.4.1 TinyTapeout TT06_SAR

8-bit successive approximation register analog-to-digital-converter

# Signal interface
TIE_L1 uio_out[7:1]
uio_out[0] : When the output DFFs sample SAR output. If it does not come, then clock is too fast uio_out[7:0]
uo_out[7:0] : Digital output. Two's complement

R3

R2[7:1]
R=0.047

R=0.047
1 * 0.3 / 0.3

1 * 0.3 / 0.3
res_generic_m4

res_generic_m4
ui_in[0] : Enable ADC. Useful to measure current consumption TIE_L uio_in[7:0]
clk : Clock, ~ 4 MHz
TIE_L2 uio_oe[7:1]
uio_oe[7:0]

R4

R1[7:1]
R=0.047

R=0.047
1 * 0.3 / 0.3

1 * 0.3 / 0.3
VPWR

res_generic_m4

res_generic_m4
AVDD

AVDD
AVDD
uio_oe[0] DONE uio_out[0]
Y A Y

AVSS
x5 x4 x3
SUNTR_TAPCELLB_CV SUNTR_TIEH_CV SUNTR_BFX1_CV
VGND

AVSS

AVSS
VPWR Power decoupling
c0 C2[8:0]
uo_out[7:0]
cap_mim_m3_1
C=6.617e-13 18 / 18
c1 MF=1
ua[7:0] Output capture
clk
x2
x1
SAR core
ena ui_in[0]
CKS ua[1]
SAR_IP
ENABLE ua[0]
CK_SAMPLE SAR_IN
clk CK_SAMPLE_BSSW
CK_SAMPLE SARN
SARN
d1
diode_pw2nd_05v5 CK_SAMPLE_BSSW SARP
area=2.025e11 EN SARP
rst_n pj=1.8e6
diode
D<7>
EN DONE
DONE
D2
d0 D<7> D<7>
D<6> D<7>
D<6> D<6>
D<5> D<6>
VGND D<5> D<5>
D<4> D<5>
D<4> D<4>
D<3> D<4>
D<3> D<3> SUNSAR_SAR8B_CV
D<2> D<3>
D<2> D<2>
D<1> D<2>
D<1> D<1>
D<0> SUNSAR_CAPT8B_CV
D<1>
D<0> D<0>
ui_in[0] uo_out[7] D<0>
DO<7> EN
uo_out[6] EN
DO<6> CK_SAMPLE
uo_out[5] CK_SAMPLE
d1
DO<5> CK_SAMPLE_BSSW
diode_pw2nd_05v5 uo_out[4] CK_SAMPLE_BSSW
ui_in[7:0] area=2.025e11 diode uo_out[3]
DO<4> VPWR
VREF
pj=1.8e6
D3
DO<3> VPWR
d0 uo_out[2] d1
diode_pw2nd_05v5 AVDD
DO<2> area=2.025e11 VGND
uo_out[1] diode AVSS
DO<1> pj=1.8e6
D1
VGND uo_out[0] d0
DO<0>
DONE
DONE
VPWR VGND
AVDD
VGND
AVSS
VGND TIE_L
TIE_L Designer Carsten Wulff
Updated wulff
Modified 2024-04-12 [Link]
Copyright Carsten Wulff Software
Library/Cell tt_um_TT06_SAR_wulffern

18.4.2 SAR operation

The key idea is to model the analog behavior to sufficient detail

such that we can verify the digital code. I think it’s best to have a
look at a concrete example.

▶ Analog input is sampled when clock goes low (sarp/sarn)

▶ uio_out[0] goes high when bit-cycling is done
▶ Digital output (ro) changes when uio_out[0] goes high
 18.4 Analog SystemVerilog Example 307

//tt06-sar/src/project.v
module tt_um_TT06_SAR_wulffern (
input wire VGND,
input wire VPWR,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
`ifdef ANA_TYPE_REAL
input real ua_0,
input real ua_1,
`else
// analog pins
inout wire [7:0] ua,
`endif
input wire ena,
input wire clk,
input wire rst_n
);

//tt06-sar/src/tb_ana.v
`ifdef ANA_TYPE_REAL
real ua_0 = 0;
real ua_1 = 0;

`else
tri [7:0] ua;
logic uain = 0;
assign ua = uain;
`endif

`ifdef ANA_TYPE_REAL
always #100 begin
ua_0 = $sin(2*3.14*1/7750*$time);
ua_1 = -$sin(2*3.14*1/7750*$time);
end
`endif

//tt06-sar/src/tb_ana.v
tt_um_TT06_SAR_wulffern dut (
.VGND(VGND),
.VPWR(VPWR),
.ui_in(ui_in),
.uo_out(uo_out),
.uio_in(uio_in),
.uio_out(uio_out),
.uio_oe(uio_oe),
`ifdef ANA_TYPE_REAL
.ua_0(ua_0),
.ua_1(ua_1),
`else
.ua(ua),
`endif
.ena(ena),
.clk(clk),
.rst_n(rst_n)
);

#tt06-sar/src/Makefile
runa:
iverilog -g2012 -o my_design -c tb_ana.fl -DANA_TYPE_REAL
vvp -n my_design

rund:
iverilog -g2012 -o my_design -c tb_ana.fl
vvp -n my_design

//tt06-sar/src/project.v
//Main SAR loop
always_ff @(posedge clk or negedge clk) begin
308 18 Analog SystemVerilog

if(~ui_in[0]) begin
state <= OFF;
tmp = 0;
dout = 0;
end
else begin
if(OFF) begin

end
else if(clk == 1) begin
state = SAMPLE;
end
else if(clk == 0) begin
state = CONVERT;
`ifdef ANA_TYPE_REAL
smpl = ua_0 - ua_1;
tmp = smpl;

for(int i=7;i>=0;i--) begin

if(tmp >= 0) begin
tmp = tmp - lsb*2**(i-1);
if(i==7)
dout[i] <= 0;
else
dout[i] <= 1;
end

else begin
tmp = tmp + lsb*2**(i-1);
if(i==7)
dout[i] = 1;
else
dout[i] = 0;
end
end
`else
if(tmp == 0) begin
dout[7] <= 1;
tmp <= 1;

end
else begin
dout[7] <= 0;
tmp = 0;
end
`endif

end
state = next_state;
end // else: !if(~ui_in[0])
end // always_ff @ (posedge clk)

//tt06-sar/src/project.v
always @(posedge done) begin
state = DONE;
sampled_dout = dout;
end

always @(state) begin

if(state == OFF)
#2 done = 0;
else if(state == SAMPLE)
#1.6 done = 0;
else if(state == CONVERT)
#115 done = 1;
end
 18.5 Want to learn more? 309

18.5 Want to learn more?

For more information on real-number modeling I would recom-

mend The Evolution of Real Number Modeling
 How to write a project report 19
19.1 Why . . . . . . . . . . 311
19.1 Why
19.2 On writing English 311
19.2.1 Shorter is better . . . 311
Them who has a Why? in life can tolerate almost any 19.2.2 Be careful with
How? adjectives . . . . . . . 312
19.2.3 Use paragraphs . . . 312
You’re writing the report on the project for me to be able to see 19.2.4 Don’t be afraid of I . 312
inside your head, and grade how much of the project you have 19.2.5 Transitions are impor-
tant . . . . . . . . . . 312
understood.
19.2.6 However, is not a
start of a sentence . 313
▶ Have you learned what is to be expected?
19.3 Report Structure . . 313
▶ Do you understand what you’re trying to explain?
19.3.1 Introduction . . . . . 313
19.3.2 Theory . . . . . . . . 313
You will work on the project in groups, however, on the report, 19.3.3 Implementation . . . 314
you will write on your own. 19.3.4 Result . . . . . . . . . 314
19.3.5 Discussion . . . . . . 314
That means, that there will be X projects reports that describe the
19.3.6 Future work . . . . . 314
same circuit. You shall not copy someone elses report text. 19.3.7 Conclusion . . . . . . 314
19.3.8 Appendix . . . . . . 315
It’s fine to share figures between reports, and also references.
19.4 Checklist . . . . . . . 315
I’m also forcing you to use a report format that matches well with
what would be expected if you were to publish a paper.

Should you make a fantastic temperature sensor, and maybe even

reach close to a tapeout I would strongly suggest you submit a
paper to NorCas. The deadline is August 15 2024.

19.2 On writing English

Writing well is important. I would recommend that you read On

writing Well.

Most of you won’t buy the book, as such, a few tips.

19.2.1 Shorter is better

I can write the section title idea in many words:

A shorter text will more elequently describe the intrica-

cies of your thoughts than a long, distinguished, tirade
of carefully, wonderfully, choosen words.

or

Shorter is better
312 19 How to write a project report

Describe an idea with as few words as possible. The text will be

better, and more readable.

19.2.2 Be careful with adjectives

Words like “very, extremely, easily, simply, . . . ” don’t belong in a

readable text. They serve no purpose. Delete them.

19.2.3 Use paragraphs

You write a text to place ideas into anothers head. Ideas and
thoughts are best communicated in chunks. I can write a dense set
of text, or I can split a dense set of text into multiple paragraphs.
The more I try to cram into a paragraph, for example, how magical
the weather has been the last weeks, with lots of snow, and good
skiing, the more difficult the paragraph is to read.

One paragraph, one thought. For example:

You write a text to place ideas into anothers head. Ideas and
thoughts are best communicated in chunks.

I can write a dense set of text, or I can split a dense set of text into
multiple paragraphs.

The more I try to cram into a paragraph, for example, how magical
the weather has been the last weeks, with lots of snow, and good
skiing, the more difficult the paragraph is to read.

19.2.4 Don’t be afraid of I

If you did something, then say “I” in the text. If there were more
people, then use “we”.

19.2.5 Transitions are important

Sentences within a paragraph are sometimes linked. Use

▶ As a result,
▶ As such,
▶ Accordingly,
▶ Consequently,

And mix them up.

 19.3 Report Structure 313

19.2.6 However, is not a start of a sentence

If you have to use “However” it should come in the middle of the

sentence.
I want to go skiing, however, I cannot today due to work.

19.3 Report Structure

The sections below go through the expected structure of a report,

and what the sections should contain.

19.3.1 Introduction

The purpose of the introduction is to put the reader into the right
frame of mind. Introduce the problem statement, key references,
the key contribution of your work, and an outline of the work
presented. Think of the introduction as explaining the “Why” of
the work.
Although everyone has the same assignment for the project, you
have chosen to solve the problem in different ways. Explain what
you consider the problem statement, and tailor the problem state-
ment to what the reader will read.
Key references are introduced. Don’t copy the paper text, write
why they designed the circuit, how they chose to implement it,
and what they achieved. The reason we reference other papers
in the introduction is to show that we understand the current
state-of-the-art. Provide a summary where state-of-the-art has
moved since the original paper.
The outline should be included towards the end of the introduction.
The purpose of the outline is to make this document easy to read. A
reader should never be surprised by the text. All concepts should
be eased into. We don’t want the reader to feel like they been
thrown in at the end of a long story. As such, if you chosen to solve
the problem statement in a way not previously solved in a key
references, then you should explain that.
A checklist for all chapters can be seen in table below.

19.3.2 Theory

It is safe to assume that all readers have read the key references, if
they have not, then expect them to do so.
The purpose of the theory section is not to demonstrate that you
have read the references, but rather, highlight theory that the
reader probably does not know.
314 19 How to write a project report

The theory section should give sufficient explanation to bridge the

gap between references, and what you apply in this text.

19.3.3 Implementation

The purpose of the implementation is to explain what you did.

How have you chosen to architect the solution, how did you split
it up in analog and digital parts? Use one subsection per circuit.

For the analog, explain the design decisions you made, how did
you pick the transistor sizes, and the currents. Did you make other
choices than in the references? How does the circuit work?

For the digital, how did you divide up the digital? What were the
design choices you made? How did you implement readout of the
data? Explain what you did, and how it works. Use state diagrams
and block diagrams.

Use clear figures (i.e. circuitikz), don’t use pictures from schematic
editors.

19.3.4 Result

The purpose of the results is to convince the reader that what

you made actually works. To do that, explain testbenches and
simulation results. The key to good results is to be critical of your
own work. Do not try to oversell the results. Your result should
speak for themself.

For analog circuits, show results from each block. Highlight key
parameters, like current and delay of comparator. Demonstrate
that the full analog system works.

Show simulations that demonstrate that the digital works.

19.3.5 Discussion

Explain what the circuit and results show. Be critical.

19.3.6 Future work

Give some insight into what is missing in the work. What should
be the next steps?

19.3.7 Conclusion

Summarize why, how, what and what the results show.

 19.4 Checklist 315

19.3.8 Appendix

Include in appendix the necessary files to reproduce the work. One

good way to do it is to make a github repository with the files, and
give a link here.

19.4 Checklist

Item Description OK
Is the problem Describe which parts of the problem you chose to focus on. The
description problem description should match the results you’ve achieved.
clearly defined?
Is there a clear The reader might need help to understand why the problem is
explanation interesting
why the
problem is
worth solving?
Is status of You should make sure that you know what others have done for
state-of-the-art the same problem. Check IEEEXplore. Provide summary and
clearly references. Explain how your problem or solution is different
explained?
Is the key Highlight what you’ve achieved. What was your contribution?
contribution
clearly
explained?
Is there an Give a short summary of what the reader is about to read
outline of the
report?
Is it possible for Have you included references to relevant papers
a reader skilled
in the art to
understand the
work?
Is the theory The theory section should be less than 10 % of the work
section too long
Are all circuits Have you explained how every single block works?
explained?
Are figures Remember to explain all colors, and all symbols. Explain what
clear? the reader should understand from the figure. All figures must
be referenced in the text.
Is it clear how It’s a good idea to explain what type of testbenches you used. For
you verified the example, did you use dc, ac or transient to verify your circuit?
circuit?
Are key You at least need current from VDD. Think through what you
parameters would need to simulate to prove that the circuit works.
simulated?
Have you tried Knowing how circuits fail will increase confidence that it will
to make the work under normal conditions.
circuit fail?
Have you been Try to look at the verification from different perspectives. Play
critical of your devil’s advocate, try to think through what could go wrong, then
own results? explain how your verification proves that the circuit does work.
Have you Imagine that someone reads your work. Maybe they want to
explained the reproduce it, and take one step further. What should that step be?
next steps?
No new Never put new information into conclusion. It’s a summary of
information in what’s been done
conclusion.
Story Does the work tell a story, is it readable? Don’t surprise the reader
by introducing new topics without background information.
Chronology Don’t let the report follow the timeline of the work done. What I
mean by that is don’t write “first I did this, then I spent huge
amount of time on this, then I did that”. No one cares what the
timeline was. The report does not need to follow the same
timeline as the actual work.
316 19 How to write a project report

Item Description OK
Too much time How much time you spent on something should not be
correlated to how much text there is in the report. No one cares
how much time you spent on something. The report is about
why, how, what and does it work.
Length A report should be concise. Only include what is necessary, but
no more. Shorter is almost always better than longer.
Template Use [Link]. Example can be seen from an old version of this
document at [Link]
/2021-10-19_project_report. Write in LaTeX. You will need
LaTeX for your project and master thesis. Use
[Link] if you’re uncomfortable with local text
editors and LaTeX.
Spellcheck Always use a spellchecker. Misspelled words are annoying, and
may change content and context (peaked versus piqued)
 Layout Generation 20
20.1 Layout . . . . . . . . . 317
20.1 Layout
20.2 Setup . . . . . . . . . . 317
20.3 CICPY . . . . . . . . . 317
The open source tools don’t have any automatic analog layout. 20.4 Placement . . . . . . . 317
To my knowledge, there is no general purpose analog automagic
layout anywhere in the world. It’s an unsovled problem. Many
have tried (including myself), but none have succeeded with a
generic analog layout engine.

There are a few things, though, that could help you on the way.

20.2 Setup

I assume that you have the latest and greatest aicex\ip setup.

See SKY130NM Tutorial if aicex is unfamiliar.

Let’s assume we use jnw_gr05_sky130a to test out our layout

cd aicex/ip/
cd jnw_gr05_sky130a
git checkout a1e3dfc324194729e042f5e653777b052759863b
cd work

20.3 CICPY

The first thing we need to do is to place all transistors. I do have a

script to help. Install cicpy.

cd aicex/ip/cicpy
git checkout master
git pull
python3 -m pip install -e .
cd ..
cd cicspi
git checkout main
git pull
python3 -m pip install -e .

20.4 Placement

To generate an initial placement we can do the command below. If

a layout exists it will be overriden

cd jnw_gr05_sky130a/work
cicpy sch2mag JNW_GR05_SKY130A OTA_Manuel
318 20 Layout Generation

The layout engine has no idea what components belong together,

for example, the current mirror below should have been place
together

We can instruct the layout engine by adding a “group” name

to the instance name. The instance name always starts with
x<something><number> where the something can be nothing, or a
group name (a,b, not a number).

The rules for placement are:

1. Sort all instances by groups

2. Sort all groups by instance name
3. Place the first instance.
4. For all instances: If the next instance has the same group,
then add on top. Otherwise increment the x location.

As such, if I rename my instances, as shown below,

 20.4 Placement 319

Then the layout becomes a bit better

cicpy sch2mag JNW_GR05_SKY130A OTA_Manuel --gbreak 3 --xspace 34000 --yspace 30000

The gbreak command inserts a “group break” after the fourth

group, such that a new Y coordinate is selected.

The X and Y space is for the distance between groups. The unit is
“Ångstrøm”, so 1 um is 10 000 Å.
320 20 Layout Generation
 MOSFETs 21
I’m stunned if you’ve never heared the word “transistor”. I think 21.1 Metal Oxide Semi-
most people have heard the word. What I find funny is that almost conductor . . . . . 321
nobody understand in full detail how transistors work. 21.2 Field Effect . . . . 323
21.3 Analog transistors
Through my 30 year venture into the world of electronics I’ve in the books . . . . 327
met “analog designers”, or people that should understand exactly 21.4 Transistors in weak
how transistors work. I used to hire analog designers, and I’ve inversion . . . . . . 329
interviewed hundred plus “analog designers” in my 8 years as 21.5 Transistors in
manager and I’ve met hundreds of students of analog design. I strong inversion . 332
would go as far as to say none of them know everything about 21.6 How should I size
transistors, including myself. my transistor? . . . 335
21.7 Introduction to
Most of the people I’ve met have a good brain, so that is not the
behavior . . . . . . 336
reason they don’t understand. Transistors are incredibly compli- 21.7.1 Drain Source Cur-
cated! I say this, because if at some point in this document, you rent . . . . . . . . . 336
don’t understand, then don’t worry, you are not alone. 21.7.2 Gate-source voltage 337
21.7.3 Inversion level . . . 337
In this document I’m focusing on Metal Oxide Semiconductor Field 21.7.4 Drain source volt-
Effect Transistors (MOSFETs), and ignore all other transistors. age . . . . . . . . . . 339
21.7.5 Strong inversion . 340
21.7.6 Low frequency
21.1 Metal Oxide Semiconductor 21.7.7
model . . . . . . . . 342
Transconductance 342
21.7.8 Intrinsic gain . . . 343
The first part of the MOSFET name illustrates the 3 dimensional 21.7.9 High frequency
composition of the transistor. Take a semiconductor (Silicon), grow model . . . . . . . . 344
21.7.10 Be careful with Cgd
some oxide (Silicon Oxide, SiO2), and place a metal, or conductive,
(blame Miller) . . . 346
gate on top of the oxide. With those three components we can build
21.8 Weak inversion . . 347
our transistor.
21.9 Velocity saturation 348
Something like the cartoon below where only the Metal (gate) of 21.9.1 Square law model 349
the MOS name is shown. 21.9.2 Mobility Degrada-
tion . . . . . . . . . 349
The oxide and the silicon bulk is not visible, but you can imagine 21.9.3 What about holes
them to be underneath the gate, with a thin oxide (a few nano (PMOS) . . . . . . . 350
meters thick) and the silicon the transparent part of the picture. 21.10 OTHER . . . . . . . 350
21.10.1 Drain induced
The length (L), and width (W) of the MOS is annotated in blue. barrier lowering
(DIBL) . . . . . . . 351
21.10.2 Well Proximity
Effect (WPE) . . . . 352
21.10.3 Stress effects . . . . 352
21.10.4 Gate current . . . . 353
21.10.5 Hot carrier injection 353
21.10.6 Channel initiated
secondary-electron
(CHISEL) . . . . . . 354
21.11 Variability . . . . . 354
21.11.1 Voltage variation . 355
21.11.2 Systematic varia-
tions . . . . . . . . . 355
21.11.3 Process variations 356
21.11.4 Process corners . . 356
21.11.5 Fix process varia-
tion . . . . . . . . . 357
322 21 MOSFETs

Figure 1: 3D crossection of a transistor

MOSFETs come in two main types. There is NMOS, and PMOS.

The symbols are as shown below. The NMOS is MN1 and PMOS is
MP1.

VD VS

MN1 MP1
VG VG

VS VD

Figure 2: Transistor symbols

The MOS part of the name can be seen in MN1, where 𝑉𝐺 is the gate
connected to a vertical line (metal), a space (oxide), and another
vertical line (the silicon substrate or silicon bulk).

On the sides of the gate we have two connections, a drain 𝑉𝐷 and

a source 𝑉𝑆 .

If we have a sufficient voltage between gate and source 𝑉𝐺𝑆 , then

the transistor will conduct from drain to source. If the voltage is
too low, then there will not be much current.

The “source” name is because that’s where the charge carrier

(electrons) come from, they come from the source, and flow towards
the drain. As you may remember, the “current”, as we’ve defined
it, flows opposite of the electron current, from drain to source.

The PMOS works in a similar manner, however, the PMOS is made

of a different type of silicon, where the dominant charge carrier
is holes in the valence band. As a result, the gate-source voltage
needs to be negative for the PMOS to conduct.

In a PMOS the holes come from the source, and flow to the drain.
Since holes are positive charge carriers, the current flows from
source to drain.

In most MOSFETs there is no physical difference between source

and drain. If you flip the transistor it would work almost exactly
the same.
 21.2 Field Effect 323

21.2 Field Effect

Imagine that the bulk (the empty space underneath the gate), and
the source is connected to 0 V. Assume that the gate is 0 V.

In the source and drain parts of the transistor there is an abundance

of free electrons that can move around, exactly like in a metal
conductor, however, underneath the gate there are almost no free
electrons.

There are electrons underneath the gate though, trillions upon

trillions of electrons, but they are stuck in co-valent bonds between
the Silicon atoms, and around the nucleus of the Silicon atoms.
These electrons are what we call bound electrons, they cannot
move, or more precisely, they cannot contribute to current (because
they do move, all the time, but mostly around the atoms).

Imagine that your eyes could see the free electrons as a blue
fluorescent color. What you would see is a bright blue drain, and
bright blue source, but no color underneath the gate.

Figure 3: MOSFET in “off” state

As you increase the gate voltage, the color underneath the gate
would change. First, you would think there might be some blue
color, but it would be barely noticeable.

Figure 4: MOSFET in subthreshold

324 21 MOSFETs

At a certain voltage, suddenly, there would be a thin blue sheet

underneath the gate. You’d have to zoom in to see it, in reality it’s
a ultra thin, 2 dimensional electron sheet.

As you continue to increase the gate voltage the blue color would
become a little brighter, but not much.

Figure 5: MOSFET in strong inversion

This thin blue sheet extend from source to drain, and create a
conductive channel where the electrons can move from source to
drain (or drain to source), exactly like a resistor. The conductance of
the sheet is the same as the brightness, higher gate source voltage,
more bright blue, higher conductance, less resistance.

Assume you raise the drain voltage. The electrons would move from
source to drain proportional to the voltage. How many electrons
could move would depend on the gate voltage.

If the gate voltage was low, then there is low density of electrons
in the sheet, and low current.

If the gate voltage is high, then the electron density in the sheet
is high, and there can be a high current, although, the electrons
do have a maximum speed, so at some point the current does not
change as fast with the gate voltage.

At a certain drain voltage you would see the blue color disappear
close to the drain and there would be a gap in the sheet.
 21.2 Field Effect 325

Figure 6: MOSFET in strong inversion and saturation

That could make you think the current would stop, but it turns out,
that the electrons close to drain get swept across the gap because
the electric field is so high from the edge of the sheet to the drain.

As you continue to increase the drain voltage, the gap increases,

but the current does not really increase that much. It’s this exact
feature that make transistor so attractive in analog circuits. I can
create a current from drain to source that does not depend much
on the drain to source voltage! That’s why we sometimes imagine
transistors as a “trans-conductance”. The conductance between
drain and source depends on the voltage somewhere else, the
gate-source voltage.

And now you may think you understand how the transistor works.
By changing the gate voltage, we can change the electron current
from source to drain. We can turn on, and off, currents, creating a
0 and 1 state.

For example, if I take a PMOS and connect the source to a high

voltage, the drain to an output, and an NMOS with the source to
ground and the drain to the output, and connect the gates together,
I would have the simplest logic gate, an inverter, as shown below.

If the input 𝑉𝑖𝑛 is a high voltage, then the output 𝑉𝑜𝑢𝑡 is a low
voltage, because the NMOS is on. If the input 𝑉𝑖𝑛 is a low voltage,
then the output 𝑉𝑜𝑢𝑡 is a high voltage, because the PMOS is on.

MP1

Vin Vout

MN1

Figure 7: Inverter
326 21 MOSFETs

I can now build more complex “logic gates”. The one below is a
Not-AND gate (NAND). If both inputs (A and B) are high, then
the output is low (both NMOS are on). Otherwise, the output is
high.

I find it amazing that all digital computers in existence can be

constructed from the NAND gate. In principle, it’s the only logic
gate you need. If you actually did construct computers from
NANDs only, they would be costly, and consume lots of power.
There are smarter ways to use the transistors.

Figure 8: NAND

You may be too young to have seen the Matrix, but now is the time
to decide between the red pill and the blue pill.

The red will start your journey to discover the reality behind the
transistor, the blue pill will return you to your normal life, and you
can continue to think that you now understand how transistors
work.
 21.3 Analog transistors in the books 327

Figure 9: The choice

Because:

▶ Why did the area underneath the gate turn blue?

▶ Why is it only a thin sheet that turns blue?
▶ Where did the electrons for the sheet come from?
▶ Why did the blue color change suddenly?
▶ How does the brightness of the blue change with gate-source
voltage?
▶ How can the electrons stay in that sheet when we connect
the bulk to 0 V?
▶ Why is there not a current from the bulk (0 V) to drain?
▶ Why does not the electrons jump from source to drain? It’s a
gap, the same as from the sheet to drain?

And did you realize I never in this chapter explained how the field
effect worked?

Someday, I may write all the details, if I ever understand it all. For
now, I hope that the sections below will help you a bit.

21.3 Analog transistors in the books

In the books we learn the equations for weak inversion

𝐼𝐷 ∝ (𝑒 (𝑉𝑔𝑠 −𝑉𝑡 ℎ )/𝑈𝑇 − 1)

, where 𝐼𝐷 is the drain current, 𝑉𝑔𝑠 is the gate source voltage, 𝑉𝑡 ℎ

is the threshold voltage and 𝑈𝑇 = 𝑘𝑇/𝑞 , where 𝑘 is Boltzmann’s
constant, 𝑇 is the temperature in Kelvin and 𝑞 is the unit charge

The equation is similar to bipolar and diode equations, because

the physics is the same.

The drain current in weak inversion is mostly a diffusion current

and relates to the density of electrons in the conduction band (for
328 21 MOSFETs

an NMOS), which can be computed from the density of available

energy states, and the Fermi-Dirac distribution.

∫ ∞
1
𝑛= 𝑁(𝐸) 𝑑𝐸
𝐸𝐶 𝑒 (𝐸−𝐸𝐹 )/𝑘𝑇 + 1

, where 𝑛 is the density of electrons in the conduction band, 𝑁(𝐸) is

the density of available energy states, 𝐸 is the integration variable
(and the energy) and 𝐸𝐹 is the Fermi-level.

Maybe the equation looks complicated, but it’s really “Multiply

the available energy state with the probability of being in that state,
and sum for all available energy states”.

Changing the voltage changes the number of free electrons, simply

because we bring the conduction band closer to the Fermi level.

The Fermi level is just something we invented, and just means

“If there was an quantum state at the Fermi level Energy, then it
would have a 50 % probability of being occupied by a electron”.

In the equation above, moving the conduction band edge is equiva-

lent to reducing the 𝐸𝐶 . As such, more of the Fermi-Dirac distribu-
tion has available energy states 𝑁(𝐸), and the density of electrons
𝑛 in conduction band becomes higher.

In strong inversion, the MOSFET is more like a voltage controlled

resistor with a conductance that is proportional to gate-source
voltage.

The density of electrons increases because we bend the conduction

band beyond the Fermi level, as a result, most of the available
energy states in the conduction band are filled by electrons.

Electrons are only free to move, however, close to the surface of

the silicon, as far away from the surface, we don’t feel the effects
of the gate-source voltage, and the conduction band stays at the
same energy. As a result, electrons form a 2 dimensional electron
gas close to the silicon surface. What we call an inversion layer.

Once we have that electron gas, or inversion layer, we have a

connection between the drain and source n-type regions, and the
current can be estimated by a drift current. Parts of the diffusion
current will still be there, but much smaller magnitude than the
drift current, so we drop the diffusion current, and get

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶 𝑜𝑥 (𝑉𝑔𝑠 − 𝑉𝑡 ℎ )2
2 𝐿

The equations in the books are good to give a physical understand-

ing of what happens. Although, we tend to forget that everybody
forgets.
 21.4 Transistors in weak inversion 329

We teach quantum physics one year, and how to compute the

density of states 𝑁(𝐸) from Schrodinger, the wave-function and
Fermi-Dirac distribution.
Next year we talk about semiconductors, crystal lattice, band
structure (density of states as a function of space), energy diagrams
(band structure is complex, so we just use the lowest conduction
band and highest valence band), doping to shift the Fermi level,
and how we can create PN-junctions, bipolars and MOSFETS.
The year after we teach the current equations for MOSFETs, and
the books don’t have the link back to solid-state physics, after all,
we already told the students that, they should remember!
I think, quite often, we just end up with confused students. And
I don’t think it’s necessary to end up with confused students.
Maybe sometimes we end up with confused students because the
Professors can’t necessarily remember where the equations come
from either, nor how electrons and holes really behave.
It’s not necessary for an analog design student to remember how
to compute the density of available energy states from Schrodinger
and the wave function. If we wanted to use the relativistc version
of Schrodinger (which includes magnetic fields, and if you did not
know, magnetic fields is just a relativistic effect of the electric field)
and the wave function to compute how an Silicon atom actually
behaves, I don’t think we can. As far as I’ve been able to figure out,
it’s not possible to have a closed form solution (symbolic), nor is
it possible with supercomputers to do a numeric time-evolution
of the states in a single Silicon atom with all the inter-particle
interactions, space, momentum, spins, electric fields and magnetic
fields.
But we can make sure we connect the links from Schrodinger to the
MOSFET equations, the short version of that was above, but the
following sections tries to explain with words how the transistor
actually works.
I’m not going to give all the equations and all the maths. For that,
there are excelent books and resources. I would recommend Mark
Lundstrom for the best in detail description of MOSFETs.

21.4 Transistors in weak inversion

Consider the cartoon below which shows the hole concentration

in the valence band, and electron concentration in the conduction
band versus the x direction of the transistor.
For the moment we’ll ignore the field effect of the gate, and how
that modulates the hole concentration underneath the gate.
If you’re familiar with bipolars, then you may think I’ve drawn the
wrong transistor, because you see an NPN bipolar transistor. The
330 21 MOSFETs

picture is correct, however, this is how a normal MOSFET looks.

It’s actually also a NPN bipolar transistor, but we don’t usually use
that part (you’ll see more when we get to ESD)

In the source we’ve doped with donors, and have an abundance of

free electrons. Underneath the gate, or the bulk, we have doped
with acceptors, and have an abundance of holes.

Source Gate Drain

n p n

Source Gate
Figure 10: Charge carrier density in a MOSFET
Drain
Let’s consider electron current for now, and only look at the
conduction band.

Source
In Gate
An electron in the source would see a energy barrier of 𝜙 𝐵 , and most
Drain
electrons would be turned around at the barrier. Some, however,
do have the energy to traverse the barrier and flow through the
n all of them would
bulk. Not
p reach the bulk,ndue to recombination,
but let’s assume the bulk is short, and all electrons injected into
the bulk show up at the drain.
e e
At the drain side they would fall down the potential barrier to the
drain. The nsame process wouldphappen in reverse, n from drain to
source.

Source
Source Gate
Gate Drain
Drain

n n
Mma
In p p
n n

e e
e e

Figure 11: MOSFET subthreshold , 𝑉𝐷𝑆 = 0

There would also be hole currents flowing between source/bulk/drain

Source
and visa versa Gate Drain
 n p n
21.4 Transistors in weak inversion 331

Source Gate Drain

Assume source and drain are at the same potential, then the sum
of all currents (1,2,3,4) for both electrons and holes in Figure 11
must equal zero.

In
Assume that we increase the drain voltage, as shown in Figure 12.
Increasing the drain voltage is the same as reducing the conduction
band in the drain.

n to bulk, it’s now

n now is a higher p
Since there barrier from drain
much less probable that electrons are injected from drain to bulk.
Now the sum e of all currents would
e not equal zero, as the 1 and 3
currents are larger than 2 and 4.
As such, there would be a net flow of electron current from source
to drain.

Source Gate Drain

n
Mma p n

e e

Figure 12: MOSFET subthreshold, 𝑉𝑆 = 0 V , 𝑉𝐷 > 0 V

Notice that if we increase the drain voltage further, then the electron
injection from drain to bulk would quickly approach zero.
At that point, even though we increase the drain voltage further,
the current does not really change. As the current is only now
given by the barrier height at the source.
The barrier height at the source is the built in voltage of the
junction, and as we’ve seen before, that voltage depends on doping
concentration. If we increase the hole concentration in bulk, then we
increase the barrier height, and it’s less probable that the electrons
have enough energy to be injected from source to bulk.
If we only need to consider the electrons and holes at source for the
subthreshold current (assuming the drain voltage is high enough),
then we should expect the equation look very similar to a diode,
and indeed it does.
The drain current, which is mostly a diffusion current, is given
by

𝑊 𝑞(𝑉𝐺𝑆 −𝑉𝑇𝐻 )/𝑛 𝑘𝑇

𝐼𝐷 = 𝐼𝐷 0 𝑒
𝐿
332 21 MOSFETs

where

𝑛 = (𝐶 𝑜𝑥 + 𝐶 𝑗 0 )/𝐶 𝑜𝑥

2
𝑘𝑇

𝐼𝐷 0 = (𝑛 − 1)𝜇𝑛 𝐶 𝑜𝑥
𝑞

This is not exactly the same as the diode equation, but we can see
that it looks similar. Most of the quantum mechanics is baked into
the 𝑉𝑇𝐻

The transconductance ( 𝑑𝐼𝐷 /𝑑𝑉𝐺𝑆 ) in weak inversion is then

𝐼𝐷
𝑔𝑚 =
𝑛𝑉𝑇

A big difference from the diode equation is the fact that the gate-
source voltage seems to determine the current, and not the voltage
across the pn junction.

21.5 Transistors in strong inversion

Consider the band diagram in Figure 13, in the figure we’re looking
at a cross section of the transistor. From left we’re in the gate, then
we have the oxide, and then the bulk of the transistor.

We don’t see the drain and source, as the source would be towards
you, and the drain would be into the picture.

The cartoon is not a real transistor. I don’t think there is necessarily

a combination of semiconductor and metal where we end up with
the same Fermi level (𝐸𝐹 ) without some bending of the conduction
band and valence band, but for illustration, let’s assume that’s the
case.

We can see the Fermi level in the semiconductor is shifted towards

the valence band, and thus we have a P-type semiconductor.

The gate is metallic, so it does not have a bandgap, and we assume

that the Fermi level is at the conduction band edge.
 ab
21.5 Transistors in strong inversion 333
n ab
n

Gate Eide Bulk

Gate Eide Bulk EC
EC

É
É
Figure 13: Band diagram of a fictive MOSFET.

Assume we increase the gate-source voltage. In a band diagram

that corresponds to shifting the energy down.

Gate Eide Bulk

Gate Eide Bulk Ec

Ec

at É
at É

Figure 14: Band diagram with gate-source voltage applied

Moving the gate down has the effect of bending the bands in the
semiconductor. We’ll lose some voltage across the oxide, but not
necessarily that much.

The bending of the valence band will decrease the hole concen-
tration close to the silicon surface, and the semiconductor will be
depleted of mobile charge carriers.

The valence band bending will also reduce the barrier height in
Figure 12, which increases the number of carriers that can be
injected at source/bulk interface, so the subthreshold current will
start to increase.

At some point, the band bending of the conduction band will

become so large that the electron concentration underneath the
334 21 MOSFETs

gate will increase signficantly. The gate-source voltage where the

electron concentration equals the bulk hole concentration far away
from the silicon surface is called the “threshold voltage”.

As you continue to increase the gate-source voltage there is a limit

to how much the electron concentration increases. When the band
bending of the conduction band passes the Fermi level, then over
50 percent of the available states in the conduction band are filled
with electrons.

Gate Eide Bulk

Ec

qV IF

I
Figure 13: Band diagram with high gate-source voltage applied

The conditions to be in strong inversion is that the gate/source

voltage is above some magic values (threshold voltage), and then
some.

The quantum state of the electron is fully determined by it’s spin,

momentum and position in space. How those parameters evolve
with time is determined by the Schrodinger equation. In the general
form

𝑑
𝑖ℏ Ψ(𝑟, 𝑡) = 𝐻Ψ(𝑟,
b 𝑡)
𝑑𝑡

The Hamiltonian (𝐻 ) is an “energy matrix” operator and may

contain terms both for the momentum and Columb force (electric
field) experienced by the system.

But what does the Schrodinger equation tell us? Well, the equation
above does not tell me much, it can’t be “solved”, or rather, it does
not have a single solution. It’s more a framework for how the wave
function, and the Hamiltonian, describes the quantum states of
 21.6 How should I size my transistor? 335

a system, and the probability ampltiudes of transition between

states.

The Schrodinger equation describes the time evolution of the

bound electrons shared between the Silicon atoms, and the fact
that applying a electric field to silicon can free co-valent bonds.

As the gate-source voltage increases the wave function that fits in

the Schrodinger equation predicts that the free electrons will form
a 2d sheet underneath the gate. The thickness of the sheet is only a
few nano meters.

In Figure 2 in

Carrier transport near the Si/SiO2 interface of a MOSFET

you can see how the free electron density is located underneath
the gate.

I would really recommend that you have a look at Mark Lund-

strom’s lecture series on Essentials of MOSFETs. It’s the most
complete description of electrons in MOSFET’s I’ve seen

21.6 How should I size my transistor?

The method that makes most sense to me, is to use the inversion-
coefficient method, described in Nanoscale MOSFET Modeling:
Part 1 and Nanoscale MOSFET Modeling: Part 2.

The inversion coefficient tells us how strongly inverted the MOSFET

channel (inversion layer) is. A number below 0.1 is weak inversion,
between 0.1 and 10 is moderate inversion. A number above 10 is
strong inversion.

There are also some blog posts worth looking at Inversion Coeffi-
cient Based Circuit Design and My Circuit Design Methodology.

I should caveat my proposal for method. For the past 7 years I’ve
not had the luxury to do full time, hardcore, analog design. As my
career progressed, most of my time is now spent telling others what
I think is a good idea to do, and not doing hardcore analog design
myself. I think, however, I have a pretty decent understanding of
analog circuits, and how to design them, so I think I’m correct in
the proposal. If I were to start hardcore analog design now, I would
go all in on inversion-coefficient based transistor size selection.
336 21 MOSFETs

21.7 Introduction to behavior

Let’s assume we know nothing about how transistors work, but

we do know how to simulate them in ngspice.

We could sit down, and try and figure out how the transistors
work.

You can find the testbenches at Testbenches at dicex/sim/spice/N-

CHIO

21.7.1 Drain Source Current

Let’s see what happens to the drain to source current when we

change the voltages. We would expect the drain to source current
to change as a function of the drain to source, 𝑉𝐷𝑆 , and gate to
source 𝑉𝐺𝑆 voltages. Or mathematically

𝐼𝐷𝑆 = 𝑓 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 , ...)

or symbolically

The symbolic model above is what we call a “Large Signal Model”.

We could expand the function above to

𝐼𝐷𝑆 = 𝑓 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 ) = 𝐺 𝑚 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝐼𝐷𝑆 )𝑉𝐺𝑆 +𝐺 𝑑𝑠 (𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝐼𝐷𝑆 )𝑉𝐷𝑆

, where the 𝐺 𝑚 is a trans-conductance (the current depends on

a voltage somewhere else), and 𝐺 𝑑𝑠 is a conductance (current
depends on the voltage across the conductance).

Even now we can see that the model above is complicated. The
transconductance and conductance of the transistor is a function
of the other voltages, and the output current. It’s a non-linear
system!
 21.7 Introduction to behavior 337

If the transistor was linear, then we would expect that the current
increased proportionally to gate/source voltage, but how does the
current look when we change the gate source voltage?

21.7.2 Gate-source voltage

Below are the conditions I’ve used in the testbench. Notice there
is a 𝑉𝐵 that is the 𝑝− substrate, or bulk, of the transistor. When
we draw symbols of a transistor we don’t always include the bulk
node, because that’s most of the time connected to ground for
NMOS.

But sometimes, we connect the bulk to another voltage, so the bulk

terminal will be in our schematics.

Param Voltage
VGS 0 to 1.8
VDS 1.0
VS 0
VB 0

In the plot below we can see the sweep of the gate voltage.

𝑖(𝑣𝑐𝑢𝑟) = 𝐼𝐷𝑆

10 3
i(vcur)
10 4

10 5

10 6

10 7

10 8

10 9

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

vgate

21.7.3 Inversion level

Define
𝑉𝑒 𝑓 𝑓 ≡ 𝑉𝐺𝑆 − 𝑉𝑡𝑛
, where
𝑉𝑡𝑛
338 21 MOSFETs

is the “threshold voltage”

Veff Inversion level

less than 0 weak inversion or subthreshold
0 moderate inversion
more than 100 mV strong inversion

Weak inversion

The drain current is low, but not zero, when

𝑉𝑒 𝑓 𝑓 << 0

𝑊 𝑉𝑒 𝑓 𝑓 /𝑛𝑉𝑇
𝐼𝐷𝑆 ≈ 𝐼𝐷 0 𝑒 if 𝑉𝐷𝑆 > 3𝑉𝑇
𝐿

𝑛 ≈ 1.5

Moderate inversion

Very useful region in real designs. Hard for hand-calculation. Trust

the model.

Strong inversion



 𝑉𝑒 𝑓 𝑓 𝑉𝐷𝑆 if 𝑉𝐷𝑆 << 𝑉𝑒 𝑓 𝑓




𝑊 𝑉𝑒 𝑓 𝑓 𝑉𝐷𝑆 − 𝑉𝐷𝑆 /2 if 𝑉𝐷𝑆 < 𝑉𝑒 𝑓 𝑓

 2


𝐼𝐷𝑆 = 𝜇𝑛 𝐶 𝑜𝑥
𝐿 
 
2 𝑉𝑒 𝑓 𝑓 if 𝑉𝐷𝑆 > 𝑉𝑒 𝑓 𝑓

 1 2





 21.7 Introduction to behavior 339

21.7.4 Drain source voltage

Param Voltage [V]

VGS 0.5
VDS 0 to 1.8
VS 0
VB 0

𝑖(𝑣𝑐𝑢𝑟) = 𝐼𝐷𝑆
340 21 MOSFETs

1e 5
1.4 i(vcur)

1.2

1.0

0.8

i(vcur)
0.6

0.4

0.2

0.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75
vdrain

21.7.5 Strong inversion



 𝑉𝑒 𝑓 𝑓 𝑉𝐷𝑆 if 𝑉𝐷𝑆 << 𝑉𝑒 𝑓 𝑓




𝑊 𝑉𝑒 𝑓 𝑓 𝑉𝐷𝑆 − 𝑉𝐷𝑆 /2 if 𝑉𝐷𝑆 < 𝑉𝑒 𝑓 𝑓

 2


𝐼𝐷𝑆 = 𝜇𝑛 𝐶 𝑜𝑥
𝐿 

2 𝑉𝑒 𝑓 𝑓 if 𝑉𝐷𝑆 > 𝑉𝑒 𝑓 𝑓

 1 2






1e 5
1.4 i(vcur)

1.2

1.0

0.8
i(vcur)

0.6

0.4

0.2

0.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75
vdrain
21.7 Introduction to behavior 341
342 21 MOSFETs

21.7.6 Low frequency model

𝜕𝐼𝐷𝑆
𝑔𝑚 =
𝜕𝑉𝐺𝑆

1 𝜕𝐼𝐷𝑆
𝑔𝑑𝑠 = =
𝑟 𝑑𝑠 𝜕𝑉𝐷𝑆

21.7.7 Transconductance

Define
𝑊
ℓ = 𝜇𝑛 𝐶 𝑜𝑥
𝐿
and
𝑉𝑒 𝑓 𝑓 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛
 21.7 Introduction to behavior 343

1
𝐼𝐷 = ℓ (𝑉𝑒 𝑓 𝑓 )2
2
and r
2𝐼𝐷
𝑉𝑒 𝑓 𝑓 =
ℓ
and
2𝐼𝐷
ℓ=
𝑉𝑒2𝑓 𝑓

𝜕𝐼𝐷𝑆 p
𝑔𝑚 = = ℓ𝑉𝑒 𝑓 𝑓 = 2ℓ 𝐼𝐷
𝜕𝑉𝐺𝑆

𝐼𝐷 2𝐼𝐷
𝑔𝑚 = ℓ𝑉𝑒 𝑓 𝑓 = 2 𝑉𝑒 𝑓 𝑓 =
𝑉𝑒 𝑓 𝑓
2 𝑉𝑒 𝑓 𝑓

Define
𝑊
ℓ = 𝜇𝑛 𝐶 𝑜𝑥
𝐿
and
𝑉𝑒 𝑓 𝑓 = 𝑉𝐺𝑆 − 𝑉𝑡𝑛

1
𝐼𝐷 = ℓ𝑉𝑒2𝑓 𝑓 [1 + 𝜆𝑉𝐷𝑆 − 𝜆𝑉𝑒 𝑓 𝑓 )]
2

1 𝜕𝐼𝐷 1
= 𝑔𝑑𝑠 = = 𝜆 ℓ𝑉𝑒2𝑓 𝑓
𝑟 𝑑𝑠 𝜕𝑉𝐷𝑆 2

Assume channel length modulation is not there, then

1
𝐼𝐷 = ℓ𝑉𝑒2𝑓 𝑓
2
which means
1
= 𝑔𝑑𝑠 ≈ 𝜆𝐼𝐷
𝑟 𝑑𝑠

21.7.8 Intrinsic gain

Define intrinsic gain as

𝑣 𝑜𝑢𝑡 𝑔𝑚
𝐴= = 𝑔𝑚 𝑟 𝑑𝑠 =
𝑣 𝑖𝑛 𝑔𝑑𝑠

2𝐼𝐷 1 2
𝐴= × =
𝑉𝑒 𝑓 𝑓 𝜆𝐼𝐷 𝜆𝑉𝑒 𝑓 𝑓
344 21 MOSFETs

v(a)

12

10

v(a)
8

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

vgaini

vgaini = Gate Source Voltage =

𝑉𝑒 𝑓 𝑓 + 𝑉𝑡𝑛

21.7.9 High frequency model

 21.7 Introduction to behavior 345

𝐶 𝑔𝑠
and
𝐶 𝑔𝑑



 𝑊 𝐿𝐶 𝑜𝑥 if 𝑉𝐷𝑆 = 0




𝐶 𝑔𝑠 =
3 𝑊 𝐿𝐶 𝑜𝑥 if 𝑉𝐷𝑆 > 𝑉𝑒 𝑓 𝑓
 2






𝐶 𝑔𝑑 = 𝐶 𝑜𝑥 𝑊 𝐿 𝑜𝑣

𝐶 𝑠𝑏
and
𝐶 𝑑𝑏

Both are depletion capacitances

𝐶 𝑠𝑏 = (𝐴 𝑠 + 𝐴 𝑐 ℎ )𝐶 𝑗𝑠

𝐶 𝑗0
𝐶 𝑗𝑠 = q
𝑉𝑆𝐵
1+ Φ0

!
𝑁𝐴 𝑁𝐷
Φ0 = 𝑉𝑇 𝑙𝑛
𝑛 𝑖2

𝐶 𝑑𝑏 = 𝐴 𝑑 𝐶 𝑗𝑑

𝐶 𝑗0
𝐶 𝑗𝑠 = q
𝑉𝐷𝐵
1+ Φ0
346 21 MOSFETs

21.7.10 Be careful with Cgd (blame Miller)

If
𝑌(𝑠) = 1/𝑠𝐶
then
𝑌1 (𝑠) = 1/𝑠𝐶 𝑖𝑛
and
𝑌2 (𝑠) = 1/𝑠𝐶 𝑜𝑢𝑡
where
𝐶 𝑖𝑛 = (1 + 𝐴)𝐶
,
1
𝐶 𝑜𝑢𝑡 = (1 + )𝐶
2

𝐶1 = 𝐶 𝑔𝑑 𝑔𝑚 𝑟 𝑑𝑠

𝐶 𝑔𝑑
can appear to be 10 to 100 times larger!

if gain from input to output is large

 21.8 Weak inversion 347

21.8 Weak inversion

If
𝑉𝑒 𝑓 𝑓 < 0
diffusion currents dominate.

𝑊 𝑉𝑒 𝑓 𝑓 /𝑛𝑉𝑇
𝐼𝐷 = 𝐼𝐷 0 𝑒
𝐿
, where

𝑉𝑇 = 𝑘𝑇/𝑞
,
𝑛 = (𝐶 𝑜𝑥 + 𝐶 𝑗 0 )/𝐶 𝑜𝑥

𝐼𝐷 0 = (𝑛 − 1)𝜇𝑛 𝐶 𝑜𝑥 𝑉𝑇2

𝐼𝐷
𝑔𝑚 =
𝑛𝑉𝑇

Bang for the buck

Subthreshold:

𝑔𝑚 1
= ≈ 25.6 [S/A] @ 300 K
𝐼𝐷 𝑛𝑉𝑇

Strong inversion:

𝑔𝑚 2
=
𝐼𝐷 𝑉𝑒 𝑓 𝑓
348 21 MOSFETs

v(gmid)
25

20

15

v(gmid)
10

0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75
vgmid

21.9 Velocity saturation

Electron speed limit in silicon

𝑣 ≈ 107 𝑐𝑚/𝑠

𝑑𝑉
𝑣 = 𝜇𝑛 𝐸 = 𝜇𝑛
𝑑𝑥

𝜇𝑛 ≈ 100 to 600 𝑐𝑚 2 /𝑉 𝑠
in nanoscale CMOS

109 Rough estimate!

v = µ ×dvdx
speed limit in silicon
speed of light

108

107

1060.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

 21.9 Velocity saturation 349

21.9.1 Square law model

𝑄(𝑥) = 𝐶 𝑜𝑥 𝑉𝑒 𝑓 𝑓 − 𝑉(𝑥)
 

𝑑𝑉
𝑣 = 𝜇𝑛 𝐸 = 𝜇𝑛
𝑑𝑥

𝑊
ℓ = 𝜇𝑛 𝐶 𝑜𝑥
𝐿

 𝑑𝑉
𝐼𝐷 = 𝑊 𝑄(𝑥)𝑣 = ℓ 𝐿 𝑉𝑒 𝑓 𝑓 − 𝑉(𝑥)

𝑑𝑥

𝐼𝐷 𝑑𝑥 = ℓ 𝐿 𝑉𝑒 𝑓 𝑓 − 𝑉(𝑥) 𝑑𝑉
 

∫ 𝐿 ∫ 𝑉𝐷𝑆
𝐼𝐷 𝑑𝑥 = ℓ 𝐿 𝑉𝑒 𝑓 𝑓 − 𝑉(𝑥) 𝑑𝑉
 
0 0

  𝑉𝐷𝑆
1
𝐼𝐷 [𝑥]0𝐿 = ℓ 𝐿 𝑉𝑒 𝑓 𝑓 𝑉 − 𝑉 2
2 0

 
1 2
𝐼𝐷 𝐿 = ℓ 𝐿 𝑉𝑒 𝑓 𝑓 𝑉𝐷𝑆 − 𝑉𝐷𝑆
2

1
@𝑉𝐷𝑆 = 𝑉𝑒 𝑓 𝑓 ⇒ 𝐼𝐷 = ℓ𝑉𝑒2𝑓 𝑓
2

21.9.2 Mobility Degradation

Multiple effects degrade mobility

▶ Velocity saturation
▶ Vertical fields reduce channel depth => more charge-carrier
scattering

𝑊
ℓ = 𝜇𝑛 𝐶 𝑜𝑥
𝐿

𝜇𝑛
𝜇𝑛 _ 𝑒 𝑓 𝑓 =
([1 + (𝜃𝑉𝑒 𝑓 𝑓 )𝑚 ])1/𝑚

1 1
𝐼𝐷 = ℓ𝑉𝑒2𝑓 𝑓
2 ([1 + (𝜃𝑉𝑒 𝑓 𝑓 )𝑚 ])1/𝑚
350 21 MOSFETs

From square law

𝜕𝐼𝐷
𝑔𝑚 = = ℓ𝑉𝑒 𝑓 𝑓
𝜕𝑉𝐺𝑆

With mobility degradation

ℓ
𝑔𝑚(𝑚𝑜𝑏−𝑑𝑒 𝑔) =
2𝜃

21.9.3 What about holes (PMOS)

In PMOS holes are the charge-carrier (electron movement in valence

band)

𝜇 𝑝 < 𝜇𝑛

In intrinsic silicon:

𝜇𝑛 ≤ 1400[𝑐𝑚 2 /𝑉 𝑠] = 0.14[𝑚 2 /𝑉 𝑠]

𝜇𝑝 ≤ 450[𝑐𝑚 2 /𝑉 𝑠] = 0.045[𝑚 2 /𝑉 𝑠]

𝜇 𝑛 ≈ 3𝜇 𝑝

𝑣 𝑛 _𝑚𝑎𝑥 ≈ 2.3 × 105 [𝑚/𝑠]

𝑣 𝑝 _𝑚𝑎𝑥 ≈ 1.6 × 105 [𝑚/𝑠]

Doping (
𝑁𝐴 or𝑁𝐷
) reduces
𝜇

21.10 OTHER

As we make transistors smaller, we find new effects that matter,

and that must be modeled.

which is an opportunity for engineers to come up with cool

names
 21.10 OTHER 351

[Link]

21.10.1 Drain induced barrier lowering (DIBL)

352 21 MOSFETs

21.10.2 Well Proximity Effect (WPE)

21.10.3 Stress effects

Stress PMOS NMOS

Stretch Fz Good Good
Compress Fy OK Good
Compress Fx Good Bad

What can change stress?

 21.10 OTHER 353

21.10.4 Gate current

21.10.5 Hot carrier injection

354 21 MOSFETs

21.10.6 Channel initiated secondary-electron (CHISEL)

21.11 Variability

Provide
𝐼2 = 1𝜇𝐴

Let’s use off-chip resistor

𝑅
, and pick
𝑅
such that
𝐼1 = 1𝜇𝐴

Use
𝑊1 𝑊2
=
𝐿1 𝐿2

What makes
𝐼2 ≠ 1𝜇𝐴
?
 21.11 Variability 355

M1 M2

I1 I2

▶ Voltage variation
▶ Systematic variations
▶ Process variations
▶ Temperature variation
▶ Random variations
▶ Noise

21.11.1 Voltage variation

𝑉𝐷𝐷 − 𝑉𝐺𝑆1
𝐼1 =
𝑅

If
𝑉𝐷𝐷
changes, then current changes.

Fix: Keep
𝑉𝐷𝐷
constant

21.11.2 Systematic variations

If
𝑉𝐷𝑆1 ≠ 𝑉𝐷𝑆2 → 𝐼1 ≠ 𝐼2
356 21 MOSFETs

If layout direction of

𝑀1 ≠ 𝑀2 → 𝐼1 ≠ 𝐼2

If current direction of

𝑀1 ≠ 𝑀2 → 𝐼1 ≠ 𝐼2

If
𝑉𝑆1 ≠ 𝑉𝑆2 → 𝐼1 ≠ 𝐼2

If
𝑉𝐵1 ≠ 𝑉𝐵2 → 𝐼1 ≠ 𝐼2

If
𝑊 𝑃𝐸1 ≠ 𝑊 𝑃𝐸2 → 𝐼1 ≠ 𝐼2

If
𝑆𝑡𝑟𝑒 𝑠𝑠 1 ≠ 𝑆𝑡𝑟𝑒 𝑠𝑠 2 → 𝐼1 ≠ 𝐼2
...

21.11.3 Process variations

Assume strong inversion and active

s
2
𝑉𝑒 𝑓 𝑓 = 𝐼1
𝜇𝑝 𝐶 𝑜𝑥 𝑊
𝐿
,
𝑉𝐺𝑆 = 𝑉𝑒 𝑓 𝑓 + 𝑉𝑡𝑝

q
𝑉𝐷𝐷 − 2
𝐼1 − 𝑉𝑡𝑝
𝑉𝐷𝐷 − 𝑉𝐺𝑆 𝜇𝑝 𝐶 𝑜𝑥 𝑊
𝐿
𝐼1 = =
𝑅 𝑅

𝜇𝑝
,
𝐶 𝑜𝑥
,
𝑉𝑡𝑝
will all vary from die to die, and wafer lot to wafer lot.

21.11.4 Process corners

Common to use 5 corners, or Monte-Carlo process simulation

 21.11 Variability 357

Corner NMOS PMOS

Mtt Typical Typical
Mss Slow Slow
Mff Fast Fast
Msf Slowish Fastish
Mfs Fastish Slowish

21.11.5 Fix process variation

Use calibration: measure error, tune circuit to fix error

For every single chip, measure voltage across known resistor

𝑅1

and tune
𝑅 𝑣𝑎𝑟
such that we get
𝐼1 = 1𝜇𝐴

Be careful with multimeters, they have finite input resistance

(approximately 1 M
Ω
)

21.11.6 Temperature variation

Mobility decreases with temperature

Threshold voltage decreases with temperature.

1
𝐼𝐷 = 𝜇𝑛 𝐶 𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑡𝑛 )2
2

High
𝐼𝐷 =
fast digital circuits

Low
𝐼𝐷 =
slow digital circuits

What is fast? High temperature or low temperature?

358 21 MOSFETs

21.11.7 It depends on
𝑉𝐷𝐷

Fast corner - Mff (high mobility, low threshold voltage) - High

𝑉𝐷𝐷

- High or low temperature

Slow corner - Mss (low mobility, high threshold voltage) - Low

𝑉𝐷𝐷

- High or low temperature

21.11.8 How do we fix temperature variation?

Accept it, or don’t use this circuit.

If you need stability over temperature, use 7.3.2 and 7.3.4 in CJM
(SUN_BIAS_GF130N)

21.11.9 Random Variation

𝑊
ℓ = 𝜇𝑝 𝐶 𝑜𝑥
𝐿

1
𝐼𝐷 = ℓ (𝑉𝐺𝑆 − 𝑉𝑡𝑝 )2
2

Due to doping , length, width,

𝐶 𝑜𝑥

,
𝑉𝑡𝑝
, . . . random varation

ℓ1 ≠ ℓ2

𝑉𝑡𝑝 1 ≠ 𝑉𝑡𝑝 2

As a result
𝐼1 ≠ 𝐼2
, but we can make them close.
 21.11 Variability 359

21.11.10 Pelgrom’s‗ law

Given a random gaussian process parameter

Δ𝑃

with zero mean, the variance is given by

𝐴2𝑃
𝜎2 (Δ𝑃) = + 𝑆𝑃2 𝐷 2
𝑊𝐿

where
𝐴𝑃
and
𝑆𝑃
are measured, and
𝐷
is the distance between devices
Assume closely spaced devices (

𝐷≈0

)
𝐴2𝑃
⇒ 𝜎 (Δ𝑃) =
2
𝑊𝐿

21.11.11 Transistors with same

𝑉𝐺𝑆
†

𝜎𝐼2𝐷
" #
𝜎ℓ2
2
1 𝑔𝑚
= 𝜎𝑣𝑡
2
+
𝐼𝐷
2 𝑊𝐿 𝐼𝐷 ℓ

Valid in weak, moderate and strong inversion

𝜎𝐼2𝐷
" #
𝜎ℓ2
2
1 𝑔𝑚
= 𝜎𝑣𝑡
2
+
𝐼𝐷
2 𝑊𝐿 𝐼𝐷 ℓ
𝜎𝐼𝐷 1
∝√
𝐼𝐷 𝑊𝐿

‗ M. J. M. Pelgrom, C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties

of MOS transistors,” IEEE J. Solid-State Cir- cuits, vol. 24, no. 5, pp. 1433–1440,
Oct. 1989.
† Peter Kinget, see CJM
360 21 MOSFETs

Assume
𝜎𝐼𝐷
= 10%
𝐼𝐷
, We want
5%
, how much do we need to change WL?

𝜎𝐼 𝐷
𝐼𝐷 1 1
∝ √ =√
2 2 𝑊𝐿 4𝑊 𝐿

We must quadruple the area to half the standard deviation

1%
would require 100 times the area

M1 M2

I1 I2

R1

Rvar

21.11.12 What else can we do?

𝜎𝐼2𝐷
" #
𝜎ℓ2
2
1 𝑔𝑚
= 𝜎𝑣𝑡
2
+
𝐼𝐷
2 𝑊𝐿 𝐼𝐷 ℓ

Strong inversion
𝑔𝑚 1
⇒ = = 𝑙𝑜𝑤
𝐼𝐷 2𝑉𝑒 𝑓 𝑓
 21.11 Variability 361

Weak inversion
𝑔𝑚 𝑞
⇒ = ≈ 25
𝐼𝐷 𝑛 𝑘𝑇

Current mirrors achieve best matching in strong inversion

𝜎𝐼2𝐷
" #
𝜎ℓ2
2
1 𝑔𝑚
= 𝜎𝑣𝑡
2
+
𝐼𝐷
2 𝑊𝐿 𝐼𝐷 ℓ

" #
1 𝜎
2 ℓ
2
𝜎𝐼2𝐷 = 𝑔𝑚 2 𝜎𝑣𝑡
2
+ 𝐼𝐷
𝑊𝐿 ℓ

Offset voltage for a differential pair

𝑖 𝑜 = 𝑖 𝑜+ − 𝑖 𝑜− = 𝑔𝑚 𝑣 𝑖 = 𝑔𝑚 (𝑣 𝑖+ − 𝑣 𝑖− )

𝜎𝐼2𝐷
" #
1 𝐼𝐷
2
𝜎ℓ2
𝜎𝑣2𝑖 = = 𝜎 2
+
𝑔𝑚 2 𝑊 𝐿 𝑣𝑡 𝑔𝑚 2 ℓ

High
𝑔𝑚
𝐼𝐷
is better (best in weak inversion)

io− io+

vi+ vi−

21.11.13 Transistor Noise

Thermal noise Random scattering of carriers, generation-

recombination in channel?

𝑃𝑆𝐷𝑇𝐻 ( 𝑓 ) = Constant
362 21 MOSFETs

Popcorn noise Carriers get “stuck” in oxide traps (dangling bonds)

for a while. Can cause a short-lived (seconds to minutes) shift in
threshold voltage

𝐴
𝑃𝑆𝐷𝐺𝑅 ( 𝑓 ) ∝ Lorentzian shape ≈
𝑓2
1+ 𝑓0

Flicker noise Assume there are many sources of popcorn noise

at different energy levels and time constants, then the sum of the
spectral densities approaches flicker noise.

1
𝑃𝑆𝐷 𝑓 𝑙𝑖𝑐 𝑘𝑒𝑟 ( 𝑓 ) ∝
𝑓
 Circuits 22
22.1 Current Mirrors . . 363
22.1 Current Mirrors 22.1.1 Normal current
mirror . . . . . . . . 363
MOSFETs need a current for the transistor to be biased in the 22.1.2 Source degeneration 366
22.1.3 Output resistance . 367
correct operating region. The current must come from somewhere,
we’ll look at bias generators later. Usually there is a central bias 22.2 Amplifiers . . . . . . 370
circuit that provides a single, good, reference current. 22.3 Source follower . . 370
22.3.1 Output resistance . 370
On an IC, however, there will be many circuits, and they all need 22.3.2 Why use a source
a bias current (usually). As such, we need a circuit to copy a follower? . . . . . . . 371
current. 22.4 Common gate . . . 372
22.4.1 Input resistance . . 373
In the figure below you can see a selection of current mirros. They 22.4.2 Output resistance . 373
all do the same thing. Try to ensure that 𝑖 𝑖 and 𝑖 𝑜 are the same 22.4.3 Gain . . . . . . . . . 373
current. 22.5 Common source . . 374
22.5.1 Gain . . . . . . . . . 375
Which one we choose is usually determined by what we mean by 22.5.2 Why common
𝑖 𝑖 = 𝑖 𝑜 . Do we mean “within ± 10 %”, or “within ± 2 %”. source? . . . . . . . . 376
22.6 Differential pair . . 376
ii
22.6.1 Diff pairs are cool . 377
ii io ii io io

M1 M2 M3 M4 M3 M4
vb
ii io

M1 M2 M3 M4 M1 M2 M1 M2

a) “normal” b) Self Cascode c) Cascode d) Lazy Cascode

22.1.1 Normal current mirror

The normal current mirror consists of a diode connected transistor

( 𝑀1 ) and a common source transistor 𝑀2 .

If we assume infinite output resistance of the MOSFETs, then the

drain voltage does not affect the current.

If the two transistors are the same size, threshold voltage, mobility,
etc, and they have the same gate-source voltage, then the current
in them must be the same.

A current pushed into 𝑀1 will cause the 𝑉𝐺𝑆1 to rise, and at some
point, find a stable point where the current pushed in is equal to
the current in 𝑀1

𝑀2 will see the same 𝑉𝐺𝑆1 = 𝑉𝐺𝑆2 so the current will be the same,
provided the voltage at 𝑖 𝑜 is sufficient to pinch-off the channel of
𝑀2 , or the 𝑉𝐷𝑆2 ≈ 3 𝑘𝑇/𝑞 if the transitor is in weak-inversion.
364 22 Circuits

ii io

M1 M2

[Link] Input resistance

To see the small signal input resistance we can apply a test voltage
to the diode connected resistor, as shown in the figure below.

Observe the current

𝑖 𝑦 = 𝑔𝑑𝑠 𝑣 𝑦 + 𝑔𝑚 𝑣 𝑦

While the input resistance

𝑣𝑦 1
𝑟 𝑖𝑛 = =
𝑖𝑦 𝑔𝑚 + 𝑔𝑑𝑠
 22.1 Current Mirrors 365

which, assuming 𝑔𝑑𝑠 >> 𝑔𝑚 , reduces to

1
𝑟 𝑖𝑛 ≈
𝑔𝑚
.

Assume now I apply 1 𝜇𝐴 current to the diode connected transistor,

and the 𝑔𝑚 = 1 𝜇𝑆 .

1 𝜇𝐴
Would the voltage be 𝑣 𝑦 = 𝑟 𝑖𝑛 𝑖 𝑦 = 1 𝜇𝑆 = 1 𝑉 ? NO! It’s important to
understand the difference between the small signal input resistance,
and the large signal impedance.

The large signal impedance is a highly non-linear function (we’ve

seen before that the current in a MOSFET has both an exponential,
and a square-law, and sometimes a linear with voltage), as such,
there is no single function describing what the gate-source voltage
will be.

To see the DC voltage, apply a current in SPICE, and use a simulator

to find the voltage.

[Link] Output resistance

366 22 Circuits

[Link] Current gain

22.1.2 Source degeneration

ii io

M1 M2

M3 M4

What is the operating region of M3 and M4?

What is the operating region of M1 and M2?

[Link] Input resistance

M1 and M2 are in linear region, can be simplified to resistors

 22.1 Current Mirrors 367

1
𝑟 𝑖𝑛 = + 𝑅𝑠
𝑔𝑚 1

ii io

M1 M2

Rs Rs

22.1.3 Output resistance

𝑣 𝑔𝑠 = −𝑣 𝑠
,
𝑣𝑠 = 𝑖𝑥 𝑅𝑠
368 22 Circuits

,
𝑣𝑥
𝑟 𝑜𝑢𝑡 =
𝑖𝑥

𝑣𝑥 − 𝑣𝑠
𝑖 𝑥 = 𝑔𝑚 2 𝑣 𝑔𝑠 +
𝑟 𝑑𝑠 2

𝑣𝑥 − 𝑖𝑥 𝑅𝑠
𝑖 𝑥 = −𝑖 𝑥 𝑔𝑚 2 𝑅 𝑠 +
𝑟 𝑑𝑠 2

𝑣 𝑥 = 𝑖 𝑥 𝑟 𝑑𝑠 2 + 𝑅 𝑠 (𝑔𝑚 2 𝑟 𝑑𝑠 2 + 1)
 

Rearranging

𝑟 𝑜𝑢𝑡 = 𝑟 𝑑𝑠 2 [1 + 𝑅 𝑠 (𝑔𝑚 1 + 𝑔𝑑𝑠 2 )] ≈ 𝑟 𝑑𝑠 2 [1 + 𝑔𝑚 1 𝑅 𝑠 ]

[Link] Cascode output resistance

From source degeneration (ignoring bulk effect)

𝑟 𝑜𝑢𝑡 = 𝑟 𝑑𝑠 4 [1 + 𝑅 𝑠 (𝑔𝑚 4 + 𝑔𝑑𝑠 4 )]

𝑅 𝑆 = 𝑟 𝑑𝑠 2

𝑟 𝑜𝑢𝑡 = 𝑟 𝑑𝑠 4 [1 + 𝑟 𝑑𝑠 2 (𝑔𝑚 4 + 𝑔𝑑𝑠 4 )]

𝑟 𝑜𝑢𝑡 ≈ 𝑟 𝑑𝑠 2 (𝑟 𝑑𝑠 4 𝑔𝑚 4 )
 22.1 Current Mirrors 369

ii io

M3 M4
vb

M1 M2

[Link] Active cascodes

𝑟 𝑜𝑢𝑡 ≈ 𝑟 𝑑𝑠 2 (𝐴𝑟 𝑑𝑠 4 𝑔𝑚 4 )
370 22 Circuits

22.2 Amplifiers

22.3 Source follower

Input resistance
≈∞

Gain
𝑣𝑜
𝐴=
𝑣𝑖

Output resistance
𝑟 𝑜𝑢𝑡

22.3.1 Output resistance

𝑖 𝑜 = 𝑣 𝑜 (𝑔𝑑𝑠 + 𝑔𝑠 ) − 𝑔𝑚 𝑣 𝑖 + 𝑣 𝑜 𝑔𝑚
 22.3 Source follower 371

𝑣𝑖 = 0

𝑖 𝑜 = 𝑣 𝑜 (𝑔𝑑𝑠 + 𝑔𝑠 + 𝑔𝑚 )

𝑣𝑜 1
𝑟 𝑜𝑢𝑡 = =
𝑖𝑜 𝑔𝑚 + 𝑔𝑑𝑠 + 𝑔𝑠

1
𝑟 𝑜𝑢𝑡 ≈
𝑔𝑚

22.3.2 Why use a source follower?

Assume 100 electrons

Δ𝑉 = 𝑄/𝐶 = −1.6 × 10−19 × 100/(1 × 10−15 ) = −16 mV

Δ𝑉 = 𝑄/𝐶 = −1.6 × 10−19 × 100/(1 × 10−12 ) = −16 uV

372 22 Circuits

22.4 Common gate

Input resistance

Gain

Output resistance
 22.4 Common gate 373

22.4.1 Input resistance

𝑖 = 𝑔𝑚 𝑣 + 𝑔𝑑𝑠 𝑣

1 1
𝑟 𝑖𝑛 = ≈
𝑔𝑚 + 𝑔𝑑𝑠 𝑔𝑚

However, we’ve ignored load resistance.

𝑅𝐿
 
1
𝑟 𝑖𝑛 ≈ 1+
𝑔𝑚 𝑟 𝑑𝑠

22.4.2 Output resistance

22.4.3 Gain
𝑣𝑜 − 𝑣𝑖
𝑖 𝑜 = −𝑔𝑚 𝑣 𝑖 +
𝑟 𝑑𝑠

𝑖𝑜 = 0
374 22 Circuits

0 = −𝑔𝑚 𝑣 𝑖 𝑟 𝑑𝑠 + 𝑣 𝑜 − 𝑣 𝑖

𝑣 𝑖 (1 + 𝑔𝑚 𝑟 𝑑𝑠 ) = 𝑣 𝑜

𝑣𝑜
= 1 + 𝑔𝑚 𝑟 𝑑𝑠
𝑣𝑖

We’ve ignored bulk effect (

𝑔𝑠
), source resistance (
𝑅𝑆
) and load resistance (
𝑅𝐿
)

(𝑔𝑚 + 𝑔𝑠 + 𝑔𝑑𝑠 )(𝑅 𝐿 ||𝑟 𝑑𝑠 )

𝐴=
𝑔𝑚 +𝑔𝑠 +𝑔𝑑𝑠
 
1 + 𝑅𝑆 1+𝑅 𝐿 /𝑟 𝑑𝑠

If
𝑅 𝐿 >> 𝑟 𝑑𝑠
,
𝑅𝑆 = 0
and
𝑔𝑠 = 0

(𝑔𝑚 + 𝑔𝑑𝑠 )𝑟 𝑑𝑠
𝐴= = 1 + 𝑔𝑚 𝑟 𝑑𝑠
1

22.5 Common source

𝑟 𝑖𝑛 ≈ ∞

𝑟 𝑜𝑢𝑡 = 𝑟 𝑑𝑠
, it’s same circuit as the output of a current mirror

Gain
 22.5 Common source 375

22.5.1 Gain

𝑣𝑜
𝑖 𝑜 = 𝑔𝑚 𝑣 𝑖 +
𝑟 𝑑𝑠

𝑖𝑜 = 0

𝑣𝑜
−𝑔𝑚 𝑣 𝑖 =
𝑟 𝑑𝑠

𝑣𝑜
= −𝑔𝑚 𝑟 𝑑𝑠
𝑣𝑖
376 22 Circuits

22.5.2 Why common source?

22.6 Differential pair

Input resistance
𝑟 𝑖𝑛 ≈ ∞

Gain
𝐴 = 𝑔𝑚 𝑟 𝑑𝑠

Output resistance
𝑟 𝑜𝑢𝑡 = 𝑟 𝑑𝑠

Best analyzed with T model of transistor (see CJM page 31)

 22.6 Differential pair 377

22.6.1 Diff pairs are cool

Can choose between

𝑣 𝑜 = 𝑔𝑚 𝑟 𝑑𝑠 𝑣 𝑖

and

𝑣 𝑜 = −𝑔𝑚 𝑟 𝑑𝑠 𝑣 𝑖

by flipping input (or output) connections

 Integrated Passives 23
23.1 Metal in ICs is not wire in schematic 23.1 Metal in ICs is not
wire in schematic . 379
23.2 Resistors . . . . . . . 380
Metal wires in an integrated circuit comes in two types, copper 23.2.1 Polysilicon . . . . . . 380
and aluminium. 23.2.2 Diffusion . . . . . . . 381
23.2.3 Metal . . . . . . . . . 381
Most of the routing layers will be copper. To ensure that the copper
23.3 Capacitors . . . . . . 382
ions don’t diffuse into the silicon-oxide a barrier material surrounds 23.3.1 What is S, M, L, XL
all copper interconnect. on a chip? . . . . . . 382
23.3.2 Metal-Oxide-Metal
Copper is too stiff to be wire-bonded. As such, the top layer metals
finger capacitors . . 382
would be aluminium. 23.3.3 MOS capacitors . . . 383
23.3.4 Varactors . . . . . . . 384
Since the routing is so small, we have to care about the parasitic
properties of the routing. Below is a table with some common 23.4 Inductors . . . . . . 384
quantities for copper. For example, if we have 1000 𝜇m metal wire 23.5 Variation in passives385
with 1 𝜇m width, then it would be approximately 150 Ω, 1 nH , 1 23.6 Relative precision . 385
pF and tolerate a maximum of 1 mA DC current. 23.7 Diodes . . . . . . . . 387

Parameter Typ. Value Unit

Resistance 150 mΩ/□
Capacitance 1 fF/𝜇m
Inductance 1 nH/mm
Max DC current 1 mA/□

The type of circuit we have determine what we must simulate.

Everything needs to be simulated with parasitc capacitance and
max current. Only RF, however, usually needs to be simulated with
resistance, capacitance, inductance and maximum current.

Circuit type Must simulate/know

All C Imax
Analog, Power R C Imax
Some RF, Some Power R L C Imax

To simulate the effects of parasitics, we need a description of the

technology. A Process Design Kit (PDK). Most PDKs are closely
guarded secrets, as they describe many things about the way the
foundry makes the integrated circuits.
Some PDKs are open source, however, see Skywater 130 nm and
IHP-Open-PDK
In addition to the PDK, we need tools that can calculate from the
layout the parasitic elements. Some of the tools are
Layout parasitic extraction tools

▶ Calibre xRC
380 23 Integrated Passives

▶ Synopsys StarRC
▶ Cadence Quantus
▶ Magic VLSI

3D EM Simulators

▶ Keysight ADS
▶ HFSS

Transistor CAD (TCAD)

▶ Synopsys TCAD

23.2 Resistors

Sometimes we want a specific resistance. In general, any resistance

on IC will vary in absolute value by maybe up to ± 20 %. The
relative size, however, can be controlled to within 0.1 %.

In other words, you can’t rely on a 1 kOhm resistor actually being 1

kOhm, it might be 0.8 kOhm. If you have two, however, you can
trust that both of them will be 0.8 kOhm.

That’s why almost all analog circuits rely on the relative sizes of
passives, not the absolute value. If a circuit does rely on absolute
values, then it usually needs to be trimmed in production.

23.2.1 Polysilicon

Can be both N-doped, and P-doped

Often with two flavors, with, and without silicide

Silicide reduces resistance of polysilicon

 23.2 Resistors 381

23.2.2 Diffusion

Use doped region as resistor

Usually without silicide

Non-linear capacitance

Tricky temperature dependence

23.2.3 Metal

Usually too low omhic to be a useful resistor

Useful for “separating nets” in schematic and layout

Must be considered for power supply and ground routing (high

currents)
382 23 Integrated Passives

23.3 Capacitors

23.3.1 What is S, M, L, XL on a chip?

nRF52832
3200𝜇𝑚 × 3000𝜇𝑚 = 9600 𝑘𝜇𝑚 2

S
< 5 𝑘𝜇𝑚 2
M
< 50 𝑘𝜇𝑚 2
L
< 200 𝑘𝜇𝑚 2
XL
> 200 𝑘𝜇𝑚 2

23.3.2 Metal-Oxide-Metal finger capacitors

Unit capacitance
≈ 1 𝑓 𝐹/𝜇𝑚 2 /𝑙𝑎 𝑦𝑒𝑟

10 𝑝𝐹 = 100𝜇𝑚 × 100𝜇𝑚 = 10 𝑘𝜇𝑚 2

 23.3 Capacitors 383

M1 M2 M3 M4 (a)

C1B

C4

C8

C2

C16

C1A
CT OP
(b)

23.3.3 MOS capacitors

dicex/sim/spice/NCHIO/[Link]
* gate cap

.include ../../../models/ptm_130.spi

vdrain D 0 dc 1
vgaini G 0 dc 0.5
vbulk B 0 dc 0
vcur S 0 dc 0

M1 D G S B nmos w=1u l=1u

.op

Moscap is
≈ 10 𝑓 𝐹/𝜇𝑚 2

10 𝑝𝐹 = 31𝜇𝑚 × 31𝜇𝑚 ≈ 1 𝑘𝜇𝑚 2

dicex/sim/spice/NCHIO/[Link]
Device m1:
Vgs (gate-source voltage) [V] : 0.5
Vgd (gate-drain voltage) [V] : -0.5
Vds (drain-source voltage) [V] : 1
384 23 Integrated Passives

Vbs (bulk-source voltage) [V] : 1.90808e-12

Vbd (bulk-drain voltage) [V] : -1
Id (drain current) [A] : 7.32634e-06
Is (source current) [A] : -7.32633e-06
Ibd (bulk-drain current) [A] : -1.01e-12
Ibs (bulk-source current) [A] : 9.581e-25
Vt (threshold voltage) [V] : 0.378198
Vgt (gate overdrive voltage) [V] : 0.121802
Vgsteff (effective vgt) [V] : 0.12515
Gm (transconductance) [S] : 8.44164e-05
Gmb (bulk bias transconductance) [S] : 2.00071e-05
Ueff (mobility) [cmˆ2/Vs] : 417.675
Gds (channel conductance) [S] : 1.95043e-07
Rds (output resistance) [Ohm] : 5.12708e+06
Vdsat (drain saturation voltage) [V] : 0.14171
IC (inversion coefficient) [] : 4.42478
Cgs (gate-source capacitance) [F] : 9.98457e-15
Csg (source-gate capacitance) [F] : 5.86932e-15
Cgd (gate-drain capacitance) [F] : 3.98239e-16
Cdg (drain-gate capacitance) [F] : 3.91086e-15
Cds (drain-source capacitance) [F] : 4.30968e-15
Cgg (gate-gate capacitance) [F] : 1.05198e-14
Cdd (drain-drain capacitance) [F] : 1.05198e-14
Css (source-source capacitance) [F] : 0
Cgb (gate-bulk capacitance) [F] : 1.05198e-14
Cbg (bulk-gate capacitance) [F] : 1.74123e-15
Cbs (bulk-source capacitance) [F] : 8e-16
Cbd (bulk-drain capacitance) [F] : 3.97768e-16

23.3.4 Varactors

A varactor is a “variable capacitor”, usually it’s a device that varies

the capacitance with the voltage across the device.

23.4 Inductors

Usually two top metals, because they are thick (low ohmic)

Use foundry model

3D electro magnetic simulation often needed

 23.5 Variation in passives 385

23.5 Variation in passives

Absolute value for resistors and capacitors

≈ ±10

% to
±20
%

Relative precision for closely spaced devices

0.1 % to 1 %

Relative precision for devices on same die

>2

% or more

23.6 Relative precision

Resistors and Capacitors can be matched extremely well

386 23 Integrated Passives

𝑖3 = 0 = 𝑖1 − 𝑖2
𝑉𝑖 − 𝑉𝑜 𝑉𝑜
0= −
𝑅 1/𝑠𝐶

0 = 𝑉𝑖 − 𝑉𝑜 − 𝑉𝑜 𝑠𝑅𝐶
𝑉𝑜 (1 + 𝑠𝑅𝐶) = 𝑉𝑖

𝑉𝑜 1
=
𝑉𝑖 1 + 𝑠𝑅𝐶
 23.7 Diodes 387

Assume standard deviation (

)‗ of

𝜎𝑅 = 20
%,
𝜎𝐶 = 20
%

√
𝜎𝑅𝐶 = 0.22 + 0.22 = 28
%

23.7 Diodes

Many, many ways

Reverse bias diodes to ground are useful for signals with long
routing to transistor gate. Protects gate from breakdown during
chemical mechanical polish.

‗ If
you don’t remember how standard deviation works, read Introduction to
mathematics of noise sources
 SPICE 24
24.1 SPICE . . . . . . . . 389
24.1 SPICE
24.2 Simulation Program
with Integrated
Circuit Emphasis . 389
24.2 Simulation Program with Integrated 24.2.1 Today . . . . . . . . . 389
Circuit Emphasis 24.2.2 But . . . . . . . . . . 390
24.2.3 Sources . . . . . . . . 391
24.2.4 Passives . . . . . . . 392
To manufacture an integrated circuit we have to be able to predict 24.2.5 Transistor Models . 392
how it’s going to work. The only way to predict is to rely on our 24.2.6 Transistors . . . . . . 394
knowledge of physics, and build models of the real world in our 24.2.7 Foundries . . . . . . 394
computers. 24.3 Find right transistor
sizes . . . . . . . . . 394
One simulation strategy for a model of the real world, which 24.3.1 Use unit size tran-
absolutely every single integrated circuit in the world has used to sistors for analog
come into existence, is SPICE. design . . . . . . . . 395
24.3.2 What about gm/Id ? 395
Published in 1973 by Nagel and Pederson 24.3.3 Characterize the
transistors . . . . . . 396
SPICE (Simulation Program with Integrated Circuit Emphasis)
24.4 More information . 396
24.5 Analog Design . . . 396
24.6 Demo . . . . . . . . . 396

24.2.1 Today

There are multiple SPICE programs that has been written, but
they all work in a similar fashion. There are expensive ones, closed
source, and open source.

Some are better at dealing with complex circuits, some are faster,
and some are more accurate. If you don’t have money, then start
with ngspice.

Commercial Cadence Spectre Siemens Eldo Synopsys HSPICE

390 24 SPICE

Free Aimspice Analog Devices LTspice

Open Source ngspice

24.2.2 But

All SPICE simulators understand the same language (yes, even

spectre can speak SPICE). We write our testbenches in a text file,
and give it to the SPICE program. That’s the same for all programs.
Some may have built fancy GUI’s to hide the fact that we’re really
writing text files, but text files is what is under the hood.

Pretty much the same usage model as 48 years ago

<spice program> [Link]

for example

ngspice [Link]

Or in the most expensive analog tool (Cadence Spectre)

spectre [Link] +escchars +log ../psf/[Link]

-format psfxl -raw ../psf +aps +lqtimeout 900 -maxw 5 -maxn 5 -
/tmp/wulff/virtuoso/TB_SUN_BIAS_GF130N/TB_SUN_BIAS/maestro/result
+logstatus

The expensive tools have built graphical user interface around the
SPICE simulator to make it easier to run multiple scenarios.

Corner Typical Fast Slow All

Mosfet Mtt Mff Mss Mff,Mfs,Msf,Mss
Resistor Rt Rl Rh Rl,Rh
Capacitors Ct Cl Ch Cl,Ch
Diode Dt Df Ds Df,Ds
Bipolar Bt Bf Bs Bf,Bs
Temperature Tt Th,Tl Th,Tl Th,Tl
Voltage Vt Vh,Vl Vh,Vl Vh,Vl
 24.2 Simulation Program with Integrated Circuit Emphasis 391

I’m a fan of launching multiple simulations from the command

line. I don’t like GUI’s. As such, I wrote cicsim, and that’s what I
use in the video and demo.

24.2.3 Sources

The SPICE language is a set of conventions for how to write the

text files. In general, it’s one line, one command (although, lines
can be continued with a +).

I’m not going to go through an extensive tutorial in this document,

and there are dialects with different SPICE programs. You’ll find
more info at ngspice

[Link] Independent current sources

Infinite output impedance, changing voltage does not change

current

I<name> <from> <to> dc <number> ac <number>

I1 0 VDN dc In
I2 VDP 0 dc Ip

[Link] Independent voltage source

Zero output impedance, changing current does not change volt-

age
392 24 SPICE

V<name> <+> <-> dc <number> ac <number>

V2 VSS 0 dc 0
V1 VDD 0 dc 1.5

24.2.4 Passives

Resistors

R<name> <node 1> <node 2> <value>

R1 N1 N2 10k
R2 N2 N3 1Meg
R3 N3 N4 1G
R4 N4 N5 1T

Capacitors

C<name> <node 1> <node 2> <value>

C1 N1 N2 1a
C2 N1 N2 1f
C4 N1 N2 1p
C3 N1 N2 1n
C5 N1 N2 1u

24.2.5 Transistor Models

Needs a model file the transistor model

BSIM (Berkeley Short-channel IGFET Model) [Link]

[Link]/models/bsim4/
 24.2 Simulation Program with Integrated Circuit Emphasis 393

Drain

Gate M1

Source
284 parameters in BSIM 4.5

.MODEL N1 NMOS LEVEL=14 VERSION=4.5.0 BINUNIT=1 PARAMCHK=1 MOBMOD=0

CAPMOD=2 IGCMOD=1 IGBMOD=1 GEOMOD=1 DIOMOD=1 RDSMOD=0 RBODYMOD=0 RGATEMOD=3
PERMOD=1 ACNQSMOD=0 TRNQSMOD=0 TEMPMOD=0 TNOM=27 TOXE=1.8E-009
TOXP=10E-010 TOXM=1.8E-009 DTOX=8E-10 EPSROX=3.9 WINT=5E-009 LINT=1E-009
LL=0 WL=0 LLN=1 WLN=1 LW=0 WW=0 LWN=1 WWN=1 LWL=0 WWL=0 XPART=0
TOXREF=1.4E-009 SAREF=5E-6 SBREF=5E-6 WLOD=2E-6 KU0=-4E-6 KVSAT=0.2
KVTH0=-2E-8 TKU0=0.0 LLODKU0=1.1 WLODKU0=1.1 LLODVTH=1.0 WLODVTH=1.0
LKU0=1E-6 WKU0=1E-6 PKU0=0.0 LKVTH0=1.1E-6 WKVTH0=1.1E-6 PKVTH0=0.0
STK2=0.0 LODK2=1.0 STETA0=0.0 LODETA0=1.0 LAMBDA=4E-10 VSAT=1.1E 005
VTL=2.0E5 XN=6.0 LC=5E-9 RNOIA=0.577 RNOIB=0.37
LINTNOI=1E-009 WPEMOD=0 WEB=0.0 WEC=0.0 KVTH0WE=1.0 K2WE=1.0 KU0WE=1.0
SCREF=5.0E-6 TVOFF=0.0 TVFBSDOFF=0.0 VTH0=0.25 K1=0.35 K2=0.05
K3=0 K3B=0 W0=2.5E-006 DVT0=1.8 DVT1=0.52 DVT2=-0.032 DVT0W=0 DVT1W=0
DVT2W=0 DSUB=2 MINV=0.05 VOFFL=0 DVTP0=1E-007 DVTP1=0.05 LPE0=5.75E-008
LPEB=2.3E-010 XJ=2E-008 NGATE=5E 020 NDEP=2.8E 018 NSD=1E 020 PHIN=0
CDSC=0.0002 CDSCB=0 CDSCD=0 CIT=0 VOFF=-0.15 NFACTOR=1.2 ETA0=0.05
ETAB=0 UC=-3E-011 VFB=-0.55 U0=0.032 UA=5.0E-011 UB=3.5E-018 A0=2
AGS=1E-020 A1=0 A2=1 B0=-1E-020 B1=0 KETA=0.04 DWG=0 DWB=0 PCLM=0.08
PDIBLC1=0.028 PDIBLC2=0.022 PDIBLCB=-0.005 DROUT=0.45 PVAG=1E-020
DELTA=0.01 PSCBE1=8.14E 008 PSCBE2=5E-008 RSH=0 RDSW=0 RSW=0 RDW=0
FPROUT=0.2 PDITS=0.2 PDITSD=0.23 PDITSL=2.3E 006 RSH=0 RDSW=50 RSW=150
RDW=150 RDSWMIN=0 RDWMIN=0 RSWMIN=0 PRWG=0 PRWB=6.8E-011 WR=1
ALPHA0=0.074 ALPHA1=0.005 BETA0=30 AGIDL=0.0002 BGIDL=2.1E 009 CGIDL=0.0002
EGIDL=0.8 AIGBACC=0.012 BIGBACC=0.0028 CIGBACC=0.002 NIGBACC=1
AIGBINV=0.014 BIGBINV=0.004 CIGBINV=0.004 EIGBINV=1.1 NIGBINV=3 AIGC=0.012
BIGC=0.0028 CIGC=0.002 AIGSD=0.012 BIGSD=0.0028 CIGSD=0.002 NIGC=1
POXEDGE=1 PIGCD=1 NTOX=1 VFBSDOFF=0.0 XRCRG1=12 XRCRG2=5 CGSO=6.238E-010
CGDO=6.238E-010 CGBO=2.56E-011 CGDL=2.495E-10 CGSL=2.495E-10
CKAPPAS=0.03 CKAPPAD=0.03 ACDE=1 MOIN=15 NOFF=0.9 VOFFCV=0.02 KT1=-0.37
KT1L=0.0 KT2=-0.042 UTE=-1.5 UA1=1E-009 UB1=-3.5E-019 UC1=0 PRT=0
AT=53000 FNOIMOD=1 TNOIMOD=0 JSS=0.0001 JSWS=1E-011 JSWGS=1E-010 NJS=1
IJTHSFWD=0.01 IJTHSREV=0.001 BVS=10 XJBVS=1 JSD=0.0001 JSWD=1E-011
JSWGD=1E-010 NJD=1 IJTHDFWD=0.01 IJTHDREV=0.001 BVD=10 XJBVD=1 PBS=1 CJS=0.0005
MJS=0.5 PBSWS=1 CJSWS=5E-010 MJSWS=0.33 PBSWGS=1 CJSWGS=3E-010 MJSWGS=0.33
PBD=1 CJD=0.0005 MJD=0.5 PBSWD=1 CJSWD=5E-010 MJSWD=0.33 PBSWGD=1
CJSWGD=5E-010MJSWGD=0.33 TPB=0.005 TCJ=0.001 TPBSW=0.005 TCJSW=0.001 TPBSWG=0.005
TCJSWG=0.001 XTIS=3 XTID=3 DMCG=0E-006 DMCI=0E-006 DMDG=0E-006 DMCGT=0E-007 DWJ=0.0E-008 XGW=0E-007
XGL=0E-008 RSHG=0.4 GBMIN=1E-010 RBPB=5 RBPD=15 RBPS=15 RBDB=15 RBSB=15 NGCON=1
JTSS=1E-4 JTSD=1E-4 JTSSWS=1E-10 JTSSWD=1E-10 JTSSWGS=1E-7 JTSSWGD=1E-7 NJTS=20.0
NJTSSW=20 NJTSSWG=6 VTSS=10 VTSD=10 VTSSWS=10 VTSSWD=10 VTSSWGS=2 VTSSWGD=2
XTSS=0.02 XTSD=0.02 XTSSWS=0.02 XTSSWD=0.02 XTSSWGS=0.02 XTSSWGD=0.02
394 24 SPICE

24.2.6 Transistors

M<name> <drain> <gate> <source> <bulk> <modelname> [parameters]

M1 VDN VDN VSS VSS nmos W=0.6u L=0.15u

M2 VDP VDP VDD VDD pmos W=0.6u L=0.15u

24.2.7 Foundries

Each foundry has their own SPICE models bacause the transistor
parameters depend on the exact physics of the technology!

[Link]

24.3 Find right transistor sizes

Assume active (
𝑉𝑑𝑠 > 𝑉𝑒 𝑓 𝑓
in strong inversion, or
𝑉𝑑𝑠 > 3𝑉𝑇
in weak inversion). For diode connected transistors, that is always
true.

Weak inversion:
𝑊 𝑉𝑒 𝑓 𝑓 /𝑛𝑉𝑇
𝐼𝐷 = 𝐼𝐷 0 𝑒
𝐿
,
𝑉𝑒 𝑓 𝑓 ∝ ln 𝐼𝐷

Strong inversion:
1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶 𝑜𝑥 𝑉𝑒2𝑓 𝑓
2 𝐿
, p
𝑉𝑒 𝑓 𝑓 ∝ 𝐼𝐷

Operating region for a diode connected transistor only depends

on the current
 24.3 Find right transistor sizes 395

24.3.1 Use unit size transistors for analog design

𝑊/𝐿 ≈∈ [4, 6, 10]

, but should have space for two contacts

Use parallel transistors for larger W/L

Amplifiers
⇒ 𝐿 ≈ 1.2 × 𝐿𝑚𝑖𝑛

Current mirrors
⇒ 𝐿 ≈ 4 × 𝐿𝑚𝑖𝑛

Choose sizes that have been used by foundry for measurement to

match SPICE model

24.3.2 What about gm/Id ?

Weak
𝑔𝑚 1
=
𝐼𝑑 𝑛𝑉𝑇

Strong
𝑔𝑚 2
=
𝐼𝑑 𝑉𝑒 𝑓 𝑓
396 24 SPICE

24.3.3 Characterize the transistors

[Link]
CH_2C1F2.html

24.4 More information

Ngspice Manual
Installing tools

24.5 Analog Design

1. Define the problem, what are you trying to solve?

2. Find a circuit that can solve the problem (papers, books)
3. Find right transistor sizes. What transistors should be weak
inversion, strong inversion, or don’t care?
4. Check operating region of transistors (.op)
5. Check key parameters (.dc, .ac, .tran)
6. Check function. Exercise all inputs. Check all control sig-
nals
7. Check key parameters in all corners. Check mismatch (Monte-
Carlo simulation)
8. Do layout, and check it’s error free. Run design rule checks
(DRC). Check layout versus schematic (LVS)
9. Extract parasitics from layout. Resistance, capacitance, and
inductance if necessary.
10. On extracted parasitic netlist, check key parameters in all
corners and mismatch (if possible).
11. If everything works, then your done.

On failure, go back

24.6 Demo

[Link]
n
 CMOS Logic 25
25.1 CMOS Logic . . . 397
25.2 Analog transistor
to digital transistor 397
25.1 CMOS Logic 25.3 CMOS static logic
assumptions . . . . 399
25.4 Don’t break rules
unless you know
exactly why it will
be OK . . . . . . . . 401
25.2 Analog transistor to digital transistor
25.5 Logic cells . . . . . 401
25.5.1 CMOS static logic is
inverting . . . . . . 401
25.5.2 Rules for inverting
logic . . . . . . . . . 404
NMOS current (W = 0.4u L=0.15u) as a function of 25.6 SR-Latch . . . . . . 408
25.7 D-Latch (16 transis-
𝑉𝐺𝑆
tors) . . . . . . . . . 409
and 25.8 Other logic cells . 409
𝑉𝐷𝑆 25.9 AOI22: and or
invert . . . . . . . . 410
25.10 Tristate inverter . 411
25.11 Mux . . . . . . . . . 411
25.12 There are other
dicex/lectures/l13/[Link] types of logic . . . 413
25.13 Speed . . . . . . . . 414
25.14 Flip-flops and
speed . . . . . . . . 414
25.15 Timing analysis . 415
25.16 Timing analysis
tools . . . . . . . . . 416
25.17 Every gate must
be simulated to
provide behavior
over input tran-
sition and load
capacitance . . . . 419
25.18 All analog blocks
must have associ-
ated liberty file to
describe behavior
and timing paths
If you integrate
analog into digital
top flow . . . . . . 419
25.19 Gate Delay . . . . 419
25.20 Delay estimation . 419
25.21 Elmore Delay . . . 420
25.22 Delay components 420
25.23 Modern IC timing
analysis requires
computers with
advanced programs 422
25.24 Best number of
398 25 CMOS Logic
 25.3 CMOS static logic assumptions 399

Gate NMOS PMOS

VDD ON OFF
VDD -> VSS X X
VSS -> VDD X X
VSS OFF ON

Gate NMOS PMOS

1 ON OFF
1 -> 0 X X
0 -> 1 X X
0 OFF ON

25.3 CMOS static logic assumptions

NMOS source is connected to low potential

𝑉𝐺𝑆 > 𝑉𝑇𝐻

when
𝑉𝐺 = 𝑉𝐷𝐷

PMOS source is connected to high potential

𝑉𝐺𝑆 < 𝑉𝑇𝐻

when
𝑉𝐺 = 0
400 25 CMOS Logic

NOT
A A

B B
y y
A B A B
 25.4 Don’t break rules unless you know exactly why it will be OK 401

25.4 Don’t break rules unless you know exactly

why it will be OK

25.5 Logic cells

A B AB AB AB ATB
0 0 1 I o o AI ITE DM
0 1 I 0 O l ATB FB DM
1 0 T O O 1
1 O AB AT
1 O f y
ATB ART
I B ATB AB FEED
1 I I 0 0 AT AT
1
I 0 I 0 0 1 Atb AT
0 I 1 0 0 I
00 0 0 1 I

25.5.1 CMOS static logic is inverting

A Y
1 0
0 1
402 25 CMOS Logic

PU OFF ON
PD

OFF Z 1

ON 0 X

PD = Pull-down PU = Pull-up

logic => [0,1,Z,X];

[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]

Pull-up series

A B Y
0 0 1
0 1 Z
1 0 Z
1 1 Z

Pull-up paralell
 25.5 Logic cells 403

A B Y
0 0 1
0 1 1
1 0 1
1 1 Z

A ABY
00 1
Of X
IO X
B
1 It
Y

1
ABY
00 1
B 01 1
A
19
[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]

Pull-down series Y
A B AY ABY
0 0 Z 00 X
0 1 Z
1 0 Z
of X
1 1 0

B lot
111
Pull-down paralell

Y ABY
A B Y
0 0 Z
0 1 0
OO X
A
1 0 0
B
1 1 0
ol
101
I l
 A

404 25 CMOS Logic

19

Y
A ABY
00 X

of X
B lot
111

Y ABY
OO X
A B ol
101
I l

25.5.2 Rules for inverting logic

Pull-up OR
⇒
PMOS in series
⇒
POS AND
⇒
PMOS in paralell
⇒
PAP

Pull-down OR
⇒
NMOS in paralell
⇒
NOP AND
⇒
NMOS in series
⇒
NAS
 25.5 Logic cells 405

[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]

Y = AB = NOT ( A AND B)

AND PU
⇒
PMOS in paralell PD
⇒
NMOS in series
406 25 CMOS Logic

A B NOT(A AND B)
0 0 1
0 1 1
1 0 1
1 1 0

[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]

Y = A + B = NOT ( A OR B)

OR PU
⇒
 25.5 Logic cells 407

PMOS in series PD
⇒
NMOS in paralell

A B NOT(A OR B)
0 0 1
0 1 0
1 0 0
1 1 0
 408 25 CMOS Logic

25.6 SR-Latch

Use boolean expressions to figure out how gates work.

Remember De-Morgan

𝐴𝐵 = 𝐴 + 𝐵
𝐴+𝐵=𝐴·𝐵

𝑄 = 𝑅𝑄 = 𝑅 + 𝑄 = 𝑅 + 𝑄

𝑄 = 𝑆𝑄 = 𝑆 + 𝑄 = 𝑆 + 𝑄

QQ ND S Q
L 1
01 I R Q
0 I
XX O
S
E

R Q

𝑄 =𝑅+𝑄
,

𝑄 =𝑆+𝑄

S R Q ~Q
0 0 X X
0 1 0 1
1 0 1 0
1 1 Q ~Q
 Q

25.7 D-Latch (16 transistors) 409

R Q
25.7 D-Latch (16 transistors)

C D Q ~Q
0 X Q ~Q
1 0 0 1
1 1 1 0

25.8 Other logic cells

What about
Y = AB
and
Y=A+B
?

Y = AB = AB

Y = A AND B = NOT( NOT( A AND B ) )

Y = A+B = A+B
410 25 CMOS Logic

Y = A OR B = NOT( NOT( A OR B ) )

25.9 AOI22: and or invert

Y = NOT( A AND B OR C AND D)

Y = AB + CD

I 1

A B

C D
Y
A C

B b

TE
É A E
A Y YE y
E E
E

Po A
143
 A

TE 25.10 Tristate inverter 411

É A E
[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]
A Y YE y
E E
25.10 Tristate inverter E

A
E A Y
0 0 Z
0 1 Z
1 0 1
1 1 0

Y
E

[.table-separator: #000000, stroke-width(1)] [.table: margin(8)]

25.11 Mux

S Y
0 NOT(P1)
0 NOT(P1)
1 NOT(P0)
1 NOT(P0)
 MUK
412 25 CMOS Logic

PO Pl

s s

n Y
s s

f i
D-Latch (12 transistors)
Pl
gPO

s E
Q
D Q
L C
c

5 s
E

Po Pl
D-Flip Flop (< 26 transistors)
 25.12 There are other types of logic 413

Alo yo XXX Bos x o3

BENT X v3
AN

always_ff always_comb always_ff

25.12 There are other types of logic

▶ True single phase clock (TSPC) logic

▶ Pass transistor logic
▶ Transmission gate logic
▶ Differential logic
▶ Dynamic logic

Consider other types of logic “rule breaking”, so you should know

why you need it.

CK D8 CK D7 CK D6 CK D5 CK D4 CK D3 CK D2 CK D1 CK D0
DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N DP 1 P N

CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO CI CO
LOGIC[8] LOGIC[7] LOGIC[6] LOGIC[5] LOGIC[4] LOGIC[3] LOGIC[2] LOGIC[1] LOGIC[0] CK
CK EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO EI EO
DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 0 DP 1 DN 0 DN 1 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 DP 1 DN 0 X1

X2
CK
CK CM P
VP +
P

VN −
Bootstrapped 28 · CU N IT 27 · CU N IT 26 · CU N IT 25 · CU N IT 24 · CU N IT 23 · CU N IT 22 · CU N IT 21 · CU N IT 20 · CU N IT N
NMOS switches
(a)

VDD VDD VDD VDD

VREF VREF VDD VDD

CK MP 0 MP 3 CK MP 4 CK MP 5

MP 6 MP 7
DP 0 DN 0 DN 1 DP 1
N MP 2 EI MN 6 EI MN 9
A

EI MN 0 P MP 1 MN 5 MN 8
EO B

P MN 1 N MN 2 MN 3 P MN 4 N MN 7 CK MN 10
CI CO

(b) (c) (d)

Dynamic logic => A Compiled 9-bit 20-MS/s 3.5-fJ/[Link] SAR

ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers
414 25 CMOS Logic

25.13 Speed

[Link]

100

CPU Max clock [GHz]

10 1

10 2

10 3

1971 1975 1983 1992 1996 2000 2006 2010 2018

Date

Alo yo XXX Bos x o3

BENT X v3
AN

always_ff always_comb always_ff

25.14 Flip-flops and speed

dicex/lib/SUN_TR_GF130N.spi:

.SUBCKT DFRNQNX1_CV D CK RN Q QN AVDD AVSS

XA0 AVDD AVSS TAPCELLB_CV
XA1 CK RN CKN AVDD AVSS NDX1_CV

Alo yo XXX Bos x o3

 25.15 Timing analysis 415

XA2 CKN CKB AVDD AVSS IVX1_CV

XA3 D CKN CKB A0 AVDD AVSS IVTRIX1_CV
XA4 A1 CKB CKN A0 AVDD AVSS IVTRIX1_CV
XA5 A0 A1 AVDD AVSS IVX1_CV
XA6 A1 CKB CKN QN AVDD AVSS IVTRIX1_CV
XA7 Q CKN CKB RN QN AVDD AVSS NDTRIX1_CV
XA8 QN Q AVDD AVSS IVX1_CV
.ENDS

Setup time: How long before clk does the data need to change

v(d)
1

0
v(ck)
1

0
v(q)
1

0
v(qn)
1

0
0.0 0.5 1.0 1.5 2.0 2.5
Time(dff_setup_8.csv) 1e 9

Hold time: How long after clk can the data change

v(d)
1

0
v(ck)
1

0
v(q)
1

1
v(qn)
0
0.0 0.5 1.0 1.5 2.0 2.5
Time(dff_hold_-[Link]) 1e 9

25.15 Timing analysis

Analyze arrival times of all nodes in a combinatorial circuit

416 25 CMOS Logic

𝑎𝑟𝑟𝑖𝑣𝑎𝑙 𝑗 = 𝑚𝑎𝑥 𝑗∈ 𝑓 𝑎𝑛𝑖𝑛(𝑖) 𝑎𝑟𝑟𝑖𝑣𝑎𝑙 𝑗 +𝑡 𝑝𝑑𝑖 ⇒ 𝑎 𝑗 = 𝑚𝑎𝑥 𝑗∈ 𝑓 𝑎𝑛𝑖𝑛(𝑖) 𝑎 𝑗 +𝑡 𝑝𝑑𝑖

𝑠𝑙𝑎𝑐 𝑘 𝑖 = 𝑟𝑒 𝑞𝑢𝑖𝑟𝑒 𝑑 𝑖 − 𝑎𝑟𝑟𝑖𝑣𝑎𝑙 𝑗

Positive slack (over PVT‗ )

⇒
Timing is OK Negative slack (over PVT† )

Timing is not OK

as so
so 99 130
98 100 30

I
93 40 20
97 60
40

25.16 Timing analysis tools

Most paths will be fast enough
Commercial Cadence Tempus

There will
Synopsys PrimeTime be some criticalpaths
Free OpenTimer
that must be analysed and maybe
fixed

‗ Often called clock gating

† Often called clock gating
 25.16 Timing analysis tools 417

[Link] What is timing analysis

[Link] What do the tools need?

Input and output delay paths as a function of input transition time

and capacitive load, setup and hold time.

osu018_stdcells.lib

cell (INVX1) {
cell_footprint : inv;
area : 16;
cell_leakage_power : 0.0221741;
418 25 CMOS Logic

pin(A) {
direction : input;
capacitance : 0.00932456;
rise_capacitance : 0.00932196;
fall_capacitance : 0.00932456;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.503808;
function : "(!A)";
timing() {
related_pin : "A";
timing_sense : negative_unate;
cell_fall(delay_template_5x5) {
index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.030906, 0.037434, 0.038584, 0.039088, 0.030318", \
"0.04464, 0.057551, 0.073142, 0.077841, 0.081003", \
"0.064368, 0.091076, 0.11557, 0.126352, 0.144944", \
"0.139135, 0.174422, 0.232659, 0.261317, 0.321043", \
"0.249412, 0.28434, 0.357694, 0.406534, 0.51187");
}

fall_transition(delay_template_5x5) {
index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.032269, 0.0648, 0.087, 0.1032, 0.1476", \
"0.036025, 0.0726, 0.1044, 0.1236, 0.183", \
"0.06, 0.0882, 0.1314, 0.1554, 0.2286", \
"0.1494, 0.1578, 0.2124, 0.2508, 0.3528", \
"0.288, 0.2892, 0.3192, 0.3576, 0.492");
}
cell_rise(delay_template_5x5) {
index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.037639, 0.056898, 0.083401, 0.104927, 0.156652", \
"0.05258, 0.083003, 0.119028, 0.141927, 0.207952", \
"0.07402, 0.112622, 0.162437, 0.191122, 0.271755", \
"0.15767, 0.201007, 0.284096, 0.331746, 0.452958", \
"0.285016, 0.326868, 0.415086, 0.481337, 0.653064");
}
rise_transition(delay_template_5x5) {
index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.031447, 0.059488, 0.0846, 0.0918, 0.138", \
"0.047167, 0.0786, 0.1044, 0.1224, 0.1734", \
"0.072, 0.096, 0.1398, 0.1578, 0.222", \
"0.1866, 0.1914, 0.2358, 0.2748, 0.3696", \
"0.3648, 0.3648, 0.384, 0.4146, 0.5388");
}
}
internal_power() {
related_pin : "A";
fall_power(energy_template_5x5) {
index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.009213, 0.004772, 0.00823, 0.018532, 0.054083", \
"0.009047, 0.005677, 0.005713, 0.015244, 0.049453", \
"0.008669, 0.006332, 0.002998, 0.01159, 0.04368", \
"0.007879, 0.007243, 0.001451, 0.004701, 0.030385", \
"0.007605, 0.007297, 0.003652, 0.000737, 0.020842");
}
rise_power(energy_template_5x5) {
25.17 Every gate must be simulated to provide behavior over input transition and load capacitance 419

index_1 ("0.005, 0.0125, 0.025, 0.075, 0.15");

index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.023555, 0.029044, 0.041387, 0.051684, 0.087278", \
"0.023165, 0.028621, 0.039211, 0.048916, 0.083039", \
"0.023574, 0.02752, 0.036904, 0.045723, 0.077971", \
"0.024479, 0.025247, 0.032268, 0.039242, 0.066587", \
"0.024942, 0.025187, 0.029612, 0.034835, 0.057524");
}
}
}
}

25.17 Every gate must be simulated to provide

behavior over input transition and load
capacitance

25.18 All analog blocks must have associated

liberty file to describe behavior and
timing paths If you integrate analog into
digital top flow

25.19 Gate Delay

[Link] Delay definitions

Parameter Name Description

t_pdr max rising propagation input to rising output cross
delay 50 %
t_pdf max falling propagation input to falling output cross
delay 50 %
t_pd propagation delay t_pdf = (t_pdr + t_pdf)/2
t_r rise time 20 % to 80 %

Parameter Name Description

t_f fall time 80 % to 20 %
t_cdr min rising contamination input to rising output cross
delay 50 %
t_cdf min falling contamination input to falling output cross
delay 50 %
t_cd contamination delay t_cd = (t_cdr + t_cdf)/2

25.20 Delay estimation

How can we get a resonably accurate hand calculation model of

delay?

𝐶 ≈ 1 fF/𝜇m
420 25 CMOS Logic

𝑅 ≈ 1 kΩ𝜇m

[Link] Inverter with inverter load

𝐶 ≈ 1 fF/𝜇m
,
𝑅 ≈ 1 kΩ𝜇m

𝑡 𝑝𝑑 = 𝑅 × 6𝐶 = 6𝑅𝐶

𝑡 𝑝𝑑 = 6 × 1 × 103 × 1 × 10−15 s

𝑡 𝑝𝑑 = 6 × 10−12 = 6 ps

25.21 Elmore Delay

X
𝑡 𝑝𝑑 ≈ 𝑅 nodes−𝑡𝑜−𝑠𝑜𝑢𝑟𝑐𝑒 𝐶 𝑖
nodes

= 𝑅1 𝐶1 + (𝑅1 + 𝑅2 )𝐶2 + ... + (𝑅 1 + 𝑅 2 + ... + 𝑅 𝑁 )𝐶 𝑁

Good enough for hand calculation

25.22 Delay components

Parasitic delay (p)

p = 9 or 12 RC

Independent of load capacitance

Effort delay (f)

f = 5h RC

Proportional to load capacitance

Let’s use process independent unit

𝑑𝑟𝑒 𝑎𝑙
𝑑=
𝜏
,
𝜏 = 3𝑅𝐶
 25.22 Delay components 421

Parasitic delay
⇒ 𝑝 = 12𝑅𝐶/3𝑅𝐶 = 4

Effort delay
5
⇒ 𝑓 = 5 ℎ𝑅𝐶/3𝑅𝐶 = ℎ
3

Delay
5
⇒𝑑= 𝑓 +𝑝 = ℎ+4
3

Logical effort (g) is the ratio of the input capacitance of a gate to

the input capacitance of an inverter delivering the same output
current

Parasitic delay
⇒𝑝=4

Logic effort
5
⇒𝑔=
3

Electrical effort
⇒ℎ=1

Effort
⇒ 𝑓 = 𝑔ℎ

Delay
2
⇒ 𝑑 = 𝑓 + 𝑝 = 𝑔ℎ + 𝑝 = 5
3

Real delay
2
⇒ 𝑑 = 5 × 3 ps = 17 ps
3

Term Stage Expression Path Expression

number of stages 1 N
Q
logical effort g G= (gi )

Cin Cout(path)
electrical effort h= Cout H= Cin(path)

Conpath +Cof f path Q

branching effort b= Conpath B= bi

effort f = gh F = GBH
P
effort delay f DF = fi
P
parsitic delay p P = pi
P
delay d=f +p D= di = DF + P
422 25 CMOS Logic

25.23 Modern IC timing analysis requires

computers with advanced programs‡

25.24 Best number of stages

25.25 Which has shortest delay?

64

1 4 16
64

Term Stage Expression Path Expression

H
It 64
number of stages 1 N
Q
logical effort g G= (gi )

Cin Cout(path)
electrical effort h= Cout H= Cin(path)

TIC
Q

G IT si T
Conpath +Cof f path
branching effort b= Conpath B= bi

effort f = gh F = GBH
P
effort delay f DF = fi

parsitic delay B p1 P =
P
pi
P
delay d=f +p D=
64 di = DF + P

F GBH
𝐻 = 𝐶 𝑐𝑜𝑢𝑡 /𝐶 𝑖𝑛 = 64

Y delay
Path effort
𝐺= 𝑔 =
Y
1=1 𝑖

‡ Often De
called power gating
E Fi
64 D 64 1
a f
 25.26 Trends 423

𝐵=1

𝐹 = 𝐺𝐵𝐻 = 64

One stage
𝑓 = 64 ⇒ 𝐷 = 64 + 1 = 65

Three stage with

𝑓 =4

𝐷𝐹 = 12, 𝑝 = 3 ⇒ 𝐷 = 12 + 3 = 15

For close to optimal delay, use

𝑓 =4

(Used to be
𝑓 =𝑒
)

25.26 Trends

3500
500
3000
2500 400
Frequency [MHz]

Power [uW]

2000 300
1500
200
1000
100
500
0 0
0.4 0.6 0.8 1.0 1.2 1.4 0.4 0.6 0.8 1.0 1.2 1.4

0.6
4000
dPower/dFrequency [uW/MHz]

0.5
dFrequency/dVDD [f/V]

3500
0.4
3000
0.3
2500
0.2
2000 0.1

1500 0.0
0.4 0.6 0.8 1.0 1.2 1.4 0.4 0.6 0.8 1.0 1.2 1.4
VDD [V] VDD [V]
424 25 CMOS Logic

2.2 1e9
2.0
1.8

Frequency [Hz]
1.6
1.4
1.2
1.0
0.8
25 0 25 50 75 100 125 150
1e7
0.4

dFrequency/dTemp [f/K]
0.6

0.8

1.0

1.2
25 0 25 50 75 100 125 150
Temperature [C]

25.27 Attack vector

module counter(
output logic [WIDTH-1:0] out,
input logic clk,
input logic reset
);

parameter WIDTH = 8;

logic [WIDTH-1:0] count;

always_comb begin
count = out + 1;
end

always_ff @(posedge clk or posedge reset) begin

if (reset)
out <= 0;
else
out <= count;
end

endmodule // counter
 25.27 Attack vector 425

.SUBCKT counter out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0 clk reset AVDD AVSS
* SPICE netlist generated by Yosys 0_9 (git sha1 1979e0b1, gcc 10_3_0-1ubuntu1~20_10 -fPIC -Os)
X0 out_2 1 AVDD AVSS IVX1_CV
X1 out_3 2 AVDD AVSS IVX1_CV
X2 out_4 3 AVDD AVSS IVX1_CV
X3 out_5 4 AVDD AVSS IVX1_CV
X4 out_6 5 AVDD AVSS IVX1_CV
X5 out_0 6 AVDD AVSS IVX1_CV
X6 out_1 7 AVDD AVSS IVX1_CV
X7 6 7 8 AVDD AVSS NRX1_CV
X8 out_0 out_1 9 AVDD AVSS NDX1_CV
X9 1 9 10 AVDD AVSS NRX1_CV
X10 10 11 AVDD AVSS IVX1_CV
X11 2 11 12 AVDD AVSS NRX1_CV
X12 out_3 10 13 AVDD AVSS NDX1_CV
X13 out_3 10 14 AVDD AVSS NRX1_CV
X14 12 14 15 AVDD AVSS NRX1_CV
X15 3 13 16 AVDD AVSS NRX1_CV
X16 16 17 AVDD AVSS IVX1_CV
X17 out_4 12 18 AVDD AVSS NRX1_CV
X18 16 18 19 AVDD AVSS NRX1_CV
X19 4 17 20 AVDD AVSS NRX1_CV
X20 out_5 16 21 AVDD AVSS NDX1_CV
X21 out_5 16 22 AVDD AVSS NRX1_CV
X22 20 22 23 AVDD AVSS NRX1_CV
X23 5 21 24 AVDD AVSS NRX1_CV
X24 out_6 20 25 AVDD AVSS NRX1_CV
X25 24 25 26 AVDD AVSS NRX1_CV
X26 out_7 24 27 AVDD AVSS NRX1_CV
X27 out_7 24 28 AVDD AVSS NDX1_CV
X28 28 29 AVDD AVSS IVX1_CV
X29 27 29 30 AVDD AVSS NRX1_CV
X30 out_0 out_1 31 AVDD AVSS NRX1_CV
X31 8 31 32 AVDD AVSS NRX1_CV
X32 out_2 8 33 AVDD AVSS NRX1_CV
X33 10 33 34 AVDD AVSS NRX1_CV
X34 35 clk AVSS reset out_0 35 AVDD AVSS DFSRQNX1_CV
X35 32 clk AVSS reset out_1 36 AVDD AVSS DFSRQNX1_CV
X36 34 clk AVSS reset out_2 37 AVDD AVSS DFSRQNX1_CV
X37 15 clk AVSS reset out_3 38 AVDD AVSS DFSRQNX1_CV
426 25 CMOS Logic

X38 19 clk AVSS reset out_4 39 AVDD AVSS DFSRQNX1_CV

X39 23 clk AVSS reset out_5 40 AVDD AVSS DFSRQNX1_CV
X40 26 clk AVSS reset out_6 41 AVDD AVSS DFSRQNX1_CV
X41 30 clk AVSS reset out_7 42 AVDD AVSS DFSRQNX1_CV
V0 count_0 35 DC 0
V1 43 out_2 DC 0
V2 44 out_3 DC 0
V3 count_3 15 DC 0
V4 45 out_4 DC 0
V5 count_4 19 DC 0
V6 46 out_5 DC 0
V7 count_5 23 DC 0
V8 47 out_6 DC 0
V9 count_6 26 DC 0
V10 48 out_7 DC 0
V11 count_7 30 DC 0
V12 49 out_0 DC 0
V13 50 out_1 DC 0
V14 count_1 32 DC 0
V15 count_2 34 DC 0
.ENDS

tran1: * gate voltage sweep

V dor

300.0

250.0

200.0

150.0

100.0

50.0

−0.0
0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0

time ns

dicex/sim/verilog/counter_sv/counter_attack_tb.cir

VDDA AVDD_ATTACK 0 dc 0.5 pulse(1.5 0.6 tcd trf trf tapw taper)
 25.27 Attack vector 427

tran1: * gate voltage sweep

V avdd_attack xdut.count_0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

−0.2
0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0

time ns

tran1: * gate voltage sweep

V do dor

300.0

250.0

200.0

150.0

100.0

50.0

0.0

−50.0
0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0

time ns
428 25 CMOS Logic

25.28 Pick two

Power

Speed Area (cost)

25.29 Power

25.30 What is power?

Instantanious power:

𝑃(𝑡) = 𝐼(𝑡)𝑉(𝑡)

Energy :
∫ 𝑇
𝑃(𝑡)𝑑𝑡
0
[J]
 25.31 Power dissipated in a resistor 429

Average power:
∫ 𝑇
1
𝑃(𝑡)𝑑𝑡
𝑇 0
[W or J/s]

25.31 Power dissipated in a resistor

Ohm’s Law
𝑉𝑅 = 𝐼𝑅 𝑅

𝑉𝑅2
𝑃𝑅 = 𝑉𝑅 𝐼𝑅 = 𝐼𝑅2 𝑅 =
𝑅

25.32 Charging a capacitor to VDD

Capacitor differential equation

𝑑𝑉
𝐼𝐶 = 𝐶
𝑑𝑡

∞ ∞ 𝑉𝐶  𝑉𝐷𝐷
𝑑𝑉 𝑉2
∫ ∫ ∫ 
𝐸𝐶 = 𝐼𝐶 𝑉𝐶 𝑑𝑡 = 𝐶 𝑉𝐶 𝑑𝑡 = 𝐶𝑉 𝑑𝑉 = 𝐶
0 0 𝑑𝑡 0 2 0

1
𝐸𝐶 = 𝐶𝑉𝐷𝐷
2
2

25.33 Energy to charge a capacitor to a voltage

VDD

1
𝐸𝐶 = 𝐶𝑉𝐷𝐷
2
2

𝑑𝑉
𝐼𝑉 𝐷𝐷 = 𝐼𝐶 = 𝐶
𝑑𝑡

∞ ∞ 𝑉𝐷𝐷
𝑑𝑉
∫ ∫ ∫
𝐸𝑉 𝐷𝐷 = 𝐼𝑉 𝐷𝐷 𝑉𝐷𝐷 𝑑𝑡 = 𝐶 𝑉𝐷𝐷 𝑑𝑡 = 𝐶𝑉𝐷𝐷 𝑑𝑉 = 𝐶𝑉𝐷𝐷
2
0 0 𝑑𝑡 0

Only half the energy is stored on the capacitor, the rest is dissipated
in the PMOS
430 25 CMOS Logic

25.34 Discharging a capacitor to 0

1
𝐸𝐶 = 𝐶𝑉𝐷𝐷
2
2

Voltage is pulled to ground, and the power is dissipated in the

NMOS

25.35 Power consumption of digital circuits

𝐸𝑉 𝐷𝐷 = 𝐶𝑉𝐷𝐷
2

In a clock distribution network (chain of inverters), every output is

charged once per clock cycle

𝑃𝑉 𝐷𝐷 = 𝐶𝑉𝐷𝐷
2
𝑓

25.36 Sources of power dissipation in CMOS

logic

𝑃𝑡𝑜𝑡 𝑎𝑙 = 𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 + 𝑃𝑠𝑡 𝑎𝑡𝑖𝑐

Dynamic power dissipation

Charging and discharging load capacitances

short-circut current, when PMOS and NMOS conduct at the same

time

𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝑃𝑠𝑤𝑖𝑡𝑐 ℎ𝑖𝑛 𝑔 + 𝑃𝑠 ℎ𝑜𝑟𝑡𝑐𝑖𝑟𝑐𝑢𝑖𝑡

Static power dissipation

Subthreshold leakage in OFF transistors

Gate leakage (tunneling current) through gate dielectric

Source/drain reverse bias PN junction leakage

𝑃𝑠𝑡 𝑎𝑡𝑖𝑐 = 𝐼 𝑠𝑢𝑏 + 𝐼 𝑔𝑎𝑡𝑒 + 𝐼 𝑝𝑛 𝑉𝐷𝐷

 25.37 Switching Power in logic gates 431

25.37 Switching Power in logic gates

Only output node transitions from low to high consume power

from
𝑉𝐷𝐷

Define
𝑃𝑖
to be the probability that a node is 1

Define
𝑃𝑖 = 1 − 𝑃𝑖
to be the probability that a node is 0

Define activity factor (

𝛼𝑖
) as the probability of switching a node from 0 to 1

If the probabilty is uncorrelated from cycle to cycle

𝛼 𝑖 = 𝑃𝑖 𝑃𝑖

25.38 Switching probability

Random data
𝑃 = 0.5
,
𝛼 = 0.25

Clocks
𝛼=1

Gate PY

AND2 PA PB

OR2 1 − P¯A P¯B

NAND2 1 − PA PB

NOR2 P¯A P¯B

XOR2 PA P¯B + P¯A PB

432 25 CMOS Logic

Gate PY

AND2 PA PB

OR2 1 − P¯A P¯B

NAND2 1 − PA PB

NOR2 P¯A P¯B

XOR2 PA P¯B + P¯A PB

I
Y
C z
b

Atte F AI E ABCD
Assume
1
𝑃 = 𝑃𝐴 = 𝑃𝐵 = 𝑃𝐶 = 𝑃𝐷 =
2

DI 5 E
𝑃𝑋 = 𝑃𝑍 = 1 − 𝑃𝑃 = 1 −
1 3
=
4 4

DE 5 E 𝑃𝑋 = 𝑃𝑌 =
1
4

Pr PC PD 0,5
1 1 1
𝑃𝑌 = × =

PA
4 4 16

 
1 1 15 1 15
𝛼= 1− = =
16 16 16 16 256
 25.39 Strategies to reduce dynamic power 433

Gate PY

AND2 PA PB

OR2 1 − P¯A P¯B

NAND2 1 − PA PB

NOR2 P¯A P¯B

XOR2 PA P¯B + P¯A PB

I
Y
C z
b

Atte
Use De Morgan first
FAB + CD

AI E ABCD
𝐴+𝐵=𝐴·𝐵

DI 5 E
AB + CD = ABCD = 𝐴𝐵𝐶𝐷

5 E
 4

DE
1 1
⇒𝑃 𝑌 = 𝑃𝐴 𝑃𝐵 𝑃𝐶 𝑃𝐷 = =
2 16

P
𝑃𝑡𝑜𝑡 = 𝛼𝐶𝑉𝐷𝐷
2
𝑓

Pr PC PD 0,5
PA 25.39 Strategies to reduce dynamic power

1. Stop clock
2. Stop activity
3. Reduce clock frequency

Py
434 25 CMOS Logic

4. Turn off VDD

5. Reduce VDD

Alo yo XXX Bos x o3

BENT X v3
AN

always_ff always_comb always_ff

25.39.1 Stop clock §

Enable Clk out

Logic D Q

Clk in
Lo
Enable Clk out
Logic D Q

Clk in
Lo
25.39.2 Stop activity

Alo yo
Alo
XXX
yo

I
XXX Bos
Bos
x o3
x o3

BED XD
AID
I

Clk out

BED XD
AID § Often called clock gating

Clk out
 as

25.39 Strategies to reduce dynamic power 435

Clk out

25.39.3 Reduce frequency

Gig
Ef

ClkA ClkB ClkB ClkA

ClkB<ClkA

25.39.4 Turn off power supply ¶

for

Inputs Gated
egg
outputs
Logic

[Link] Reduce power supply

VDDH

VDDL
[Link]
Fast logic Slow logic Level
I 1 1 1 1 shifter 1

any rook

Uno ont
it
faut
d
¶ Often e velocity sot
called power gating

4 2 Quadratic
so onto 2
436 25 CMOS Logic

[Link] Energy-Delay Product

𝐶 2𝑉𝐷𝐷
3
𝐸𝐷𝑃 = 𝑘
(𝑉𝐷𝐷 − 𝑉𝑡 )1 to 2

Differentiating with respect to

𝑉𝐷𝐷

and setting the result to

0
it’s possible to work out that

3
𝑉𝐷𝐷−𝑜𝑝𝑡 = 𝑉𝑡 ∈ [1.5, 3]𝑉𝑡
3 − 1 to 2

25.40 Wires

25.41 Wire geometry

Pitch = w + s

Aspect ratio (AR) = t/w

These days
𝐴𝑅 ≈ 2

25.42 Metal stack

Often 5 - 10 layers of metal

Metal Material Thickness Purpose

Metal 1 Copper Thin in gate routing
Metal 3 - 5 Copper Thicker Between gates
routing
RDL Aluminium Ultra tick Can tolerate high
forces during wire
bonding.
 25.43 Metal routing rules on IC 437

25.43 Metal routing rules on IC

Odd numbers metals

⇒
Horizontal routing (as far as possible)

Even numbers metals

⇒
Vertical routing (as far as possible)

25.44 Modeling Interconnect

Resistance narrow size impedes flow

Capacitance through under the leaky pipes

Inductance paddle wheel intertia opposes changes in flow rate

25.45 Lumped model

Use 1-segment
𝜋
-model for Elmore delay
438 25 CMOS Logic

C/2 R C/2
---/\/\/\---
| |
--- ---
--- ---
| |
--- ---
- -

25.46 Wire resistance

resistivity ⇒ 𝜌 [Ωm]

𝜌 𝑙 𝑙
𝑅= = 𝑅□
𝑡𝑤 𝑤

𝑅□ = sheet resistance [Ω/□]

To find resistance, count the number of squares

𝑅 = 𝑅□ × # of squares

25.47 Most wires: Copper

1.7𝜇Ω𝑐𝑚
𝑅 𝑠 ℎ𝑒 𝑒𝑡−𝑚 1 ≈ ≈ 0.1Ω/□
200𝑛𝑚

1.7𝜇Ω𝑐𝑚
𝑅 𝑠 ℎ𝑒 𝑒𝑡−𝑚 9 ≈ ≈ 0.006Ω/□
3𝜇𝑚

Pitfalls

Cu atoms diffuse into silicon and can cause damage

Must be surrounded by a diffusion barrier

Difficult high current densities (mA/

m) and high temperature (125 C)

 25.48 Contacts 439

25.48 Contacts

Contacts and vias can have 2-20

Must use many contacts/vias for high current wires

25.49 Wire Capacitance

Dense wires has about

0.2 fF/𝜇m

25.50 FSM

25.51 Mealy machine

An FSM where outputs depend on current state and inputs

Mealy machine
Careful with
An FSM where outputs depend on current
tate and inputs
output comb
for analogsystem
glitches
1

arsten Wulff 2021 4

440 25 CMOS Logic

25.52 Moore machine

An FSM where outputs depend on current state

Moore machine
Careful with
An FSM where outputs depend on current output comb
state for analogsystem
in glitches
y
fates
out
so I t

CLK
Carsten Wulff 2021 5

25.53 Mealy versus Moore

Parameter Mealy Moore

Outputs depend on input and output depend on current
current state state
States Same, or fewer states than
Moore
Inputs React faster to inputs Next clock cycle
Outputs Can be asynchronous Synchronous
States Generally requires fewer More states than Mealy
states for synthesis
Counter A counter is not a mealy A counter is a Moore
machine machine
Design Can be tricky to design Easy

25.53.1 dicex/sim/counter_sv/counter.v

module counter(
output logic [WIDTH-1:0] out,
input logic clk,
input logic reset
);
parameter WIDTH = 8;
logic [WIDTH-1:0] count;

always_comb begin
count = out + 1;
end

always_ff @(posedge clk or posedge reset) begin

if (reset)
out <= 0;
else
out <= count;
end

endmodule // counter
 25.54 Battery charger FSM 441

25.54 Battery charger FSM

25.54.1 Li-Ion batteries

Most Li-Ion batteries can tolerate 1 C during fast charge

For Biltema 18650 cells:

1 C = 2950 mA

0.1 C = 295 mA

Most Li-Ion need to be charged to a termination voltage of 4.2 V

442 25 CMOS Logic

Too high termination voltage, or too high charging current can

cause growth of lithium dendrites, that short + and -. Will end
in flames. Always check manufacturer datasheet for charging
curves and voltages

25.54.2 Battery charger - Inputs

Voltage above
𝑉𝑇𝑅𝐼𝐶𝐾𝐿𝐸

Voltage close to
𝑉𝑇𝐸𝑅𝑀

If voltage close to
𝑉𝑇𝐸𝑅𝑀
and current is close to
𝐼𝑇𝐸𝑅𝑀
, then charging complete

If charging complete, and voltage has dropped (

𝑉𝑅𝐸𝐶𝐻𝐴𝑅𝐺𝐸

), then start again

25.54.3 Battery charger - States

Trickle charge (0.1 C)

Fast charge (1 C)

Constant voltage

Charging complete
 25.54 Battery charger FSM 443

iterm = 0
vterm = 0

vtrkl = 0
vterm = 1 Const. Voltage
Fast charge vrchrg = 0
vtrkl = 1 iterm = 1

Trickle charge
vrchrg = 1 Complete

[Link] One way to draw FSMs - Graphviz

digraph finite_state_machine {
rankdir=LR;
size="8,5"

node [shape = doublecircle, label="Trickle charger", fontsize=12] trkl;

node [shape = circle, label="Fast charge", fontsize=12] fast;
node [shape = circle, label="Const. Voltage", fontsize=12] vconst;
node [shape = circle, label="Done", fontsize=12] done;

trkl -> trkl [label="vtrkl = 0"];

trkl -> fast [label="vtrkl = 1"];
fast -> fast [label="vterm = 0"];
fast -> vconst [label="vterm = 1"];
vconst-> vconst [label="iterm = 0"];
vconst-> done [label="iterm = 1"];
done-> done [label="vrchrg = 0"];
done-> trkl [label="vrchrg = 1"];

dot -Tpdf [Link] -o [Link]

444 25 CMOS Logic

iterm = 0
vterm = 0

vtrkl = 0
vterm = 1 Const. Voltage
Fast charge vrchrg = 0
vtrkl = 1 iterm = 1

Trickle charge
vrchrg = 1 Complete

module bcharger( output logic trkl,

output logic fast,
output logic vconst,
output logic done,
input logic vtrkl,
input logic vterm,
input logic iterm,
input logic vrchrg,
input logic clk,
input logic reset
);

parameter TRLK = 0, FAST = 1, VCONST = 2, DONE=3;

logic [1:0] state;
logic [1:0] next_state;

//- Figure out the next state

always_comb begin
case (state)
TRLK: next_state = vtrkl ? FAST : TRLK;
FAST: next_state = vterm ? VCONST : FAST;
VCONST: next_state = iterm ? DONE : VCONST;
DONE: next_state = vrchrg ? TRLK :DONE;
default: next_state = TRLK;
endcase // case (state)
end

//- Control output signals

always_ff @(posedge clk or posedge reset) begin
if(reset) begin
state <= TRLK;
trkl <= 1;
fast <= 0;
vconst <= 0;
done <= 0;
end
else begin
state <= next_state;
case (state)
TRLK: begin
trkl <= 1;
fast <= 0;
vconst <= 0;
done <= 0;
end
FAST: begin
trkl <= 0;
fast <= 1;
vconst <= 0;
done <= 0;

end
VCONST: begin
trkl <= 0;
fast <= 0;
vconst <= 1;
done <= 0;

end
 25.54 Battery charger FSM 445

DONE: begin
trkl <= 0;
fast <= 0;
vconst <= 0;
done <= 1;
end
endcase // case (state)
end // else: !if(reset)
end
endmodule

[Link] Synthesize FSM with yosys

dicex/sim/verilog/bcharger_sv/[Link]

# read design
read_verilog -sv [Link];
hierarchy -top bcharger;

# the high-level stuff

fsm; opt; memory; opt;

# mapping to internal cell library

techmap; opt;
synth;
opt_clean;

# mapping flip-flops
dfflibmap -liberty ../../../lib/SUN_TR_GF130N.lib

# mapping logic
abc -liberty ../../../lib/SUN_TR_GF130N.lib

# write synth netlist

write_verilog bcharger_netlist.v
read_verilog ../../../lib/SUN_TR_GF130N_empty.v
write_spice -big_endian -neg AVSS -pos AVDD -top bcharger bcharger_netlist.sp

# write dot so we can make image

show -format dot -prefix bcharger_synth -colors 1 -width -stretch
clean

vtrkl
BUF
A $441 $442
$437 Y A Y
iterm BUF A Y B NDX1_CV IVX1_CV
IVX1_CV
A $444
A $447 Y
vterm BUF Y B NRX1_CV
B NRX1_CV
A $452
BUF A $451 Y
A Y B NDX1_CV
vrchrg $450 NRX1_CV
Y B
B NRX1_CV
A $445
Y
B NDX1_CV
$435 A 0:0 - 0:0
A Y $453
IVX1_CV A $443 Y
Y B NDX1_CV
B NRX1_CV
$436 $446 A $455
A Y A Y A Y
IVX1_CV IVX1_CV $454 NDX1_CV
Y B
B NRX1_CV 0:0 - 1:1
next_state 1:1 - 0:0
A $440 $449
1:1 - 0:0 Y A Y
B NRX1_CV IVX1_CV

0:0 - 0:0
A $438 A
Y $448
0:0 - 0:0 B NDX1_CV Y
B NDX1_CV BUF CK
state Q
0:0 - 0:0 D $322
R DFSRQNX1_CV
CK QN $429
Q S
D $321
R DFSRQNX1_CV CK 1'0
QN Q
S $428 D $326 0:0 - 1:1
1'0
1'0 R DFSRQNX1_CV
QN $433
S
trkl
BUF
clk
$439
A Y
IVX1_CV CK
Q vconst
D $324
R DFSRQNX1_CV
0:0 - 0:0 QN $431
S
1'0

BUF
reset
CK
Q fast
D $325
R DFSRQNX1_CV
QN $432
S
1'0

0:0 - 0:0
CK
Q done
D $323
R DFSRQNX1_CV
QN $430
S
1'0

bcharger
 Mixed Signal Simulation in
NGSPICE 26
26.1 Mixed Signal Simu-
26.1 Mixed Signal Simulation in ngspice lation in ngspice . . 447
26.2 Digital simulation . 447
26.2 Digital simulation 26.3 Transient analog
simulation . . . . . . 448
26.4 Demo . . . . . . . . . 449
▶ The order of execution of events at the same time-step do
26.5 The circuit . . . . . . 450
not matter
26.6 The digital code . . 450
▶ The system is causal. Changes in the future do not affect
26.7 Compile RTL . . . . 451
signals in the past or the now
26.8 Import object into
There are both commercial an open source tools for digital simula- SPICE file . . . . . . 451
tion. If you’ve never used a digital simulator, then I’d recommend 26.9 Import in testbench 452
you start with iverilog. I’ve made some examples at dicex. 26.10 Override default
digital output voltage452
Commercial 26.11 Running . . . . . . . 452

▶ Cadence Excelium
▶ Siemens Questa
▶ Synopsys VCS

Open Source

▶ iverilog/vpp
▶ Verilator
▶ SystemDotNet

Below is an example of a counter in SystemVerilog. The code can

be found at counter_sv.

In the always_comb section we code what will become the combi-

natorial logic. In the always_ff section we code what will become
our registers.
module dig(
input wire clk,
input wire reset,
output logic [4:0] b
);

logic rst = 0;

always_ff @(posedge clk) begin

if(reset)
rst <= 1;
else
rst <= 0;
end

always_ff @(posedge clk) begin

if(rst)
b <= 0;
else
b <= b + 1;
448 26 Mixed Signal Simulation in NGSPICE

end // dig

endmodule

26.3 Transient analog simulation

Analog simulation is different. There is no quantized time step.

How fast “things” happen in the circuit is entirely determined by
the time constants, change in voltage, and change in current in the
system.
It is possible to have a fixed time-step in analog simulation, for
example, we say that nothing is faster than 1 fs, so we pick that
as our time step. If we wanted to simulate 1 s, however, that’s at
least 1e15 events, and with 1 event per microsecond on a computer
it’s still a simulation time of 31 years. Not a viable solution for all
analog circuits.
Analog circuits are also non-linear, properties of resistors, capac-
itors, inductors, diodes may depend on the voltage or current
across, or in, the device. Solving for all the non-linear differential
equations is tricky.
An analog simulation engine must parse spice netlist, and setup
partial/ordinary differential equations for node matrix
The nodal matrix could look like the matrix below, 𝑖 are the currents,
𝑣 the voltages, and 𝐺 the conductances between nodes.

𝐺 𝐺 ··· 𝐺
1𝑁 𝑣 𝑖
© 11 12
ª© 1ª © 1ª
­ 𝐺21 𝐺22 · · · 𝐺2𝑁 ® ­ 𝑣2 ® ­ 𝑖2 ®
­ . .. .. .. ®® ­­ .. ®® = ­­ .. ®®
­ .. . . . ®­ . ® ­ . ®
­
« 𝐺 𝑁 1 𝐺 𝑁 2 · · · 𝐺 𝑁 𝑁 ¬ «𝑣 𝑁 ¬ « 𝑖 𝑁 ¬
The simulator, and devices model the non-linear current/voltage
behavior between all nodes
as such, the 𝐺 ’s may be non-linear functions, and include the 𝑣 ’s
and 𝑖 ’s.
Transient analysis use numerical methods to compute time evolu-
tion
The time step is adjusted automatically, often by proprietary algo-
rithms, to trade accuracy and simulation speed.
The numerical methods can be forward/backward Euler, or the
others listed below.

▶ Euler
▶ Runge-Kutta
▶ Crank-Nicolson
▶ Gear
 26.4 Demo 449

If you wish to learn more, I would recommend starting with the

original paper on analog transient analysis.

SPICE (Simulation Program with Integrated Circuit Emphasis)

published in 1973 by Nagel and Pederson

The original paper has spawned a multitude of commercial, free

and open source simulators, some are listed below.

If you have money, then buy Cadence Spectre. If you have no

money, then start with ngspice.

Commercial - Cadence Spectre - Siemens Eldo - Synopsys

HSPICE

Free - Aimspice - Analog Devices LTspice - xyce

Open Source - ngspice

Digital Analog
Simulator Simulator

Event Timester Control

26.4 Demo

Tutorial at [Link]

Repository at [Link]

Assumes knowledge of Tutorial

450 26 Mixed Signal Simulation in NGSPICE

26.5 The circuit

In design/JNW_SV_SKY130A/JNWSW_CM.sch you’ll find a current

mirror, and a 5-bit current DAC.

What we want from the digital is to control the binary value of the
current DAC.

26.6 The digital code

The digital code is shown below. The clk controls the stepping,
while the reset sets the output b=0. When reset is off, then the b
increments.

module dig(
input wire clk,
input wire reset,
output logic [4:0] b
);

logic rst = 0;

always_ff @(posedge clk) begin

if(reset)
rst <= 1;
else
rst <= 0;
end

always_ff @(posedge clk) begin

if(rst)
b <= 0;
else
b <= b + 1;
end // dig
endmodule
 26.7 Compile RTL 451

26.7 Compile RTL

The first thing we need to do is to translate the verilog into a

compiled object that can be used in ngspice.

cd sim/JNWSW_CM
ngspice vlnggen ../../rtl/dig.v

26.8 Import object into SPICE file

I’m lazy. So I don’t want to do the same thing multiple times. As

such, I’ve written a small script to help me instanciate the verilog

perl ../../tech/script/gensvinst ../../rtl/dig.v dig

The script generates an [Link] file. The first section imports

the digital compiled library

adut [clk
+ reset
+ ]
+ [b.4
+ b.3
+ b.2
+ b.1
+ b.0
+ ] null dut
.model dut d_cosim
+ simulation="../[Link]" delay=10p

Turns out that ngspice needs the digital inputs and outputs to
be connected to something to calculate them (I think), so connect
some resistors

* Inputs
Rsvi0 clk 0 1G
Rsvi1 reset 0 1G

* Outputs
Rsvi2 b.4 0 1G
Rsvi3 b.3 0 1G
Rsvi4 b.2 0 1G
Rsvi5 b.1 0 1G
Rsvi6 b.0 0 1G

For the busses I find it easier to read the value as a real, so translate
the buses from digital b[4:0] to a real value dec_b

E_STATE_b dec_b 0 value={( 0

+ + 16*v(b.4)/AVDD
+ + 8*v(b.3)/AVDD
+ + 4*v(b.2)/AVDD
+ + 2*v(b.1)/AVDD
+ + 1*v(b.0)/AVDD
+)/1000}
.save v(dec_b)
452 26 Mixed Signal Simulation in NGSPICE

26.9 Import in testbench

An example testbench can be seen below (sim/JNWSW_-

CM/[Link])

...

.include ../[Link]
.include ../[Link]

* Translate names
VB0 b.0 b<0> dc 0
VB1 b.1 b<1> dc 0
VB2 b.2 b<2> dc 0
VB3 b.3 b<3> dc 0
VB4 b.4 b<4> dc 0

...

26.10 Override default digital output voltage

We can override the output dac from digital to analog to ensure

that the digital signals have the right levels

*- Override the default digital output bridge.

pre_set auto_bridge_d_out =
+ ( ".model auto_dac dac_bridge(out_low =te 0.0 out_high = 1.8)"
+ "auto_bridge%d [ %s ] [ %s ] auto_dac" )

26.11 Running

You can run the whole thing with

cd sim/JNWSW_CM/
make typical
 Analog Neural Networks and
Translinear Circuits 27
27.0.1 Kirchoff’s voltage law455
27.0.2 Kirchoff’s current law456
27.0.3 Charge concervation 457
27.1 Multiplication . . . 458
Attention Is All You Need 27.1.1 Digital capacitance . 458
27.1.2 Mixing . . . . . . . . 458
27.1.3 Translinear principle 459
27.2 Want to learn more? 461

Figure 1: The Transformer - model architecture.

The Transformer follows this overall architecture using stacked self-attention and point-wise, fully
connected layers for both the encoder and decoder, shown in the left and right halves of Figure 1,
espectively.
Neural Nets 3blue1brown
3.1 Encoder and Decoder Stacks

Encoder: The encoder is composed of a stack of N = 6 identical layers. Each layer has two
ub-layers. The first is a multi-head self-attention mechanism, and the second is a simple, position-
wise fully connected feed-forward network. We employ a residual connection [11] around each of
he two sub-layers, followed by layer normalization [1]. That is, the output of each sub-layer is
LayerNorm(x + Sublayer(x)), where Sublayer(x) is the function implemented by the sub-layer
𝑎 𝑙+1 =in𝜎(𝑊
tself. To facilitate these residual connections, all sub-layers 𝑙 𝑎 𝑙 +as𝑏 well
the model, 𝑙 ) as the embedding
ayers, produce outputs of dimension dmodel = 512.

Decoder: The decoder is also composed of a stack of N = 6 identical layers. In addition to the two
ub-layers in each encoder layer, the decoder inserts a third sub-layer, which performs multi-head
attention over the output of the encoder stack. Similar to the encoder, we employ residual connections
around each of the sub-layers, followed by layer normalization. We also modify the self-attention
ub-layer in the decoder
A NNstackconsists
to prevent of
positions from attending
addition, to subsequent
multiplication, and positions. This
a non-linear func-
masking, combined with fact that the output embeddings are offset by one position, ensures that the
tion
predictions for position i can depend only on the known outputs at positions less than i.

3.2 Attention

An attention function can be described as mapping a query and a set of key-value pairs to an output,
where the query, keys, values, and output are all vectors. The output is computed as a weighted sum

3
454 27 Analog Neural Networks and Translinear Circuits

𝑤 𝑤12 ... 𝑤 1𝑛  𝑥1   𝑏1 
©  11
­  𝑤21 𝑤22 ... 𝑤 2𝑛  𝑥2   𝑏2  ®
   ª
y = 𝜎 ­­  . .. .. ..  .  +  . ®
­  .. . . . 
 ..   ..  ®
   ®
«  𝑚1 𝑤𝑚2
𝑤 . . . 𝑤 𝑚𝑛  𝑥 𝑛  𝑏 𝑚  ¬

!
𝑅−1 X
X 𝑆−1 X
𝐶−1
OA(𝑥,𝑦,𝑘) = 𝑓 IA(𝑥+𝑖,𝑦+𝑗,𝑐) × 𝑊(𝑖,𝑗,𝑐,𝑘)
𝑖=0 𝑗=0 𝑐=0

Assume N neurons

▶ N multiplications per neuron

▶ N + 1 additions per neuron
▶ 1 sigmoid per neuron

For efficient inference, additions and multiplications should be

low power!
 455

Wil
91

win
win

yu
wan

27.0.1 Kirchoff’s voltage law

The directed sum of the potential differences around

any closed loop is zero

𝑉1 + 𝑉2 + 𝑉3 + 𝑉4 = 0
456 27 Analog Neural Networks and Translinear Circuits
Addition
Vo V V2 V3

V1 V2 V3
a
a a
a

Is current law
27.0.2 Kirchoff’s

Is IY I ILE
The algebraic sum of currents in a network of conduc-
tors meeting at a point is zero
I

MAC

Io
M

vs
m
get

𝑖1 + 𝑖2 + 𝑖3 + 𝑖4 = 0
 457

Is
Is IY I ILE

27.0.3 Charge concervation

MAC
See Charge concervation on Wikipedia

Ci 2 03
Qy V4
V3
Q VIC qucY 03036
Io
a a M a a
vs
m
get

𝑄4 = 𝑄1 + 𝑄2 + 𝑄3

𝐶1𝑉1 + 𝐶2𝑉2 + 𝐶3𝑉3

𝑉4 =
𝐶1 + 𝐶2 + 𝐶3
458 27 Analog Neural Networks and Translinear Circuits

27.1 Multiplication

27.1.1 Digital capacitance

𝐶1𝑉1 + 𝐶2𝑉2 + 𝐶3𝑉3

𝑉4 =
𝐶1 + 𝐶2 + 𝐶3

𝐶1 𝐶𝑁
Is 𝑉𝑂 =
𝐶𝑇𝑂𝑇
𝑉1 + · · · +
𝐶𝑇𝑂𝑇
𝑉𝑁

Is IY I ILE
Make capacitors digitally controlled, then

𝐶1
𝑤1 =
𝐶𝑇𝑂𝑇

I Might have a slight problem with variable gain as a function of

total capacitance

27.1.2 Mixing

MAC 𝐼 𝑀 1 = 𝐺 𝑚 𝑉𝐺𝑆

𝐼 𝑜 = 𝐼 𝑀 1 𝑡 𝑖𝑛𝑝𝑢𝑡

Io
M

vs
m
get
 27.1 Multiplication 459

27.1.3 Translinear principle

[Link] MOSFET in sub-threshold

10 3
i(vcur)
10 4

10 5

10 6

10 7

10 8

10 9

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

vgate

𝑊 (𝑉𝐺𝑆 −𝑉𝑡 ℎ )/𝑛𝑈𝑇 𝑘𝑇

𝐼 = 𝐼𝐷 0 𝑒 ,𝑈𝑇 =
𝐿 𝑞

𝑊 −𝑉𝑡 ℎ /𝑛𝑈𝑇
𝐼 = ℓ 𝑒 𝑉𝐺𝑆 /𝑛𝑈𝑇 , ℓ = 𝐼𝐷 0 𝑒
𝐿

𝐼
 
𝑉𝐺𝑆 = 𝑛𝑈𝑇 ln
ℓ

Il Iz Is It

𝑉1 + 𝑉2 = 𝑉3 + 𝑉4

𝐼1 𝐼2 𝐼3 𝐼4
         
𝑛𝑈𝑇 ln + ln = 𝑛𝑈𝑇 ln + ln
ℓ1 ℓ2 ℓ3 ℓ4
460 27 Analog Neural Networks and Translinear Circuits

𝐼1 𝐼2 𝐼3 𝐼4
   
ln = ln
ℓ 1ℓ 2 ℓ 3ℓ 4

𝐼1 𝐼2 𝐼3 𝐼4
=
ℓ 1ℓ 2 ℓ 3ℓ 4

𝐼1 𝐼2 = 𝐼3 𝐼4 , if ℓ 1ℓ 2 = ℓ 3ℓ 4

𝐼1 𝐼2 = 𝐼3 𝐼4

𝐼1 = 𝐼 𝑎 , 𝐼2 = 𝐼 𝑏 + 𝑖 𝑏 , 𝐼3 = 𝐼 𝑏 , 𝐼4 = 𝐼 𝑎 + 𝑖 𝑎

𝐼 𝑎 (𝐼𝑏 + 𝑖 𝑏 ) = 𝐼𝑏 (𝐼 𝑎 + 𝑖 𝑎 )

𝐼 𝑎 𝐼𝑏 + 𝐼 𝑎 𝑖 𝑏 = 𝐼𝑏 𝐼 𝑎 + 𝐼𝑏 𝑖 𝑎

𝐼𝑏
𝑖𝑏 = 𝑖𝑎
𝐼𝑎

ℓ 1ℓ 2 = ℓ 3ℓ 4

𝑊 −𝑉𝑡 ℎ /𝑛𝑈𝑇
ℓ1 = 𝐼𝐷 0 𝑒
𝐿

𝑊 −(𝑉𝑡 ℎ ±𝜎𝑡 ℎ )/𝑛𝑈𝑇

ℓ2 = 𝐼𝐷 0 𝑒 = ℓ 1 𝑒 ±𝜎𝑡 ℎ /𝑛𝑈𝑇
𝐿

𝑎 𝑣𝑡
𝜎𝑡 ℎ = √
𝑊𝐿

ℓ2 𝑎
± √ 𝑣𝑡 /𝑛𝑈
= 𝑒 𝑊𝐿 𝑇
ℓ1

[Link] Demo

JNW_SV_SKY130A
 27.2 Want to learn more? 461

27.2 Want to learn more?

An Always-On 3.8 u J/86 % CIFAR-10 Mixed-Signal Binary CNN

Processor With All Memory on Chip in 28-nm CMOS
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM
for Accurate and Precision-Programmable CNN Inference
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN
Processor Featuring Analog Neuronal Computation Unit and
Analog Memory
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-
in-Memory CNN Accelerator Featuring a 4.2-POPS/W
146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-
Normalization
 Bibliography

D. Johns and K. Martin, Analog Integrated Circuit Design. John

Wiley & Sons, Inc., 1997.
A. V. D. Ziel, Noise in Solid State Devices and Circuits. John Wiley
& Sons Inc, 1986.
B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-
Hill, 2001.
R. M. Gray and L. D. Davisson, An Introduction to Statistical
Signal Processing. Cambridge University Press, 2004, no. ISBN-
0521838606.
A. Einstein, “Method for the determinination of the statistical
values of observations concerning quantities subject to irregular
fluctuations,” vol. October, 1987.