Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

Scaling and Technology Issues for Soft Error Rates

Allan. H. Johnston
Jet Propulsion Laboratory
California Institute of Technology
Pasadena, California

Abstract - The effects of device technology and scaling on Figure 2 shows how various contributions to the
soft error rates are discussed, using information obtained from terrestrial error rate are affected by critical charge [3]. The
both the device and space communities as a guide to determine work was done with SRAM cells, fabricated with a 0.35 µm
the net effect on soft errors. Recent data on upset from high-
energy protons indicates that the soft-error problem in DRAMs
CMOS process. For critical charge < 35 fC it is possible to
and microprocessors is less severe for highly scaled devices, in upset the cell with alpha particles. The largest contribution
contrast to expectations. Possible improvements in soft-error from alphas comes from solder, but there is also a significant
rate for future devices, manufactured with silicon-on-insulator contribution from impurities in the metallization. By
technology, are also discussed. increasing the critical charge it is possible to eliminate errors
from alpha particles, but terrestrial neutrons are still able to
I. INTRODUCTION induce errors. The gradual decrease in neutron-induced error
Soft-errors from alpha particles were first reported by rate with increasing critical charge is due to the distribution
May and Woods [1], and considerable effort was spent by the of neutron energies, which extends over a very wide range.
semiconductor device community during the ensuing years to Figure 2. Various contributions to error rate for a small-area
deal with the problem of errors from alpha particles in 10-8
packaging, metallization and other materials. This included 1.2 um x 1.2 um SRAM junction
modifications in device design to reduce the inherent 10-9 Volume = 6 um3
sensitivity to extraneous charge, as well as application of
Error Rate (errors/hour/bit)

topical shielding and improvements in material purity. 10-10

Neutron (sea level flux)

Atmospheric neutrons can also produce soft errors. One Alpha (AI wire, 0.001 α-cm2/hr)
example is shown in Figure 1, after Lage, et al.[2], which Alpha (PbSn solder, 0.01 α-cm2/hr)
10-11
shows the increase in measured soft error rate when
experiments were done on SRAMs using alpha sources with
10-12
different intensities. The increased error rate is due to the
presence of atmospheric neutrons that have a larger relative
influence when alpha experiments are done for long time 10-13

periods using low-intensity sources.

10-14
100,000 0 50 100 150 200
Critical Charge (fC)
24fC SRAM cell, fabricated with a 0.35 µm CMOS process, vs. critical
Increased error rate charge (after Tosaka, et al. [3]).
10,000 with low-intensity
System Soft Error Rate (FITS)

sources In parallel with the work by commercial manufacturers,

the space community began to be concerned about soft errors
48fC in the more rigorous environment of space at about the same
1,000 32fC time period [4,5]. The most severe soft-error effect in space
is due to high-energy galactic cosmic rays, which have
specific ionization values that are many orders of magnitude
100
Extrapolated value from
above that of alpha particles. Those effects, just as for alpha
tests with high-intensity particles, are due to direct ionization along the path of the
alpha source incident particle.
10 The space community also recognized that indirect
reactions from high-energy protons could cause soft errors
After Lage, et al., 1993 IEDM [6-8]. The first experimental observations of proton upset
1 were made in 1979. Subsequently, high-energy protons have
0.01 0.1 1 10 100 1000 been shown to cause many different effects in space
Accelerated Soft-Error Rate (Hits/hr) environments, including latchup in some devices [9], which
Figure 1. Increase in soft-error rate of an SRAM when low- is of particular concern because it is potentially catastrophic.
intensity alpha particle sources are used.
The space community routinely tests advanced devices
------- with high energy protons, and that data, which is widely
The research in this paper was carried out by the Jet Propulsion available, provides an interesting set of data for comparisons
Laboratory, California Institute of Technology, under contract with
the National Aeronautics and Space Adminstration (NASA) under with scaling predictions and modeling that can be directly
the NASA Electronics Parts and Packaging Program (ERC). applied to neutron upset in the terrestrial environment. The

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 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

space community also routinely tests devices with heavy high-energy neutrons. This allows test results for high-
ions. For example, Figure 3 shows how the cross sections of energy protons to be extended directly to neutron
internal registers and cache memory of a microprocessor environments, which has been noted by workers in both the
increase when tests are done with long-range ions that have semiconductor and space environments [10,11]. The
different values of LET. (For reference, the LET of a 5-MeV proposed standard for evaluating SER rates in terrestrial
alpha particle is 1 MeV-cm2/mg). The heavy-ion data applications allows protons to be used as an alternative to
provides a direct indication of the specific ionization track tests with neutron sources [12].
density required for upset, and is a useful way to compare the Although cross sections for protons and neutrons are
upset sensitivity of different devices. nearly the same at high energies, that is not the case for lower
energies (<50 MeV). At low energies, protons cross
10 -1 sections increase because of Coulomb interactions with the
Dynamic Test (Cache Enabled) lattice atoms, causing the cross section to increase with
10 -2
decreasing energy.
10 -3 In addition, the neutron energy distribution of the
uncharged neutrons in terrestrial environments extends to
Cross Section (cm 2/bit)

10 -4 much lower energies than the distribution of protons within

Registers spacecraft because even moderate amounts of shielding
10 -5 eliminate most of the low-energy protons in space. Figure 4
compares the distribution of atmospheric neutrons (actually
10 -6
the energy distribution of the white neutron source at Los
10 -7 Alamos National Laboratory) with the typical distribution of
proton energies in spacecraft.
10 -8 Differential Flux (particles/cm2-sec-MeV)
10-2 109
10 -9

10-10 10-3 108

0 10 20 30 40 protons
LET (MeV-cm2/mg)
10-4 107
neutrons
Figure 3. Dependence of cross section on linear energy transfer for
a microprocessor. The upset threshold is slightly above the LET for 10-5 106
a 5-MeV alpha particle.

II. SPACE AND TERRESTRIAL ENVIRONMENTS 10-6 105

A. Comparison of Environments
10-7 104
The high-energy cosmic rays that spacecraft encounter 1 10 100 1000
are largely shielded by the earth’s atmosphere. Consequently Neutron or Proton Energy, MeV
they do not occur in significant numbers in terrestrial
applications. However, the interaction of cosmic rays in the Figure 4. Energy distributions of atmospheric neutrons on the
upper atmosphere produces secondary particles, including ground and protons in an earth-orbiting spacecraft.
neutrons. The neutrons have a low interaction probability
with the atmosphere, and significant numbers of energetic The point of this figure is to show that the proton
neutrons arrive at the earth’s surface. spectrum in space decreases at low energies, reducing the
importance (and interest) of low energy protons in causing
Although spacecraft are usually not concerned with errors in spacecraft. On the other hand, the relative number
neutrons, most space environments include high-energy of neutrons in terrestrial environments continues to increase
protons with a wide distribution of energies. Direct at low energies. Thus, the soft-error rate problem on the
ionization from protons is generally too low to be of concern ground is much more affected by reductions in the threshold
in microelectronics. However, protons can produce nuclear energy for errors from neutron-induced reactions compared
reactions in silicon, and the secondary reaction products from to the soft-error problem in space (from protons).
reactions or nuclear collisions -- which have relatively short
range -- produce ionization tracks with much higher charge B. Recoil Energy Distribution
densities compared to those generated along the path of the A great deal of experimental work has been done to
high-energy protons that initiate the reaction. However, the investigate the distribution of recoil energies when
cross section for such indirect processes is much smaller than experiments are done with monoenergetic protons [13,14].
for direct ionization because the incoming particle has to That work has shown that there is a continuous distribution
undergo a nuclear collision in order to produce the reaction of recoil energies that decreases up to a maximum energy.
(nuclear cross sections are typically 10-4 to 10-5 lower). For silicon, the maximum recoil energy due to elastic
Protons with energies above 50 MeV have cross sections collisions is 13.6% of the energy of the incident particle.
for nuclear reactions that are nearly identical to those for This means that for 100 MeV protons (or neutrons), the

2
 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000
1.2

maximum total energy of a recoil is 13.6 MeV. However, 1.0 80 ns

there are very few particles with maximum recoil energy.

Normalized Charge
The energy distribution decreases roughly as 1/E up to the 0.8 40 ns
maximum recoil energy.
The range of the recoil products varies with energy. For 0.6 20 ns 3.5 µm track length
the case where the incident particle energy is 100 MeV the p-substrate: 1 x 1015 cm-3
more energetic recoils have ranges up to 5 µm, but most of
0.4 10 ns
the particles have ranges below 2 µm.
Depletion width
For the real environments in terrestrial or space
environments the net distribution of recoils is a superposition 0.2
1 ns
of the distribution of energetic primary particles along with
the energy distribution of the recoil products. Most of the 0
0 2 4 6 8 10 12 14 16 18 20
recoils will have relatively short ranges, but “short” is a Distance from Top Surface (µm)
relative term. For older technologies, one could make the
assumption that the entire recoil energy was absorbed within
the sensitive volume of a sensitive device because device
III. DEVICE SCALING TRENDS
dimensions were considerably larger than the range of most
recoils. That is no longer true for highly scaled devices, A. Scaling for Microprocessors and Logic
which affects the collected charge. Device scaling is an extremely complex topic that
C. Effective Volume for Recoil Products involves many assumptions about technology evolution. The
Many of the recoil products have ranges that are earliest studies were done by Dennard, et al. at IBM [20].
considerably longer than the average charge collection depth. More recent studies by Davari, et al. [21] and Hu [22] have
Thus, particles that undergo collisions outside the charge discussed scaling trends for two basic technology directions:
collection region may have sufficient energy to reach the high performance, where power dissipation is a secondary
sensitive region and deposit part of the energy in that region. concern; and low power, where power and performance are
One way to deal with this is to define a generation rate for both considered. Table 1, after Davari, presents the results
recoils (referred to as the burst generation rate) and then based on the state-of-the-art in 1995. Those predictions have
assume an extended region outside the charge collection been reasonably accurate in predicting future technology
region for the total sensitive volume [15-18]. trends. For radiation susceptibility, the key parameters are
gate oxide thickness, relative speed and density, and power
This approach has been reasonably effective for older
supply voltage which affect charge collection and critical
generation devices, but needs to be modified to handle
charge.
modern devices with smaller sensitive volumes [ref]. It is
also important to realize that the charge collection region is Table 1. Scaling Predictions for High-Performance and Low-
not really constant, but changes dimensions depending on the Power Logic Circuits (after Davari, et al. [21])
total deposited energy and location because the depletion
region collapses if the energy is sufficiently high.
Late
Charge collection volumes for DRAMs are quite complex Parameter
1980's
1992 1995 1998 2001 2004

because diffused charge in the substrate, well beyond the Supply voltage (V)
depletion region, can be collected by a reverse-biased High performance
Low power
5
-
5/3.3
3.3/2.5
3.3/2.5
2.5/1.5
2.5/1.8
1.5/1.2
1.5
1.0
1.2
1.0
junction. Figure 5 shows the results of calculations of the
charge collected by particles that produce charge tracks well Lithog. resolution (µm) 1.25 0.8 0.5 0.35 0.25 0.18

away from the depletion region [19] (similar to the situation Channel length (µm) 0.9 0.6/0.45 0.35/0.25 0.2/0.15 0.1 0.07
in the bulk substrate of a DRAM). These calculations were Gate oxide thickness (nm) 23 15/12 9/7 6/5 3.5 2.5
done with the PISCES device analysis program. Note that
2.5 6.3 12.8 25 48
nearly all of the deposited charge is collected, but the time Relative density 1.0

over which the charge collection occurs extends to relatively Relative speed
High performance 1.0 1.4/2.0 2.7/3.4 4.2/5.1 7.2 9.6
long time intervals. For DRAMs this is an important effect Low power - 1.0/1.6 2.0/2.4 3.2/3.5 4.5 7.2
because the charge will be effective in fully or partially
discharging the storage capacitor. Although the same charge B. Scaling for Memories
collection process will take place in SRAMs or logic devices, Memory technologies involve quite different scaling
they are generally only sensitive to charge collected in short assumptions. There are two reasons for this: first, memory
time periods, unlike DRAMs. Thus, charge collection technologies require very low leakage and hence must
depends not only on substrate properties, but also on the way impose a much higher ratio between “on” and “off”
in which the circuit responds to longer duration charge transistors within the memory; and second, memories are
pulses. generally sold at very low prices compared to
microprocessors and other high-performance devices,
resulting in much more conservative approaches for device
Figure 5. Charge collection from short range recoils at various design.
distances from the depletion region of a p-n junction.

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 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

There have been many changes in memory technology. reduces the voltage swing, directly affecting critical charge.
For DRAMs, storage capacitor technology is one factor that That factor, along with the decease in device dimensions and
has continually evolved. Although it is not possible to cover increase in switching speed, will compete with the decrease
all aspects of DRAM scaling in this paper, Figure 6, after in charge collection depth.
Itoh, et al. [23] shows how cell area and storage capacitor For DRAMs the effect of internal voltage is less apparent
size have changed over several DRAM generations. Device because of the effect of charge leakage, which reduces the
dimensions have scaled inversely with memory size, as internal cell voltage between successive refresh cycles.
expected from general scaling trends. On the other hand, DRAM architecture is also a factor. Most DRAMs use
storage capacitance has decreased far more slowly. One boosted word lines, and the internal noise margin is affected
reason for this is the need to keep the total stored charge by the ratio of the bit line capacitance and the cell storage
above the charge generated by alpha particles, as well as capacitance. Changes in DRAM architecture have resulted
other noise sources. The charge generated by a 5-MeV alpha in block-oriented designs that have allowed the capacitance
particle in one micrometer of path length is indicated on this ratio to increase for scaled devices [24]. Architecture and
figure for comparison. This trend in storage capacitance device design play a large role in determining DRAM
affects soft-error rates for proton or neutron reactions sensitivity, and make it difficult to establish general scaling
because it establishes a “floor” for charge generation. trends.
10,000 1000
Critical Charge

Signal Charge Qs (fC)

Signal Charge Qs
Planar
Trench
The effects of device scaling on soft-error rate depend on
1000 100 several competing factors. The critical charge required to
upset a memory element (or active transistor) is expected to
Stack
decrease with scaling. but this is partially offset by the
Cell Area (µm2)

100 10 decrease in charge collection depth as well as by device

Cell Area
LET of 5 MeV architecture. Although earlier studies predicted a steady
Alpha Particle decrease in critical charge with scaling [25], the complex
is 10 fC/µm
10
interaction of device design with other scaling issues was not
taken into account. Even though critical charge is expected
to decrease with scaling, the net effect on threshold
1
conditions is less obvious, and may actually improve with
scaling as discussed in the next section. Designs that take
16K 256K 4M 64M 1G upset from alpha particles into account will reduce the
Memory Capacity (bit)
critical charge compared to earlier projections.
Cross Sectional Area
Figure 6. Cell area and stored charge for DRAMs over several Finally, even if the first two factors cancel the decrease in
generations (after Itoh, et al. [23]). device area that results from scaling will lower the total cross
section per bit. Thus, the net upset rate per bit is expected to
decrease with scaling even if the minimum ionization track
C. Scaling Implications for SER Sensitivity charge density is unchanged.
Charge Collection Depth Other factors must also be considered. For example,
The depth over which charge from a long-range ion is devices with complex internal architectures (e.g., special
collected generally decreases with scaling. This is due to internal test modes in DRAMs) may allow new types of
several factors, including the decrease in active layer errors to be introduced that are difficult to identify and may
thickness and increase in channel doping, which reduces the interfere with standard ways to detect and correct errors. The
depletion width as well as charge funneling. total functional capability of VLSI devices continues to
Substrate properties also affect charge collection depth, increase with scaling, and thus the probability of an error
particularly for epitaxial CMOS. Present state-of-the-art within a chip may increase substantially even if the error rate
CMOS devices use epitaxial layers that are approximately 2 per bit decreases. This has certainly been an issue in the
µm thick, effectively limiting charge collection to that region. space environment.
That is not true for bulk substrates (which are typically used IV. TEST RESULTS FROM THE SPACE COMMUNITY
for memories), and thus the charge collection depth for
memories can be up to an order of magnitude higher. As A. Microprocessors
discussed later, circuits designed with SOI technology will Extensive work has been done on microprocessor testing
further reduce charge collection depth, potentially reducing during the last 15 years. That work has shown that the
SER sensitivity by up to an order of magnitude. dominant effect of heavy ions and protons on
Switching Amplitude microprocessors is upset in internal registers. Upset in
Power supply voltage (and total switching amplitude) random logic has not been a significant factor up to now,
directly affect critical charge and upset sensitivity. For logic although this may change as microprocessors continue to
circuits and SRAMs, the decrease in switching voltage evolve.

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 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

One result which was certainly unexpected is that the 10-12

threshold LET required to upset registers in NMOS and

CMOS microprocessors has essentially not changed during PC603e
the last fifteen years [26]. As shown in Table 2, the feature

Cross Section (cm2/bit)

size used in manufacturing these devices has changed by 10-13
more than one order of magnitude during that time period.
The last entry in this table is for a very high speed modern
microprocessor, the Power PC750. This may be influenced Power PC 750
by overall concerns about alpha particle sensitivity by 10-14
microprocessor manufacturers.

Table 2. Threshold LET for Microprocessors

10-15
0 100 200 300 400
Feature Threshold LET Proton Energy (MeV)
Device Manuf. Year Size (approx.) (MeV-cm2/mg)
Figure 7. Comparison of proton upset for registers in high-
Z-80 Zilog 1986 3 µm 1.5 - 2.5
performance microprocessors from one manufacturer that represent
1996 and 1999 design technologies.
8086 Intel 1986 1.5 µm 1.5 - 2.5
80386 Intel 1991 0.8 µm 2-3 These results are indicative of mainstream
68020 Mot. 1992 0.8 µm 1.5 - 2.5 microprocessors that are fabricated on epitaxial substrates.
LS64811 LSI 1993 1.2 µm 2 - 2.5 The newer Power PC750 operates at very high clock
90C601 MHS 1993 1.2 µm 2 - 2.5 frequencies (700 MHz). Test results on both types of
80386 Intel 1996 0.6 µm 2-3 processors indicate that their responses to both protons and
PC603e Mot. 1997 0.4 µm 1.7 - 3 heavy ions are dominated by errors in registers and the cache
Pentium Intel 1997 0.35 µm 2-3 memory. It is possible that faster devices may be susceptible
Power PC750 Mot. 2000 0.25 µm 2 - 2.5 to transient errors in logic or other regions of the processor,
creating a scenario where the upset rate may increase with
further scaling. That topic is currently under investigation at
It is also useful to examine trends in proton upset for JPL using next-generation microprocessors as a vehicle for
microprocessors. Figure 7 shows the dependence of proton study. Once that threshold is reached, it may become quite
upset cross section on proton energy for register errors, difficult to use devices in space. The error rate in the
normalized per bit, for two relatively advanced processors. terrestrial environment will also increase, but will be of less
The threshold energy is essentially the same, but the cross importance because the particle flux is so much lower for the
section of the newer Power PC750 processor is more than an terrestrial environments.
order of magnitude lower than that of the older PC603e.
Both processors use thin epitaxial layers over highly doped
substrates. The PC603e was designed with a feature size of B. DRAMs
0.35 µm, while the feature size of the Power PC750 was 0.25 Trends in DRAM responses are also of great interest.
µm. However, two points must be kept in mind: first, DRAM
The fact that the threshold energy is approximately the scaling involves very different assumptions about device
same is consistent with the results in Table 2 showing nearly parameters; and second, DRAMs are almost always
the same threshold LET for the two processors. However, fabricated on bulk substrates and are sensitive to charge
there is an important consideration for proton recoils beyond collection over far longer distances. The latter factor is
that of threshold LET for long-range particles. As devices highly significant when comparing upset from heavy ions
become smaller, the range of the recoil atoms from indirect (with long range) and the short-range recoil products from
processes increases relative to device feature size. This proton or neutron reactions.
allows reaction products with lower energy to upset the Figure 8 shows how the sensitivity of proton upset rates
device, potentially increasing the upset rate in the terrestrial have changed as DRAMs have evolved. The upset rate has
neutron environment. steadily declined, on average over several DRAM
generations. This figure does not consider any of the details
involving the structure of individual devices, and it is
apparent that there are large differences in the upset rate of
devices from different manufacturers. This is probably
related to the design of the wells; most DRAMs use a triple-
well structure in order to reduce leakage current in the
memory array.

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 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

6.5
10-12

NEC 6.0
Vn = 3V

Collected Charge, Q (fC)

Cross Section (cm2/bit)

Toshiba Vn = 2.2V
10-13
5.5
Average
Vn = 1.5V
Samsung 5.0
Lines correspond to model
10-14 200 MeV protons Points are for 3-D simulation
4.5 Trench isolation (0.3 micron)

After H. Shin, Trans. Elect. Dev., 1851 (1999)

4.0
10-15 0.05 0.10 0.15 0.20 0.25
0 1 10 100
µm2)
Junction Area (µ
DRAM Size (Mbits)
Figure 8. DRAM upset rate from high energy protons for various Figure 9. Model and calculations of charge collection from alpha
generations. particles in advanced, small area devices.

Heavy-ion results have shown that the threshold LET for

DRAMs has remained between 1 and 2 MeV-cm2/mg for an These results are roughly indicative of charge collection
extended period. In this case, the threshold is almost for particles with higher LET. However, with higher LET
certainly related to concerns about alpha-particle sensitivity, the internal voltage collapse is more complete. This not only
which involves relatively long-range particles with LET extends the charge collection region further outside the
values that are slightly below 1 MeV-cm2/mg.. Although depletion region, but also extends the time period for
earlier generation devices often used internal die coatings to recovery.
reduce sensitivity to upset from those sources, newer Although it is not possible to use these results directly
generation DRAMs have taken alpha particle sensitivity into for devices with epitaxial substrates, the general features of
account as part of the design process [24]. these simulations show the limitations of elementary
calculations of the effect of device geometry on charge
V. PREDICTIONS FOR MORE ADVANCED TECHNOLOGIES
collection. The process is very involved because of the very
A. High-Speed/Low-Voltage Designs high carrier densities that cause the field to collapse at short
time periods after the ion strike. Dodd has investigated
As discussed earlier, one of the major concerns about
charge collection for basic p-n structures with various
high-speed devices is sensitivity to upset from internal
conditions, including epitaxial substrates [28]. However,
transients in logic circuits. Clocked logic circuitry generally
more work needs to be done on charge collection to
reduces sensitivity to such transients because the timing
investigate these dependencies for the more compact
window is limited to periods when the clock is undergoing a
structures that occur in circuits. This requires three-
logic transition. However, as devices are pushed to higher
dimensional simulations which are time consuming and
and higher speeds the relative size of the sensitive timing
difficult to interpret because of the many variables involved.
window increases. Reduced switching voltages increase
overall sensitivity to this type of error, particularly when B. Silicon-on-Insulator Technology
power dissipation is reduced. Silicon-on-insulator technology has been studied for
Recent simulations and models by Shin, et al. have shown many years. For the first time mainstream high-performance
how charge collected from alpha particles in very small devices are being produced [29], although their availability is
devices is affected by junction area and switching voltage extremely limited at the present time. No radiation test
[27]. Figure 9 shows the results of those calculations, which results are available at this time, but is expected in the near
are done for a triple-well structure in an advanced DRAM. future.
The collected charge does not change nearly as rapidly with Results for SOI processors from much older technologies
junction area as one would expect. This is mainly due to the indicated that the threshold LET was approximately five time
collapse of internal electric fields during the first 200-500 ps higher for equivalent SOI structures [30]. This agrees
of the ion strike. The collapse of the field extends the charge closely with elementary calculations using the charge
collection region beyond the boundaries established by the collection depth in combination of the assumption of a
depletion region. somewhat lower critical charge. If the newer processors
As shown in the figure, the collected charge falls slightly behave similarly, the net effect will be to reduce upset rates
with decreasing switching voltage. The net effect is to make in either space or terrestrial environments by about one order
the dependence of critical charge on cell voltage sublinear, of magnitude. Although this is a significant decrease, it does
rather than the linear relationship that would be expected not eliminate concern about upset rates in either the
from elementary considerations. terrestrial or space environments.
Another important effect is bipolar action due to the short
channel length [31], which remains an important problem for
partially depleted devices that are currently used for SOI

6
 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

devices [32]. The bipolar parasitic transistor between source as DRAMs have evolved. This trend is consistent with the
and drain can be turned on by heavy ions or recoil products elementary concept of a near constant threshold for
from protons or neutrons, providing far more current than sensitivity to long-range ions, along with the reduced area of
that due to the ionization. Recent work on SOI structures advanced devices. However, charge collection in these
has investigated bipolar action triggered by terrestrial structures is a complex process, and more modeling studies
neutrons [33], relying on modified contacts to reduce need to be done in order to improve the level of
vulnerability. understanding of charge collection in structures that closely
Commercial manufacturers are continuing to evaluate the resemble real semiconductor devices.
response of SOI devices to neutrons. Figure 10 shows recent
results from a group at Fujitsu Semiconductor [34]. These
measurements were done on large-area SOI structures which
allow considerably more total charge to be collected
compared to the compact, small area regions in an actual SOI
transistor. The work shows how the distribution of charges
collected in experiments at the Los Alamos white neutron
source depends on SOI film thickness.

Figure 10. Charge collection in large-area SOI test structures at the

Los Alamos neutron source for various film thickesses [ref].

VI. CONCLUSIONS
This paper has discussed various factors that affect soft
error rates in advanced devices using a slightly different
approach that takes advantage of the body of test data and
analysis in the space community on the radiation response of
memories and microprocessors. Such results are largely
empirical because the space community lacks the thorough
understanding of internal device design that is present in the
semiconductor device community. However, the data taken
in space environments provides a direct comparison of
different device types and manufacturers, and is readily
available in the literature.
Results with high-energy protons are generally applicable
to the atmospheric neutron environment, provided the
threshold energy remains above approximately 30 MeV.
Recent data for high-performance processors shows that the
threshold energy is still above that range, and that errors in
current-technology processors are still dominated by registers
and cache memories.
Data for high-density memories show that the overall
cross section for upsets from protons has steadily decreased

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 Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000

[20] R. H. Dennard, F. H. Gaensslen, H-N. Yu, V. L. Rideout, E.

Bassous and A. R. LeBlanc, “Design of Ion-Implanted
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8
Presented at the 4th Annual Research Conference on Reliability, Stanford University, October 2000