ELEC 335

Digital Logic Design

Instructor:

Dr. Abdul-Halim Jallad

3–1 ELEC 335, Digital Logic Design, UAE University

 Chapter 3

Combinational Logic Circuits

3–2 ELEC 335, Digital Logic Design, UAE University

 Outline
• Combinational Logic
• Combinational Logic Analysis
• Literal Analysis
• Symbol Analysis
• Standard Expression Forms
• Karnaugh Map Minimization
• Karnaugh Map Minimization with Don’t Cares

ELEC 335, Digital Logic Design, UAE University

3–3
 CLOs Covered
1. Manipulate number system, binary codes, and computer
arithmetic. [PLO-1]
2. Apply Boolean algebra and Karnaugh map minimization
techniques to simplify Boolean expressions. [PLO-1]
3. Design binary adders, decoders, encoders, multiplexers, and de-
multiplexers to implement combinational logic circuits. [PLO-1,
2]
4. Design with flip-flops, synchronous and asynchronous sequential
circuits, state diagrams, and state tables. [PLO-1, 2]
5. Design registers (serial, parallel, and shift) ripple counters, and
synchronous counters. [PLO-1, 2]
6. Design digital circuits with memory devices of ROMs, PLAs, &
PALs. [PLO-2, 4]
ELEC 335, Digital Logic Design, UAE University
 Combinational Logic
• One or more digital signal inputs
• One or more digital signal outputs
• Outputs are only functions of current input
values (ideal) plus logic propagation delays

I1 O1
Combinational
Im Logic
On

3–5 ELEC 335, Digital Logic Design, UAE University

 Combinational Logic (cont.)
• Combinational logic has no memory!
– Outputs are only function of current input
combination
– Nothing is known about past events
– Repeating a sequence of inputs always gives the
same output sequence
• Sequential logic (covered later) does have
memory
– Repeating a sequence of inputs can result in an
entirely different output sequence
ELEC 335, Digital Logic Design, UAE University
3–6
 Combinational Logic Example
• Circuit controls the level of fluid in a tank
– inputs are:
• HI - 1 if fluid level is too high, 0 otherwise
• LO - 1 if fluid level is too low, 0 otherwise
– outputs are:
• Pump - 1 to pump fluid into tank, 0 for pump off
• Drain - 1 to open tank drain, 0 for drain closed
– input to output relationship is described by a
truth table

ELEC 335, Digital Logic Design, UAE University

3–7
 Combinational Logic Example (cont.)

HI LO Pump Drain Truth table representation

0 0 0 0 Tank level is OK
0 1 1 0 Low level, pump more in
1 0 0 1 High level, drain some out
1 1 x x inputs cannot occur

Logic HI Pump
Circuit

Drain
LO

3–8 ELEC 335, Digital Logic Design, UAE University

 Combinational Logic Example (cont.)
A B Z
A AB
0 0 0 A
B
0 1 1
1 0 0 A AB
AB + AB
B
1 1 1
A B X
0 0 0 A
A x = AB
0 1 1 B
1 0 0
1 1 0
3–9 ELEC 335, Digital Logic Design, UAE University
 Combinational Circuit Analysis
• Combinational circuit analysis starts with a
schematic and answers the following
questions:
– What is the truth table(s) for the circuit output
function(s)
– What is the logic expression(s) for the circuit
output function(s)

3–10 ELEC 335, Digital Logic Design, UAE University

 Literal Analysis
• Literal analysis is process of manually
assigning a set of values to the inputs, tracing
the results, and recording the output values
– For ‘n’ inputs there are 2n possible input
combinations
– From input values, gate outputs are evaluated to
form next set of gate inputs
– Evaluation continues until gate outputs are
circuit outputs
• Literal analysis only gives us the truth table

3–11 ELEC 335, Digital Logic Design, UAE University

 Literal Analysis - Example
A 1 A B C Z
1
C 0 1 0 0 0 x
1 Z 0
0
0
1
1
0
x
x
0 1 1 x
1 0 0 x
0
B 1
1 0 1 x
1 1 0 1
1 1 1 x

Assign input values

Determine gate outputs and propagate
Repeat until we reach output

3–12 ELEC 335, Digital Logic Design, UAE University

 Symbolic Analysis
• Like literal analysis we start with the circuit
diagram
– Instead of assigning values, we determine gate
output expressions instead
– Intermediate expressions are combined in
following gates to form complex expressions
– We repeat until we have the output function and
expression
• Symbolic analysis gives both the truth table
and logic expression

3–13 ELEC 335, Digital Logic Design, UAE University

 Symbolic Analysis (cont.)
• Note that we are constructing the truth table
as we go
– truth table has a column for each intermediate
gate output
– intermediate outputs are combined in the truth
table to generate the complex columns
• Symbolic analysis is more work but gives us
complete information

3–14 ELEC 335, Digital Logic Design, UAE University

 Symbolic Analysis - Example
Generate intermediate
A expression
A·C
C Create associated TT
C Z
column
A·C + B·C Repeat till output
B B·C
reached

A B C C A· C B·C Z = A· C + B·C
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 0 1 0 0 0 0
1 1 0 1 1 0 1
1 1 1 0 0 1 1

3–15 ELEC 335, Digital Logic Design, UAE University

 A complete design procedure
1. Set up the truth table
2. Write the AND term for each case where the
output is 1
3. Write the SOP expression for the output
4. Simplify the output expression
5. Implement the circuit for the final expression

3–16 ELEC 335, Digital Logic Design, UAE University

 A complete design example
• Design a logic circuit that has three inputs,
A, B, and C, and whose output will be HIGH
only when a majority of the inputs are HIGH?
• Solution:
1. The output should be 1 whenever two or more
inputs are 1; for all other cases, the output
should be 0

3–17 ELEC 335, Digital Logic Design, UAE University

 A complete design example
• The truth table is shown below:
A B C Z
0 0 0 0
0 0 1 0 2. Write the AND terms
0 1 0 0
0 1 1 1 ABC
1 0 0 0
1 0 1 1 ABC
1 1 0 1 ABC
1 1 1 1 ABC
3–18 ELEC 335, Digital Logic Design, UAE University
 A complete design example
3. Write the SOP expression
x = A’BC + AB’C + ABC’ + ABC

4. Simplify the expression

x = A’BC + AB’C + ABC’ + ABC
x = A’BC + AB’C + AB(C’ + C)
x = A’BC + A(B + B’C) = A’BC + AB + AC
x = B(A + A’C) + AC = AB + BC + AC

ELEC 335, Digital Logic Design, UAE

University
 A complete design example
5. Implement the circuit for the final expression
AB + AC + BC

AB
A
B

C AC AB + AC + BC

BC

3–20 ELEC 335, Digital Logic Design, UAE University

 Complement of a function
• The complement of a function, F, is obtained from
an interchange of 1’s to 0’s and 0’s to 1’s for the
values of F in the truth table
• The complement of a function can be obtained
algebraically by applying Demorgan’s theorem

• Ex: F = X Y Z + X Y Z
F = X Y Z + Z Y Z = (X Y Z) (X Y Z)
= (X + Y + Z) (X + Y + Z)

3–21 ELEC 335, Digital Logic Design, UAE University

 Standard Expression Forms
• Two standard (canonical) expression forms
– Canonical sum form
• disjunctive normal form or sum-of-products
• OR of AND terms
– Canonical product form
• conjunctive normal form or product-of-sums
• AND or OR terms
• In both forms, each first-level operator
corresponds to one row of truth table
• 2nd-level operator combines 1st-level results

3–22 ELEC 335, Digital Logic Design, UAE University

 Standard Forms (cont.)
Standard Sum Form
Sum of Products (OR of AND terms)

( ) ( ) (
F = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + (A ⋅ B ⋅ C ))
Minterms

Standard Product Form

Product of Sums (AND of OR terms)

( )(
F = A+ B+C ⋅ A+ B+C ⋅ A+ B+C ⋅ A+B+C )( )( )
Maxterms

3–23 ELEC 335, Digital Logic Design, UAE University

 Standard Sum Form
• Each product (AND) term is a Minterm
– ANDed product of literals in which each variable
appears exactly once, in true or complemented
form (but not both!)
– Each minterm has exactly one ‘1’ in the truth table
– When minterms are ORed together each minterm
contributes a ‘1’ to the final function

3–24 ELEC 335, Digital Logic Design, UAE University

 Minterms and Standard Sum Form
A B C Minterms F
0 0 0 m0 = A ⋅ B ⋅ C 1
0 0 1 m1 = A ⋅ B ⋅ C 0
0 1 0 m2 = A ⋅ B ⋅ C 0
0 1 1 m3 = A ⋅ B ⋅ C 1
1 0 0 m4 = A ⋅ B ⋅ C 0
1 0 1 m5 = A ⋅ B ⋅ C 0
1 1 0 m6 = A ⋅ B ⋅ C 1
1 1 1 m7 = A ⋅ B ⋅ C 1

F = A ⋅B⋅C + A ⋅B⋅C + A ⋅B⋅C + A ⋅B⋅C

F(A, B, C ) = m 0 + m 3 + m 6 + m 7
F(A, B, C ) = ∑ m(0, 3, 6, 7 )
3–25 ELEC 335, Digital Logic Design, UAE University
 Standard Product Form
• Each OR (sum) term is a Maxterm
– ORed product of literals in which each variable
appears exactly once, in true or complemented
form (but not both!)
– Each maxterm has exactly one ‘0’ in the truth
table
– When maxterms are ANDed together each
maxterm contributes a ‘0’ to the final function

3–26 ELEC 335, Digital Logic Design, UAE University

Maxterms and Standard Product Form
A B C Maxterms F
0 0 0 M0 = A + B + C 1
0 0 1 M1 = A + B + C 0
0 1 0 M2 = A + B + C 0
0 1 1 M3 = A + B + C 1
1 0 0 M4 = A + B + C 0
1 0 1 M5 = A + B + C 0
1 1 0 M6 = A + B + C 1
1 1 1 M7 = A + B + C 1

( )(
F = A+ B+C ⋅ A+ B+C ⋅ A+ B+C ⋅ A+ B+C)( )( )
F(A, B, C ) = M1 ⋅ M 2 ⋅ M 4 ⋅ M 5
F(A, B, C ) = ∏ M(1, 2, 4, 5)
3–27 ELEC 335, Digital Logic Design, UAE University
A sum term is one or more literals connected by OR operators.
A standard sum term, also called a maxterm, is a sum term that
includes each variable of the problem, either uncomplemented
or complemented.
A product of sums expression (POS) is one or more sum terms
connected by AND operators.
A canonical product or product of standard sum terms is just a
product of sums expression where all of the terms are standard
sum terms.
SOP:
POS:
x′y + xy′ + xyz
(x + y′)(x′ + y)(x′ + z′)
therefore!
both: x′ + y + z or xyz′
neither: x(w′ + yz) or z′ + wx′y + v(xz + w′)
ELEC 335, Digital Logic Design, UAE
University
 Karnaugh Map Minimization

• Karnaugh Map (or K-map) minimization is a

visual minimization technique
– Procedure guarantees a minimal expression
– Easy to use; fast
– Problems include:
• Applicable to limited number of variables (4 ~ 8)
• Errors in translation from TT to K-map
• Not grouping cells correctly
• Errors in reading final expression

3–29 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)
• Basic K-map is a 2-D rectangular array of
cells
– Each K-map represents one bit column of output
– Each cell contains one bit of output function
• Arrangement of cells in array facilitates
recognition of adjacent terms
– Adjacent terms differ in one variable value;
equivalent to difference of one bit of input row
values
• e.g. m2 (010) and m3 (011)

3–30 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)
• For any cell in 2-D array, there are four
direct neighbors (top, bottom, left, right)
• 2-D array can therefore show adjacencies of
up to four variables. AB
A
C 00 01 11 10
AB A
CD 00 01 11 10 Four Three 0

00 variable variable 1 C

01 K-map K-map
D B
11
C
10
cells are adjacent
B top to bottom and side to side.

3–31 ELEC 335, Digital Logic Design, UAE University

Karnaugh maps
The Karnaugh map (K-map) is a tool for simplifying
combinational logic with 3 or 4 variables. For 3 variables,
8 cells are required (23).
The map shown is for three variables
labeled A, B, and C. Each cell ABC ABC
represents one possible product
term. ABC ABC

Each cell differs from an adjacent ABC ABC

cell by only one variable.
ABC ABC
 Karnaugh maps

Cells are usually labeled using 0’s and 1’s to represent the
variable and its complement.
C The numbers are entered in gray
0 1
AB code, to force adjacent cells to be
00 different by only one variable.

Gray 01 Ones are read as the true variable

code and zeros are read as the
11
complemented variable.
10
Karnaugh maps

Alternatively, cells can be labeled with the variable letters.

This makes it simple to read, but it takes more time
preparing the map.
CC CC
Read the terms for the AB
AB ABC ABC
yellow cells.
AB
AB ABC
ABC ABC

The cells are ABC and ABC. AB

AB ABC ABC

AB ABC
AB ABC
ABC
 Karnaugh maps
K-maps can simplify combinational logic by grouping
cells and eliminating variables that change.
Group the 1’s on the map and read the minimum logic.

C 0 1
AB
1 1. Group the 1’s into two overlapping
00
B changes groups as indicated.
across this 01 1 1 2. Read each group by eliminating any
boundary variable that changes across a
11
boundary.
10 C changes
3. The vertical group is read AC.
across this 4. The horizontal group is read AB.
boundary
X = AC +AB
Karnaugh maps
A 4-variable map has an adjacent cell on each of its four
boundaries as shown.
Each cell is different only by
CD CD CD CD
one variable from an adjacent
AB
cell.
AB Grouping follows the rules
AB
given in the text.
The following slide shows an
AB
example of reading a four
variable map using binary
numbers for the variables…
 Karnaugh maps
Group the 1’s on the map and read the minimum logic.
C changes across
outer boundary
CD
AB
00 01 11 10 1. Group the 1’s into two separate
00 1 1 groups as indicated.
B changes 2. Read each group by eliminating
01 1 1 any variable that changes across a
11 1 1
boundary.
B changes 3. The upper (yellow) group is read as
10 1 1 AD.
4. The lower (green) group is read as
C changes
AD.
X
X = AD +AD
 Karnaugh Map Minimization (cont.)

Two-variable Karnaugh maps.

3–38 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)
Three-variable maps.

Product terms corresponding to groups of two.

3–39 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)
The four-variable map

3–40 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)

Entry of TT data into K-map

b3 b2 b1 b0 x3
0 0 0 0 0 AB A
0 0 0 1 0
CD 00 01 11 10
0 0 1 0 0
0 0 1 1 0 00 0 0 0 1
0 1 0 0 0
0 1 0 1 1
01 0 1 0 1
0 1 1 0 1
0 1 1 1 1 D
1 0 0 0 1 11 0 1 0 0
1 0 0 1 1 C
1 0 1 0 - 10 1 0 0
1 0 1 1 - 0
1 1 0 0 - Use 0’s
1 1 0 1 - for now B
1 1 1 0 -
1 1 1 1 -

3–41 ELEC 335, Digital Logic Design, UAE University

 Karnaugh Map Minimization (cont.)
x ′yz ′ + x′yz + xy ′z ′ + xy ′z + xyz.
A better solution

The minimum solutions.

3–42 ELEC 335, Digital Logic Design, UAE University

 Implicants and Prime Implicants
Single cells or groups that
could be part of a larger
group are know as implicants
AB A
CD 00 01 11 10
00 0 0 0 1
A group that is as large as
01
possible is a prime implicant
0 1 0 1

11 1 1 0 0
D
Implicants
C
10 1 1 0 0 Single cells can be prime
B
implicants is they cannot be
grouped with any other cell
Prime Implicants

3–43 ELEC 335, Digital Logic Design, UAE University

 Implicants and Minimal Expressions
• Any set of implicants that encloses (covers)
all values is “sufficient”; i.e. the associated
logical expression represents the desired
function.
– All minterms or maxterms are sufficient.
• The smallest set of prime implicants that
covers all values forms a minimal expression
for the desired function.
– There may be more than one minimal set.

3–44 ELEC 335, Digital Logic Design, UAE University

 K-map Minimization
We want a sum of
products expression so
A
CD
AB
00 01 11 10
we circle 1s
ABD* 00 0 0 0 1 ABC* * PIs are essential; no
01
implecant remain ( no
0 1 0 1
D secondary PIs).
C
11 0 1 0 0
The minimal expression
ABC*
10 0 1 0 0 is:
B

X 3 = A BC + ABC + ABD

3–45 ELEC 335, Digital Logic Design, UAE University

 K-Map with Don’t Cares
• For expression minimization, don’t care
values (- or x) can be assigned either 0 or 1
– Hard to use in algebraic simplification; must
evaluate all possible combinations
– K-map minimization easily handles don’t cares

• Basic don’t care rule for K-maps include the

dc (- or x) in group if it helps to form a larger
group; else leave it out

3–46 ELEC 335, Digital Logic Design, UAE University

 K-map Minimization of X3 with Don’t Cares

We want a sum of
AB A products expression so
CD 00 01 11 10 we circle 1s and x’s
BD* 00 0 0 x 1 A* (don’t cares)
01 0 1 x 1 * PIs are essential; no
D
11 0 1 x x
other implicants remain
C ( no secondary PIs).
10
BC* 0 1 x x
The minimal expression
B is:

X 3 = A + BC + BD

3–47 ELEC 335, Digital Logic Design, UAE University