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ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
Analysis and Design of CMOS Source Followers and
Super Source Follower
Mr. D. K. Shedge1, Mr. D. A. Itole2, Mr. M. P. Gajare3, and Dr. P. W. Wani4
123
AISSMS IOIT, Electronics Engineering Dept., Pune, India
Email: dshedge@yahoo.com
4
College of Engineering, Electronics and Telecommunication Dept., Pune, India
Email: cooldev.itole@gmail.com and pwwani@gmail.com
Abstract— The source follower circuit is used as a voltage voltage minus gate source voltage. The gate source voltage
buffer and level shifter. It is more flexible level shifter as the consists of threshold and over drive voltage. If both these
dc value of voltage level can be adjusted by changing aspect voltages are constant, then output voltage is simply input
ratio of MOSFETs. It is desired to have low output resistance
voltage added with offset. The small signal gain would then
for such applications. Source follower can give minimum
output resistance 1/(gm+g mb) with load resistance and channel
be unity. Thus, the source follows the gate and circuit is
resistance tending to infinity. The super source follower is a known as a source follower. Actually threshold voltage de-
circuit formed using negative feedback through another pends on the body effect and the over drive depends on
MOSFET. This offers even reduced output resistance but with drain current. Also even if the drain current is kept constant,
reduced voltage gain as that of source follower. the over drive depends to some extent on the drain-source
voltage. Small signal equivalent circuits of MOSFETs with
Index Terms— NMOS Source follower (NSF), PMOS Source body effect can evaluate the analysis of source follower cir-
follower (PSF), Super Source follower (SSF), Voltage buffer, cuits.
Level shifter, output resistance.
B. Small Signal Analysis of NSF
I. INTRODUCTION The NSF in Fig. 1 consists of an NMOS input transistor
A high voltage gain can be achieved from common source and an NMOS current source as a load [9]. The input signal
amplifier with high load impedance [5]. If amplifier is required Vi consists of the DC biasing voltage VTH and the ac signal vi
to drive a low impedance load then a buffer must be placed whereas the output signal Vo consists of a DC biasing voltage
after amplifier. A buffer will drive the low impedance load with VDS and the ac signal vo. For n-well process, the bulks of M1
negligible loss of signal strength [2]. and M2 share the same substrate. Hence, NSF suffers from
The common drain stages (source followers) are used as the body effect.
building blocks in a large number of high speed or high The small signal equivalent circuit of NSF is shown in
frequency applications, due to their intrinsic simplicity and Fig. 2. The body terminal is connected to lowest supply
wideband characteristics [7] [8]. The source followers suffer voltage (ground) to maintain source body junction reverse
from non-ideal effects such as body effect, channel length biased. Since source is connected to output, vbs changes
modulation, capacitive effects and distortions arising from with output [1]. The load current source formed with M2 is
capacitive loads. These non-ideal effects create a tradeoff replaced by its drain resistance ro2.
among linearity, bandwidth and power dissipation. The main
objective of this paper is to analyze and design the NSF, PSF
and SSF for wide bandwidth with low power consumption at
2.5V supply. The analysis of source followers is based on
non-linear parameters gm, gmb and ro in a low frequency small
signal model.
Section II describes the analysis of NMOS, PMOS and
Super source followers with small signal low frequency
models. In section III, the proposed circuits of source
followers and super source follower are presented. The
performances of the three source followers are observed using
EDA Tool Tanner V14.1 and Cadence. Concluding remarks
are made in Section IV.
II. ANALYSIS OF SOURCE FOLLOWER
For NSF as well as PSF, the input signal is applied to the
gate and output is taken from the source. For signal levels
Figure 1. NMOS Source follower (NSF) circuit
above threshold voltage, the output voltage is equal to input
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ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
Figure 2. Small signal equivalent circuit of NSF
Applying KVL around input loop,
vi = vgs + vo (1)
When the output is open circuited, io= 0 and applying KCL
at output node gives Figure 3. PMOS Source follower (PSF) circuit
0 (2) (6)
From (1) substituting for vgs in (2) and rearranging,
(7)
g m r o1 It is seen that the body effect reduces the output
resistance, which is desirable as the source follower produces
r
1 g m g mb r o1 o1
r o2
(3) a voltage output. This desired effect results from the non-
If load current source is ideal (3) simplifies to zero small signal current drawn by the gmb generator. As
and this output resistance becomes 1/
(4) (gm+gmb), same as input resistance of common gate amplifier.
The source followers are used as buffers and level shifters.
If ro1 is finite, the open circuit voltage gain of source They are more flexible as a level shifter because the dc value
follower is less than unity even if body effect is neglected. of VGS can be change by aspect ratio W/L.
The variation in output voltage changes the drain-source B. Small signal analysis of PSF
voltage and the current through ro1. The large signal analysis
With the circuit of PSF, the most of designs have utilized
shows that the over drive on gate also depends on the drain
a body tied PMOS input transistor to remove the bulk
source voltage unless channel length modulation is
modulation effect and to improve the precision. This is
negligible. This causes the small signal gain to be less than
possible as PMOS and NMOS transistors share the same
unity.
substrate. Due to lower mobility of PMOS devices, this results
in higher output impedance than NSF. Also the
(5) transconductance efficiency is low in PSFs which results
into small drive ability and a larger silicon area.
Fig. 3 shows a conventional PSF in an n-well process
The (5) shows that the voltage gain of the source follower
which includes a PMOS input transistor and a PMOS current
is less than unity and it depends on χ= gmb/gm, which is in the
source. The small signal equivalent model for PSF will be
range of 0.1 to 0.3. In addition, χ depends on source-body
same as NSF. In high frequency equivalent model, PSF will
voltage, which is Vo when the body is grounded. Hence, gain
have additional capacitance due to bulk-well. In addition, the
found out in (5) depends on output voltage, causing
channel length modulation coefficients of M1 and M2 in PSF
distortion for large signal changes in the output. This can be
are smaller than that of NSF. This gives better linearity of
overcome by selecting the type of source follower n-channel
PSF.
or p-channel fabricated in an isolated well. The well can be
connected to source making vsb =0. In this case the parasitic C. The Super source follower
capacitance from well to substrate increases reducing the The output resistance of source follower is approximately
bandwidth of source follower. 1/(g m+g mb ) [3]. As MOSFETs have much lower
The output resistance of source follower can be calcu- transconductance, this output resistance may be too high
lated from Fig. 2 by driving the output with a voltage source especially when a resistive load is to be driven. The output
vo and setting vi = 0. resistance can be reduced by increasing aspect ratio W/L of
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ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
source follower and its dc bias current. Assuming I1 and I2 to be ideal current sources, also
This requires a proportionate increasing the area and and (gm1+gmb1)ro1>>1,
power dissipation. To minimize the area and power dissipation
required for low Ro, the source follower configuration is used
as shown in Fig. 3.
Figure 5.Small signal equivalent circuit of super source follower
(11)
This is the output resistance of super source follower.
Comparing (11) with the output resistance of source follower
(7), shows that the negative feedback through M2 reduces
the output resistance by a factor of about gm2ro1.
The open circuit gain of super source follower can be
Figure 4. Super-source follower circuit
found out from small signal equivalent circuit with the output
The super follower as shown in Fig. 4 uses negative open circuited. Applying KCL at the output node gives,
feedback through M2 to reduce the output resistance [4].
The qualitative analysis shows that, when the input voltage (12)
is constant and the output voltage increases; the drain current
of M1 also increases, resulting into increased gate-source Also applying KCL at drain of M1 gives
voltage of M2. (13)
As a result, the drain current of M2 increases, reducing
the output resistance. The dc bias current in M2 is the different Substituting for v2 from (12) into (13) and rearranging gives
between I1 and I2, therefore I1 > I2 is required for proper
operation. This condition can be used to find small signal (14)
parameters of MOSFETs. The small signal equivalent circuit
is shown in Fig. 5. The body effect of M2 is neglected because
vbs2= 0. The polarities voltage controlled current sources for With ideal current sources,
NMOS and PMOS are identical. The current sources I1 and I2
(15)
are replaced by their internal resistances r1 and r2 respectively.
If current I1 and I2 are ideal, and . For practical Comparing the open circuit voltage gain of the super
current sources these resistances are large but finite. source follower (15) with the open circuit voltage gain of a
To find output resistance of the super source follower, simple source follower (4) shows that the deviation of this
set vi =0 and find the current io that flows into the output gain from unity is greater in super source follower than a
node when it is driven by a voltage vo. Applying KCL at simple source follower. If gm2ro2 >>1, this difference is small
output under these conditions to Fig. 5, and the conclusion is that the super source follower has little
effect on the open circuit voltage gain. The product gmro for
(8)
MOSFET is given by relation
Similarly applying KCL at drain of M1 with vi = 0,
(16)
(9)
Where µ is mobility of charge carriers, Cox is gate oxide
Substituting for v2 from (9) into (8) and rearranging gives, capacitance, λ is channel length modulation coefficient and
W/L is aspect ratio
(10) In addition, λ α 1/L, hence we get
(17)
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ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
Therefore the width and length can be adjusted to get B. PSF with current source load
desired product gmro without changing Id. The circuit of PSF is formed with load resistance replaced
by simple MOS current source using M2 similar to NSF. The
III. PROPOSED CIRCUITS PSF circuit is designed with dc bias drain current of 1mA and
dc level shift of 0.8V with supply voltage 2.5V. Then using
A. NSF with current source load basic equation for drain current, aspect ratio of M1 and M2 is
The circuit of NSF is formed with load resistance replaced calculated as 500/0.49(µm/µm) for M1 and 60/0.49 (µm/µm) for
by simple MOS current source using M2 as shown in Fig. 6. M2, moreover, applying dc voltage Vb = 0.6V.
This current source offers high resistance if operated in
C. SSF with current source load
saturation region [6]. The voltage applied at gate of M2 that
is Vb makes sure that M2 operates in saturation all the time For super source follower M1 is selected with aspect ratio
[10]. The source follower circuit is designed with dc bias 500/0.5 (µm/µm), being PMOS with bias current 1mA. Both
drain current of 1mA and dc level shift of 0.43V with supply current sources I1 and I2 (Fig. 4) are implemented using single
voltage 2.5V. Then using basic equation for drain current, MOSFETs M3 and M4 as shown in Fig. 7. The total current
aspect ratio of M1 and M2 is calculated as 200/0.45 (µm/µm) supplied by upper current source M3 is addition of dc bias
for M1 and 60/0.45 (µm/µm) for M2 and applying dc voltage current required for M1 and dc bias current required for M2.
Vb = 0.6V. As M2 provides negative feedback for super source follower
The circuit is simulated using EDA tool Tanner V14.1 with circuit, it is desired to draw less amount of current. Hence the
0.25 µm technology and Cadence with 0.18 µm technology. dimensions of M2 is selected 1/1 (µm/µm). This selected W
The small signal voltage gain as per simulation of the circuit and L of M2 will ensure small feedback current through M2
comes out to be 0.8323 and output resistance comes out to with high gmro as per (16) and (17). The dc bias current of M1
be 9.1k&!. In addition, bandwidth is measured which comes is 1mA, thus the dimension of M4 is selected W/L=60/0.5
out to be 350MHz. (µm/µm) with gate bias Vb2= 0.6V. The aspect ratio of M3 is
The result shows large deviation of small signal voltage selected to be 120/0.5 (µm/µm) with gate bias Vb1=1.9V to
gain from unity and the higher output resistance as compared supply desired bias currents to M1 and M2. The result of
to emitter follower simulation gives a small signal voltage gain 0.42 and the output
resistance 4.7k&! which is lower than that of NSF and PSF.
The bandwidth measured shows 800MHz, larger than that of
NSF and PSF as expected. The dimensions of MOSFETs
selected for three circuits are shown in Table I and simulated
results are shown in Table II.
TABLE I. DIMENSIONS OF MOSFET DEVICES
Asp ect Ratio (W/L) µm/µm
MOSFETs
NSF PSF SSF
M1 20 0/0.45 500/0.49 500/0.5
M2 60 /0.45 60/0.49 1/1
M3 ---- ---- 120/0.5
M4 ---- ---- 60/0.5
TABLE II.SIMULATED RESULTS
Figure 6. NSF with current source load
IV. CONCLUSIONS
It is observed from simulated results that voltage gain of
PSF comes out to be closer to unity than NSF. While the
bandwidth offered gets reduced in PSF. The other important
performance parameter, the output resistance is measured
lowest with SSF but at the cost of reduced voltage gain.. The
voltage gain of super source follower gets reduced by al-
most same proportion as that of output resistance. The su-
per source follower is useful in driving low input resistance
Figure 7. Super source follower with current mirror sources
loads. It is also used in bipolar technologies to reduce the
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ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
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