APPLICATION NOTE

 Data Generation and Configuration

for Spartan Series FPGAs

XAPP 126 June 14, 1999 (Version 1.1) Application Note by Ashok Chotai

Summary
This application note describes various methods to configure Spartan series FPGAs. Each configuration method is
described in detail. Information on necessary software programs to run with input files required, output files produced,
download cables used, and other hardware necessary to accomplish the task is discussed. This application note targets
users who are new to Xilinx devices and Alliance/Foundation series software tools, and is intended to make the configuration
and debugging flows easy to understand.
Xilinx Families
Spartan and SpartanXL

Introduction Figure 1). The program can also produce an LL file which is
used for debugging the device. The program is a part of the
A design is entered as a schematic or high level HDL implementation process. Additionally, the BitGen program
description and then implemented (translated, partitioned,
has the following options:
placed and routed) into a Spartan series FPGA using Xilinx
software tools. As a result, a bitstream is produced which is Configuration Options: configuration clock rate, RBT and
used to configure the FPGA. Xilinx FPGAs are built with LL file generation and Cyclic Redundancy Check (CRC)
static RAM and hence they need a data source such as a error check.
PROM or other intelligent interface to load the configuration I/O Programmability: TTL or CMOS thresholds for the
data upon power-up. inputs and outputs (Spartan family only), pull-up and
Configuration is the process of loading the bitstream into pull-down control for the dedicated configuration pins
one or more FPGAs to define the functional operation of (TDO, DONE, M0 and M1), Power Down Control (Spartan
the internal blocks (function look-up table, flip-flop, multi- XL family only) and 5V Tolerant I/Os (SpartanXL family
plexer, buffers, pull up/down, slew rate etc.) and their inter- only).
connections (pass transistors). Each configuration bit for Start-up Timing Options: User clock or configuration clock
the FPGA defines the state of a static memory cell that con- selection, control of the sequence of output events (DONE
trols either an internal block or its interconnections. The going High, user I/Os going active, and release of global
device can be configured through standard configuration Set/Reset).
pins or through the boundary scan (JTAG) interface.
Readback Options: User clock or configuration clock selec-
Xilinx Alliance/Foundation series software programs, the tion, bitstream verification and in-circuit debugging control.
files required by these programs, the download cables
used, and other hardware necessary to accomplish the Boundary Scan Options: Control of boundary scan based
configuration and debugging task are discussed in the fol- configuration and bitstream readback.
lowing section. Other Options: Tie unused internal nodes.

Software Programs The program can be run as a stand-alone tool from the
UNIX/DOS command prompt or by running the Configure
There are five different software programs that may be
step in the Flow Engine of the Xilinx Design Manager
required to run the configuration flow. They are: BitGen,
Graphical User Interface. For information on the
PROMGen, JTAG Programmer, Hardware Debugger and
command-line mode usage and options, refer to the
the HW-130 Programmer software. The first four programs
BitGen chapter of the Development System Reference
are part of the Alliance/Foundation series software and the
Guide. For instructions on graphical mode usage and
last program is a part of the HW-130 Programmer. The user
options, refer to the Implementation Options chapter of
may not need to run all of these programs. These programs
the Design Manager/Flow Engine Reference/User Guide.
are described briefly in this section.
PROMGen (PROM File Formatter)
BitGen (Configure - Flow Engine)
PROMGen formats single or multiple BIT files into a PROM
BitGen is a program that takes a mapped, placed and fully file or a straight HEX file (see Figure 1). The PROM file is
routed NCD design file as its input and produces a configu- used to program the PROM. The HEX file or the PROM file
ration bitstream - a BIT file with a .bit extension (see

XAPP 126 June 14, 1999 (Version 1.1) 1

is used by the microprocessor or other intelligent interface for all the devices is listed in the Spartan Program Data
to configure the FPGA. PROMGen needs to be run in the table (Table 17) in the Spartan/XL data sheet.
following situations:
The RBT (raw bit) file is an ASCII representation of the BIT
- The FPGA is configured using a serial or parallel PROM file. The main benefit of using the RBT file instead of the
- The FPGA is configured using a microprocessor BIT file is that this file can be viewed using a common text
editor. Also, the order in which the 1’s and 0’s appear in this
- To concatenate bitstream files for multiple devices, when file is actually what shows up on the DOUT pin of the FPGA
they are to be configured in a daisy chain during configuration. Monitoring the DOUT pin during the
- To split an existing PROM file into multiple PROM files configuration process helps in identifying whether the bit-
stream gets loaded into the correct device.
PROMGen can be run as a stand-alone program from the
UNIX/DOS command prompt or by running the PROM File The LL (logic allocation) file contains the position informa-
Formatter tool in the Xilinx Design Manager Graphical User tion of CLB flip flops, latches and the IOBs. The file is used
Interface (GUI). For instructions on the command-line if the user wants to perform an additional step of performing
mode usage and options, refer to the PROMGen chapter in the readback operation on the device, which is essentially
the Development System Reference Guide. For information reading the internal states of the configured device.
on the graphical mode usage, refer to the PROM File For- The HEX file has each hexadecimal digit representing four
matter Reference/User Guide. consecutive configuration bits in a BIT file. The file is typi-
cally used by the microprocessor based configuration.
JTAG Programmer
The PROM file is a formatted BIT file that can be used to
The JTAG Programmer software is used to load the config-
program the PROM. The file can be MCS, TEK or EXO for-
uration data into Xilinx FPGAs through boundary scan
mat.
(JTAG) pins and perform functional (boundary scan) tests
on a single FPGA or a daisy chain of FPGAs. The BSD file is the Boundary scan description file. The file
contains the description of test pins and test instructions. It
Hardware Debugger is used for boundary scan based configuration and testing.
The Hardware Debugger software is used to configure and A BSD file is required for every Xilinx and non-Xilinx device
debug a single FPGA, or configure a daisy chain of FPGAs. in the chain.
For a single device configuration, the software uses the BIT
file, RBT file or a PROM file (MCS, TEK, EXO). For multiple Programming Equipment
devices, it uses only the PROM file. For debugging, which This section describes the hardware equipment that is
is available only for a single device, the software uses BIT required to accomplish the device configuration. It assumes
and LL files. Also note that the software does not support that the user already has other equipment such as the sys-
configuration through the boundary scan (JTAG) interface. tem board with Spartan/XL device on it, the cables neces-
sary for probing and connecting the power source and the
HW-130 Programmer Software 3.3/5V DC power supply.
As the name implies, the HW-130 Programmer software
comes with the HW-130 Programmer. The program is used Xilinx Download Cables
to load the configuration data into Xilinx serial PROMs. The XChecker cable is an RS232 serial cable which con-
nects to the serial port of both the PC and the workstation.
Files for Configuration The cable supports configuration and debugging of
There are various files that are used in the configuration FPGAs. The Parallel Download Cable connects to the par-
flow. This section describes each file and its importance in allel port of the PC. This cable supports only the configura-
the configuration flow. tion of FPGAs. It has a higher drive capability and is much
faster than the XChecker cable. For more information on
The BIT file (configuration bitstream) is a binary represen-
these cables, refer to the Hardware User Guide.
tation of the logic design. The file is used to configure the
Xilinx device. It can also be used to create a PROM file. Xilinx HW-130/3rd Party Programmer
Note that the bitstream file size is a constant for any given
device, regardless of the amount of logic in it. Every bit in HW-130 Programmer is used to program the Spartan/XL
the device gets programmed, whether it is used or not. series serial PROMs. The programmer supports MCS,
Also, note that the same bitstream is used for Master/Slave EXO and TEK file formats. For more information, refer to
Serial Mode and the JTAG mode. However, the Express the HW-130 Programmer Data sheet or the On-Line help
mode bitstream has a different size and hence it cannot be which is available in the software.
used for any other configuration mode. The Express Mode The user can optionally use a 3rd party PROM program-
is available only in the SpartanXL family. The bitstream size mer. For a complete list of the programmers supporting Xil-

2 XAPP 126 June 14, 1999 (Version 1.1)

inx FPGAs, refer to the Programmer Solutions Technical XAPP122: The Express Configuration of SpartanXL
Tips on the Xilinx web site. FPGAs. The bitstream file for this mode is created by the
following command from the command prompt:
Configuration Modes
bitgen -g ExpressMode:Enable -g CRC:Disable -b infile
This section describes the various configuration modes in outfile
which the FPGA can be connected.
Since the Express Mode does not support error detection
The Spartan series can be configured through standard using CRCs, it is necessary to disable this feature with the
configuration pins or through the boundary scan interface. text “-g CRC: Disable”. For more information on configura-
Using the standard configuration pins, the Spartan family tion modes, refer to the Configuration and Test section in
has two modes and the SpartanXL family has three modes. the Spartan/XL data sheet.
The two modes common to both the families are Master
Configuration through the boundary scan interface is dis-
Serial Mode and Slave Serial Mode. These modes are
cussed in detail in the section “JTAG Flow” on page 6 of this
selected using the mode pin(s) on the device. In the Master
application note.
Serial mode, the FPGA generates its own configuration
clock (CCLK) to load the configuration data from an exter- Configuration Flows
nal memory source such as Xilinx serial PROM. In the
Slave Serial mode, an external signal drives the CCLK Xilinx FPGAs can be configured in several ways. The vari-
input of the FPGA to load the configuration data from an ous possible flows are: Debug flow, Any_File flow, JTAG
external device such as a lead FPGA or an intelligent inter- flow, Processor flow and PROM flow. The Debug flow is the
face such as a microprocessor. The slave serial mode is only flow which has additional capability of reading the
described in the application note XAPP098: The Low-Cost internal states of the configured device. The Debug,
Efficient Serial Configuration of Spartan FPGAs. Any_File and the JTAG flows need a Xilinx cable. Any of
these flows can be used based upon the requirements.
The SpartanXL family has an additional mode called These flows are summarized in Table 1 and shown graphi-
Express Mode. It has the same timing as Slave Serial cally in Figure 1. To encounter problems during configura-
Mode, except that it is 8 times faster as the data is pro- tion during any of these flows, refer to The Configuration
cessed one byte instead of one bit per CCLK cycle. The Problem Solver located on the Xilinx web site.
Express Mode is described in the application note
Table 1: Configuration Flows Overview

Flow Name Designer Goal Program Equipment1 Software Required2 Files Needed
Debug Prototype for a single device • XChecker Cable • Flow Engine BIT and LL
• Hardware Debugger
Any_File Prototype for a single device • XChecker/Parallel • Flow Engine BIT/RBT/PROM file
Cable • Hardware Debugger
JTAG Production/Prototype for • XChecker/Parallel • Flow Engine BIT and BSDL for
single device OR multiple Cable • JTAG Programmer each device
devices in daisy chain using
Boundary Scan interface3
PROM Prototype/Production stage • PROM • Flow Engine PROM file
for single device OR multiple • HW-130/3rd Party • PROM File Formatter
devices in daisy chain PROM Programmer • HW-130/3rd Party
Programmer software
Processor Prototype/Production stage • Microprocessor with • Flow Engine HEX/PROM file
for single device OR multiple memory • PROM File Formatter
devices in daisy chain using • Microprocessor firmware4
Micro-processor
1. The target board which includes the Spartan/XL device(s) must be already present.
2. All the software programs are part of Xilinx Alliance/Foundation series software tools, unless otherwise stated.
3. Boundary-scan (BSCAN) symbol must be instantiated in the design and you must have a separate BIT file for each FPGA
in the chain.
4. Not supplied by Xilinx.

Debug Flow data that was sent to the device and comparing it against
the original bitstream data to ensure that the device is
Debugging involves Readback Verify and Readback Cap-
loaded with the correct data. Readback Capture refers to
ture. Readback Verify consists of reading the programming

XAPP 126 June 14, 1999 (Version 1.1) 3

 NCD

BitGen
Configure (Flow Engine)

LL BIT RBT

PROMGen
PROM File Formatter

PROM file1 HEX

BSD2
Xilinx HW-130 or 3rd Party
PROM Programmer

Hardware Debugger & Hardware Debugger & JTAG Programmer &

XChecker/Parallel Cable PROM Intelligent Interface
XChecker Cable XChecker/Parallel Cable
(Single Device Only) (through JTAG Port) (e.g. microprocessor)

DEBUG ANY_FILE JTAG PROM PROCESSOR

Xilinx Cables LEGEND

Input/Output file name

Task or Program Name

Any one of the file types may be used

Figure 1: Spartan/XL Configuration Flows
NOTE:
1. The PROM file can be MCS, TEK or EXO file
2. Call the Xilinx hotline to get the BSD file for the Spartan/XL device

reading the internal states (flip flop outputs, CLB outputs, for this task. This method neither requires external storage
IOB outputs and the RAM/ROM bits) of the device to make for configuration data nor an external clock to synchronize
sure the design performs correctly. Note that debug pro- the configuration process. The XChecker cable itself con-
cess does not interfere with the normal operation of the tains static RAM and an internal oscillator circuit for clock
device. To get familiar with the configuration and debugging generation. The FPGA is configured in Slave Serial mode.
flow, use the Watch tutorial on the Xilinx web site. For more information on this mode, refer to the Slave
Serial Mode description under the Configuration and
The Debug Flow is useful when the designer wants to con-
figure and debug the prototype of the design. The Hard- Test section in the Spartan/XL data sheet. The following
ware Debugger software and the XChecker cable are used steps are required to perform the task:

4 XAPP 126 June 14, 1999 (Version 1.1)

1. Instantiate the READBACK symbol in your schematics or chapter of the Hardware Debugger Reference/User
HDL based design (Figure 2). Guide.

VCC VCC RT RT
READ_DATA GND
CLK DATA GND RD RD
READ_TRIGGER TRIG TRIG
READBACK OBUF OPAD
TRIG RIP CCLK CCLK
Spartan/XL
D/P DONE N.C.
IPAD TDI
IBUF DIN DIN N.C.
TCK
PROG PROGRAM N.C.
TMS
Figure 2: Example of Readback Schematic INIT1 INIT CLKI
N.C.
RST CLKO
Target System
For more information on the READBACK symbol and its
System Clock
description, refer to the Configuration and Test section
Cable Connector 1 Cable Connector 2
in the Spartan/XL data sheet.
Figure 3: XChecker Cable Connections
2. Create EDIF netlist for your design.
NOTE: 1. The INIT pin on the connector is marked as INIT by mistake
3. Implement the design to get the LL and BIT files.
5. Configuration and Debugging using Hardware Debugger
Set the Readback Clock to CCLK and check the field for
“Enable Bitstream Verification and In-Circuit Hardware Configure the device using the Hardware Debugger soft-
Debugging” in the Configuration Options window to use ware. Set the synchronous debug mode, clock options,
the internal clock in the FPGA to synchronize the read- trigger type settings and the signals to display and then
back data and create an LL file for readback. The Hard- perform the device readback and verify operations using
ware Debugger uses this file for the readback operation. the software. For more information on these operations,
Implement the design using Xilinx Foundation/Alliance refer to the Programming a Device or a Daisy Chain
implementation tools to create the bitstream. For more and Debugging a Device chapters in the Hardware
information on implementing the design, refer to Imple- Debugger Reference/User Guide or the online help
mentation Options chapter in the Design Man- which is available in the Hardware Debugger software.
ager/Flow Engine Reference/User Guide. Any_File Flow
4. XChecker Cable Connections
Here, any of the two cables - XChecker or Parallel cable
Make sure the mode pin(s) are set for slave serial mode. can be used to configure the device. The XChecker cable
Although these pins have weak pull-up resistor during must be connected to the serial port of the PC or worksta-
configuration, it is recommended to attach an external tion and the Parallel cable to the parallel port of the PC.
pull-up of 4.7 KΩ to make sure these pins are not float- Also, you can use any of these files: BIT, RBT or any
ing. Connect the cable connectors 1 and 2 to the target PROM file (MCS, TEK, EXO). The flows for these three
system as shown in Figure 3. This setup is used to per- files are described in the next section.
form synchronous debugging where the cable is used to
control the external system clock and the logic states of Using the BIT file
the design. The XChecker cable needs 5V DC power 1. Implement the design to get the BIT file.
which is drawn from the target system. The power supply
For more information, refer to Using the Design Man-
required is 5V DC for the system with Spartan device(s)
ager chapter in the Design Manager/Flow Engine Refer-
and 3.3V DC for the system that contains SpartanXL
ence/User Guide.
device(s). Since the XChecker cable must be powered
only with a 5V supply, a separate 5V supply may be used 2. XChecker/Parallel Cable Connections
for the SpartanXL system or an 3.3V XChecker adapter Make sure the mode pin(s) are set for slave serial mode.
(Order Number: HW-XCH3V) may be used that accepts Although these pins have weak pull-up resistor during
2.9-5.25V DC as input and provides the output stepped configuration, it is recommended to attach an external
up to 5V needed by the cable. pull-up of 4.7 KΩ to make sure these pins are not float-
Power up the board using the DC power supply. Invoke ing. Connect the XChecker cable connector 1 to the tar-
Hardware Debugger from the Design Manager window. get system as shown in Figure 4. The Parallel cable pin
For description of XChecker pin connections, refer to connections are the same as that of the XChecker cable
Tables 4_3 and 4_4 in the Connecting your Cable except that there is no connection to the INIT pin as the
cable does not have it. Power up the board using a 5V
DC supply if it has Spartan device(s) and 3.3V supply if it
has SpartanXL device(s).

XAPP 126 June 14, 1999 (Version 1.1) 5

 . ware Debugger Reference/User Guide or the online help
which is available in the software.
VCC VCC
GND GND JTAG Flow
Spartan/XL
CCLK CCLK If the user is testing a system using Boundary Scan, then
D/P DONE it is possible to configure the FPGA through the same
DIN DIN Boundary scan (JTAG) pins. This will minimize additional
PROG PROGRAM configuration circuitry. The JTAG Programmer software
INIT1 INIT
N.C. and one of the two cables, XChecker or Parallel, are
RST
Target System used for this purpose. The programming file used is a
BIT file. The BSDL files for all the Xilinx and non-Xilinx
Cable Connector 1
devices in the chain also must be available. The steps to
Figure 4: XChecker Cable Connections perform configuration are described below:
NOTE: 1. The INIT pin on the connector is marked as INIT by mistake
1. Instantiate the BSCAN symbol in your schematics or
3. Configuration using Hardware Debugger HDL based design.
Invoke the Hardware Debugger program from the Design Optional To User Logic
IBUF
Manager window and configure the device. For more
TDI TDI TDO TDO
information, refer to the Programming a Device or a
TMS TMS DRCK
Daisy Chain and Debugging a Device chapters in the TCK TCK IDLE To User
Hardware Debugger Reference/User Guide or the online From TDO1 SEL1
Logic
User Logic
help which is available in the software. TDO2 SEL2
BSCAN
Using the RBT file
Figure 5: Example of Boundary Scan
1. Implement the design to get the BIT and RBT files.
For more information, refer to Using the Design Man- 2. Implement the design to get the BIT file.
ager chapter in the Design Manager/Flow Engine Refer- For more information, refer to Using the Design Man-
ence/User Guide. ager chapter in the Design Manager/Flow Engine Refer-
2. Follow the steps 2 and 3 described in the previous sec- ence/User Guide.
tion “Using the BIT file” to configure the device. 2. XChecker/Parallel Cable Connections
Using the PROM file Connect one end of the Parallel cable to the PC port (see
Figure 6) and the other end to the target system. The
For a single device, the user may use the PROM file. But,
XChecker cable pin connections are same as the Paral-
for multiple devices in daisy chain, the PROM file must be
lel cable except that the RD pin on the cable must be
used. No other file format (BIT, RBT) is acceptable.
connected to the TDO pin of the target system. Power up
1. Implement the design to get the BIT file. the board using a 5V DC supply if it has Spartan
2. Create the PROM file using the PROM File Formatter in device(s) and 3.3V supply if it has SpartanXL device(s).
the Design Manager For more information, refer to the Hardware chapter of
the Hardware User Guide.
For more information, refer to the PROM File Formatter
VCC VCC
Reference/User Guide. GND
GND
3. XChecker/Parallel Cable Connections
TCK TCK TCK
Connect the XChecker or Parallel cable as shown in
TDI TDO TDI TDO
Figure 4. Follow the instructions described in the step 2 TDO
TDI Device 1 Device 2
of the previous section “Using the BIT file” to power up
TMS TMS
the board.
TMS
Target System
4. Configuration using Hardware Debugger
Invoke the Hardware Debugger program from the Design Cable Connector

Manager window. The program looks for the MCS file by Figure 6: Parallel Cable Connections
default. Optionally, the PROM format files TEK and EXO 3. Configuration
may also be used. Configure the device. For more infor-
mation, refer to the Programming a Device or a Daisy Invoke the JTAG Programmer program in the Design
Chain and Debugging a Device chapters in the Hard- Manager and configure the devices in the chain. For

6 XAPP 126 June 14, 1999 (Version 1.1)

 more information, refer to the JTAG Programmer Guide 4. Connecting the processor to an FPGA
or the online help which is available in the software. Select the appropriate configuration mode according to
For more information on boundary scan, refer to the your requirements. Connect the intelligent interface to
application note XAPP017: Boundary Scan in XC4000 the FPGA as shown in the corresponding circuit diagram
and XC5200 Series Devices, which also applies to the under the Configuration and Test section in the Spar-
Spartan series. tan/XL data sheet.

PROM Flow 5. Configuration

Here, the PROM is used to store the configuration data for Power up the board using a 5V DC supply if it has Spar-
an FPGA or a daisy chain of FPGAs. tan device(s) and 3.3V DC supply if it has SpartanXL
device(s). Configure the device.
1. Implement the design to get the BIT file.
2. Create the PROM file using PROM File Formatter in the References
Design Manager Data Sheets
For more information, refer to the PROM File Formatter • Spartan/XL data sheet
Reference/User Guide. (http://www.xilinx.com/partinfo/spartan.pdf)
3. Loading the PROM file into a PROM • Spartan/XL series Serial PROMs data sheet
To load the PROM file into a Xilinx serial PROM, use the (http://www.xilinx.com/partinfo/
HW-130 programmer or any third-party PROM program-
• HW-130 Programmer Data Sheet
mer. The byte-wide PROM can be used only for the
Express mode configuration. It can be from any third (http://www.xilinx.com/partinfo/program.pdf)
party PROM manufacturer. For information on program-
mers, refer to the HW-130 Programmer Users Manual or Application Notes
• XAPP017: Boundary Scan in XC4000 and XC5200
3rd party supplied documentation, if you are using a
Series Devices
non-Xilinx programmer.
(http://www.xilinx.com/xapp/xapp017.pdf)
3. Connecting PROM to an FPGA
Select the appropriate configuration mode according to • XAPP098: The Low-Cost Efficient Serial Configuration
the requirements. Connect the PROM to the FPGA by of Spartan FPGAs
(http ://www.xilinx.com/xapp/xapp098.pdf)
looking at corresponding circuit diagram under the Con-
figuration and Test section in Spartan/XL data sheet. • XAPP122: The Express Configuration of SpartanXL
FPGAs
4. Configuration
Power up the board using a 5V DC supply if it has Spar- (http://www.xilinx.com/xapp/xapp122.pdf)
tan device(s) and 3.3V DC power supply if it has Spar- • FPGA Configuration Application Notes
tanXL device(s). Configure the device. (http://support.xilinx.com/apps/config.htm)
Processor Flow Technical Support
Note that this section covers the topic in a very high level • The Configuration Problem Solver
without going into specific technical details. The user is (http://support.xilinx.com/support/techsup/journals/con-
advised to learn more based on the type of processor that fig/cps.htm)
is being used. This method is also described in the applica- • Hardware Debugger Watch Tutorial
tion note XAPP098: The Low-Cost Efficient Serial Configu-
ration of Spartan FPGAs. (http://support.xilinx.com/support/techsup/tutorials)
1. Implement the design to get the BIT file. • Programmer Solutions Technical Tips
2. Create the PROM file using PROM File Formatter in the (http://support.xilinx.com/support/programr/ps.htm)
Design Manager
Online Software Documents
Make sure that you create the file format that is accept- (http://support.xilinx.com/support/sw_manuals/)
able by the intelligent interface. For more information, • Design Manager/Flow Engine Reference/User Guide
refer to the PROM File Formatter Reference/User Guide. • Development System Reference Guide
3. Loading the PROM file • PROM File Formatter Reference/User Guide
• JTAG Programmer User Guide
Load the PROM file into RAM of the processor or any • Hardware Debugger Reference/User Guide
other configuration data storage device you are using. • Hardware User Guide

XAPP 126 June 14, 1999 (Version 1.1) 7