a Single-Chip, DSP-Based

High Performance Motor Controller

ADMC401
FEATURES Internal or External Voltage Reference
26 MIPS Fixed-Point DSP Core Out-of-Range Detection
Single Cycle Instruction Execution (38.5 ns) Voltage Reference
ADSP-21xx Family Code Compatible Internal 2.0 V  2.0% Voltage Reference
16-Bit Arithmetic and Logic Unit (ALU) Three-Phase 16-Bit PWM Generation Unit
Single Cycle 16-Bit
16-Bit Multiply and Accumulate Programmable Switching Frequency, Dead Time and
Into 40-Bit Accumulator (MAC) Minimum Pulsewidth
32-Bit Shifter (Logical and Arithmetic) Edge Resolution of 38.5 ns
Multifunction Instructions One or Two Updates per Switching Period
Single Cycle Context Switch Hardware Polarity Control
Zero Overhead Looping Individual Enable/Disable of Each Output
Conditional Instruction Execution High Frequency Chopping Mode
Two Independent Data Address Generators Dedicated Shutdown Pin (PWMTRIP)
Memory Configuration Additional Shutdown Pins in I/O System
2K
24-Bit Internal Program Memory RAM High Output Sink and Source Capability (10 mA)
2K
24-Bit Internal Program Memory ROM Incremental Encoder Interface Unit
1K
16-Bit Internal Data Memory RAM Quadrature Rates to 17.3 MHz
14-Bit Address Bus and 24-Bit Data Bus for External Programmable Filtering of Encoder Inputs
Memory Expansion Alternative Frequency and Direction Mode
High Resolution Multichannel ADC Two Registration Inputs to Latch Count Value
12-Bit Pipeline Flash Analog-to-Digital Converter Optional Hardware Reset of Counter
Eight Dedicated Analog Inputs Single North Marker Mode
Simultaneous Sampling Capability Count Error Monitor Function
All Eight Inputs Converted in <2 s Dedicated 16-Bit Loop Timer (Periodic Interrupts)
4.0 V p-p Input Voltage Range Companion Encoder Event (1/T) Timer
PWM Synchronized or External Convert Start
(Continued on Page 14)

FUNCTIONAL BLOCK DIAGRAM

26 MIPS DSP CORE

PM
ROM MEMORY MOTOR CONTROL
DATA 2K
24 PERIPHERALS
ADDRESS
GENERATORS PM DM WATCH- POWER- INTERRUPT EVENT DIGITAL
PROGRAM DOG ON ENCODER I/O
RAM RAM CONTROLLER INTERFACE CAPTURE
DAG 1 DAG 2
SEQUENCER 2K
24 1K
16 TIMER RESET UNIT UNIT

EXTERNAL PROGRAM MEMORY ADDRESS

ADDRESS
BUS DATA MEMORY ADDRESS

EXTERNAL PROGRAM MEMORY DATA

DATA
BUS DATA MEMORY DATA

ARITHMETIC UNITS SERIAL PORTS 2 CHANNEL PRECISION 16-BIT

INTERVAL 8 CHANNEL VOLTAGE PWM
SPORT 0 SPORT 1 TIMER AUXILIARY 12-BIT ADC
ALU MAC SHIFTER PWM REFERENCE GENERATION

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: [Link]
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADMC401–SPECIFICATIONS
(VDD = AVDD = 5 V  5%, GND = AGND = 0 V, TAMB = –40C to +85C,
RECOMMENDED OPERATING CONDITIONS CLKIN = 13 MHz, unless otherwise noted)
B Grade
Parameter Min Max Unit
VDD Digital Supply Voltage 4.75 5.25 V
AVDD Analog Supply Voltage 4.75 5.25 V
TAMB Ambient Operating Temperature –40 +85 °C

ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Max Unit
1, 2, 3
VIH HI-Level Input Voltage @ VDD = max 2.0 V
VIL LO-Level Input Voltage1, 2, 3 @ VDD = min 0.8 V
VOH HI-Level Output Voltage1, 3, 4, 5, 6 @ VDD = min, IOH = –1.0 mA 2.4 V
@ VDD = min, IOH = –0.1 mA VDD – 0.3 V
VOL LO-Level Output Voltage1, 3, 4, 5, 6 @ VDD = min, IOL = 2.0 mA 0.4 V
VOH HI-Level Output Voltage5 @ VDD = min, IOH = –10.0 mA 2.4 V
VOL LO-Level Output Voltage5 @ VDD = min, IOL = 10.0 mA 1.2 V
IIH HI-Level Input Current7 @ VDD = max, VIN = VDD max 10 µA
IIH HI-Level Input Current8 @ VDD = max, VIN = VDD max 100 µA
IIH HI-Level Input Current9 @ VDD = max, VIN = VDD max 10 µA
IIL LO-Level Input Current7 @ VDD = max, VIN = 0 V 10 µA
IIL LO-Level Input Current8 @ VDD = max, VIN = 0 V 10 µA
IIL LO-Level Input Current9 @ VDD = max, VIN = 0 V 100 µA
IOZH HI-Level Three-State Leakage Current10 @ VDD = max, VIN = VDD max 10 µA
IOZL LO-Level Three-State Leakage Current10 @ VDD = max, VIN = 0 V 10 µA
IDD Digital Supply Current (Idle)11 @ VDD = max 40 mA
IDD Digital Supply Current (Dynamic)12 @ VDD = max 110 mA
IDD Analog Supply Current @ AVDD = max 60 mA
CI Input Pin Capacitance13 VIN = 2.5 V, fIN = 1 MHz, 8 pF
TAMB = +25°C
CO Output Pin Capacitance13, 14 VIN = 2.5 V, fIN = 1 MHz, 8 pF
TAMB = +25°C
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0–PIO11.
2
Input only pins: PWMTRIP, PWMPOL, PWMSR, RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR
and PWD.
3
Programmable I/O Pins (PIO0–PIO11).
4
Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1, BG, BGH, PMS, DMS, BMS, RD, WR, PWDACK and A0–A13.
5
Output pins: AH, AL, BH, BL, CH and CL.
6
Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to V DD–0.3 V and GND+0.3 V assuming no dc loads.
7
Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD.
8
Input pins with internal pull-down PIO0–PIO11 and PWMTRIP.
9
Input pins with internal pull-up, PWMPOL and PWMSR.
10
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
11
Idle refers execution of the IDLE instruction. Deasserted pins are driven to V DD or GND. Current reflects device operation with CLKOUT disabled.
12
Current reflects device operating with no output loads.
13
Guaranteed but not tested.
14
Output Pin Capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.

–2– REV. B
 ADMC401
(VDD = AVDD = 5 V  5%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 13 MHz,
ANALOG-TO-DIGITAL CONVERTER VIN0 to VIN7 = 4.0 V p-p, VREF = 2.0 V, unless otherwise noted)
Parameter Test Conditions Min Typ Max Unit
AC SPECIFICATIONS
SNR Signal to Noise Ratio fIN = 1.0 kHz 68 70 dB
SNRD Signal to Noise and Distortion fIN = 1.0 kHz 66 69 dB
THD Total Harmonic Distortion fIN = 1.0 kHz –76 –70 dB
CTLK Channel-Channel Crosstalk fIN = 1.0 kHz –89 –72 dB
CMRR Common-Mode Rejection Ratio –90 –72 dB
PSRR Power Supply Rejection Ratio 0.025 0.1 % FSR
ACCURACY
INL Integral Nonlinearity ± 0.6 ± 1.5 LSB
DNL Differential Nonlinearity ± 0.5 ± 1.0 LSB
No Missing Codes 12 Bits Guaranteed
Zero Error 0.1 0.25 % FSR
Gain Error1 0.4 1.0 % FSR
TEMPERATURE DRIFT
Zero Error 0.025 % FSR
Gain Error1 0.025 % FSR
INPUT VOLTAGE
VIN Voltage Span 4.0 V p-p
CIN Input Capacitance2 10 pF
CONVERSION TIME
tCONV Total Conversion Time All 8 Channels 1.88 µs
NOTES
1
Excludes Internal Voltage Reference Error.
2
Analog Input Pins VIN0 to VIN7.
Typical values are neither tested nor guaranteed.
Specifications subject to change without notice.

(VDD = AVDD = 5 V  5%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 13 MHz, VIN0 to VIN7 =
VOLTAGE REFERENCE 4.0 V p-p, VREF = 2.0 V, unless otherwise noted)
Parameter Test Conditions Min Typ Max Unit
VREF Output Voltage Reference SENSE = REFCOM 1.96 2.0 2.04 V
Output Voltage Tolerance1 SENSE = REFCOM 6 mV
Output Current 1.0 mA
Load Regulation 1.0 mA Load Current 0.3 1.5 mV
Power Supply Rejection Ratio 0.1 1.5 mV
Reference Input Resistance 8 kΩ
NOTES
1
Relative tolerance due to temperature change, T MIN to TMAX.
Specifications subject to change without notice.

POWER-ON RESET (GND = AGND = 0 V, T AMB = –40C to +85C, CLKIN = 13 MHz, unless otherwise noted)
Parameter Test Conditions Min Typ Max Unit
VRST Reset Threshold Voltage 3.25 4.0 V
VHYST Hysteresis Voltage 75 mV
Specifications subject to change without notice.

REV. B –3–
ADMC401
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under absolute maximum ratings may cause permanent
damage to the device. These are stresses only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option
ADMC401BST –40°C to +85°C 26 MHz 144-Lead Plastic Thin Quad Flatpack (LQFP) ST-144
ADMC401-ADVEVALKIT Development Tool Kit
ADMC401-PB Evaluation/Processor Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the ADMC401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

Timing Parameters
GENERAL NOTES MEMORY REQUIREMENTS
Use the exact timing information given. Do not attempt to This chart links common memory device specification names
derive parameters from the addition or subtraction of others. and ADMC401 timing parameters for your convenience.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect Common
statistical variations and worst cases. Consequently, you cannot Parameter Memory Device
meaningfully add up parameters to derive longer times. Name Function Specification Name
tASW A0–A13, DMS, PMS Address Setup to
TIMING NOTES
Setup before WR Low Write Start
Switching characteristics specify how the processor changes its
tAW A0–A13, DMS, PMS Address Setup to
signals. You have no control over this timing; it is dependent on
before WR Deasserted Write End
the internal design. Timing requirements apply to signals that
tWRA A0–A13, DMS, PMS Address Hold Time
are controlled outside the processor, such as the data input for a
Hold after WR Deasserted
read operation.
tDW Data Setup before WR High Data Setup Time
Timing requirements guarantee that the processor operates tDH Data Hold after WR High Data Hold Time
correctly with another device. Switching characteristics tell you tRDD RD Low to Data Valid OE to Data Valid
what the device will do under a given circumstance. Also, use tAA A0–A13, DMS, PMS, Address Access Time
the switching characteristics to ensure any timing requirement BMS to Data Valid
of a device connected to the processor (such as memory) is
satisfied.

–4– REV. B
 ADMC401
Parameter Min Max Unit
Clock Signals
tCK is defined as 0.5tCKI. The ADMC401 uses an input clock
with a frequency equal to half the instruction rate; a 13 MHz
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor
cycle (equivalent to 26 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing
parameters to obtain specification value.
Example: tCKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
tCKI CLKIN Period 76.9 150 ns
tCKIL CLKIN Width Low 20 ns
tCKIH CLKIN Width High 20 ns
Switching Characteristics:
tCKL CLKOUT Width Low 0.5tCK – 10 ns
tCKH CLKOUT Width High 0.5tCK – 10 ns
tCKOH CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirement:
tRSP RESET Width Low 5tCK1 ns
PWM Shutdown Signals
Timing Requirements:
tPWMTPW PWMTRIP Width Low tCK ns
tPIOPWM PIO Width Low 2tCK ns
ADC Signals
Timing Requirements:
tCSI Internal Convert Start Width High 2tCK ns
tCSE External Convert Start Width High 2tCK ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).

t CKI
t CKIH

CLKIN

t CKIL t CKOH

t CKH

CLKOUT

t CKL

Figure 1. Clock Signals

REV. B –5–
ADMC401
Parameter Min Max Unit
Interrupts and Flags
Timing Requirements:
tIFS IRQx or FI Setup before CLKOUT Low1, 2, 3 0.25tCK + 15 ns
tIFH IRQx or FI Hold after CLKOUT High1, 2, 3 0.25tCK ns
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low4 0.5tCK – 7 ns
tFOD Flag Output Delay from CLKOUT Low4 0.5tCK + 5 ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further
information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0 and IRQ1.
4
Flag Output = FL1 and FO.

t FOD

CLKOUT

t FOH

FLAG
OUTPUTS

t IFH

IRQx
FI

t IFS

Figure 2. Interrupts and Flags

–6– REV. B
 ADMC401
Parameter Min Max Unit
Bus Request/Grant
Timing Requirements:
tBH BR Hold after CLKOUT High1 0.25tCK +2 ns
tBS BR Setup before CLKOUT Low1 0.25tCK + 17 ns
Switching Characteristics:
tSD CLKOUT High to DMS, PMS, BMS, 0.25tCK + 10 ns
RD, WR Disable
tSDB DMS, PMS, BMS, RD, WR
Disable to BG Low 0 ns
tSE BG High to DMS, PMS, BMS,
RD, WR Enable 0 ns
tSEC DMS, PMS, BMS, RD, WR
Enable to CLKOUT High 0.25tCK – 7 ns
tSDBH DMS, PMS, BMS, RD, WR
Disable to BGH Low2 0 ns
tSEH BGH High to DMS, PMS, BMS,
RD, WR Enable2 0 ns
NOTES
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t BH
CLKOUT

BR

t BS

CLKOUT

PMS, DMS
BMS, RD
WR t SD t SEC

BG
t SDB t SE

BGH
t SDBH t SEH

Figure 3. Bus Request–Bus Grant

REV. B –7–
ADMC401
Parameter Min Max Unit
Memory Read
Timing Requirements:
tRDD RD Low to Data Valid 0.5tCK – 11 + w ns
tAA A0–A13, PMS, DMS, BMS to Data Valid 0.75tCK – 12 + w ns
tRDH Data Hold from RD High 0 ns
Switching Characteristics:
tRP RD Pulsewidth 0.5tCK – 5 + w ns
tCRD CLKOUT High to RD Low 0.25tCK – 5 0.25tCK + 7 ns
tASR A0–A13, PMS, DMS, BMS Setup before RD Low 0.25tCK – 6 ns
tRDA A0–A13, PMS, DMS, BMS Hold after RD Deasserted 0.25tCK – 3 ns
tRWR RD High to RD or WR Low 0.5tCK – 5 ns
w = wait states × tCK.

CLKOUT

A0–A13

DMS, PMS
BMS
t RDA

RD
t ASR
t RP t RWR
t CRD

t RDD t RDH
t AA

WR

Figure 4. Memory Read

–8– REV. B
 ADMC401
Parameter Min Max Unit
Memory Write
Switching Characteristics:
tDW Data Setup before WR High 0.5tCK – 7 + w ns
tDH Data Hold after WR High 0.25tCK – 2 ns
tWP WR Pulsewidth 0.5tCK – 5 + w ns
tWDE WR Low to Data Enabled 0 ns
tASW A0–A13, DMS, PMS Setup before WR Low 0.25tCK – 6 ns
tDDR Data Disable before WR or RD Low 0.25tCK – 6 ns
tCWR CLKOUT High to WR Low 0.25tCK – 5 0.25tCK + 7 ns
tAW A0–A13, DMS, PMS, Setup before WR Deasserted 0.75tCK – 9 + w ns
tWRA A0–A13, DMS, PMS Hold after WR Deasserted 0.25tCK – 3 ns
tWWR WR High to RD or WR Low 0.5tCK – 5 ns
w = wait states × tCK.

CLKOUT

A0–A13

DMS, PMS

t WRA

WR

t ASW t WP t WWR
t AW
t DH t DDR
t CWR
D

t DW
t WDE

RD

Figure 5. Memory Write

REV. B –9–
ADMC401
Parameter Min Max Unit
Serial Ports
Timing Requirements:
tSCK SCLK Period 50 ns
tSCS DR/TFS/RFS Setup before SCLK Low 5 ns
tSCH DR/TFS/RFS Hold after SCLK Low 10 ns
tSCP SCLKIN Width 20 ns
Switching Characteristics:
tCC CLKOUT High to SCLKOUT 0.25tCK 0.25tCK + 15 ns
tSCDE SCLK High to DT Enable 0 ns
tSCDV SCLK High to DT Valid 20 ns
tRH TFS/RFSOUT Hold after SCLK High 0 ns
tRD TFS/RFSOUT Delay from SCLK High 20 ns
tSCDH DT Hold after SCLK High 0 ns
tTDE TFS(Alt) to DT Enable 0 ns
tTDV TFS(Alt) to DT Valid 20 ns
tSCDD SCLK High to DT Disable 20 ns
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 20 ns

CLKOUT
t CC t CC t SCK

SCLK
t SCP
t SCS t SCS t SCP
DR
RFSIN
TFSIN
t RD
t RH
RFSOUT
TFSOUT
t SCDD
t SCDV
t SCDH
t SCDE

DT
t TDE
t TDV
TFS
alternate
frame mode

t RDV
RFS
multichannel mode,
frame delay 0
(MFD = 0)

Figure 6. Serial Ports

–10– REV. B
 ADMC401
POWER DISSIPATION 3.0V
To determine total power dissipation in a specific application, INPUT 1.5V
0.0V
the following equation should be applied for each output:
C × VDD2 × f 2.0V
OUTPUT 1.5V
C = load capacitance, f = output switching frequency. 0.3V

Example:
In an application where external data memory is used and no Figure 7. Voltage Reference Levels for AC Measure-
other outputs are active, power dissipation is calculated as ments (Except Output Enable/Disable)
follows: Output Enable Time
Assumptions: Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
• External data memory is accessed every cycle with 50% of the driving. The output enable time (tENA) is the interval from when
address pins switching. a reference signal reaches a high or low voltage level to when
• External data memory writes occur every other cycle with the output has reached a specified high or low trip point, as
50% of the data pins switching. shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
• Each address and data pin has a 10 pF total load at the pin.
that of the first pin to start driving.
• The application operates at VDD = 5.0 V and tCK = 38.5 ns.
REFERENCE
Total Power Dissipation = PINT + (C × VDD2 × f) SIGNAL
tMEASURED
PINT = VDD × (IDD Digital + IDD Analog) tENA
(C × VDD2 × f) is calculated for each output: VOH tDIS VOH
(MEASURED) (MEASURED)
VOH (MEASURED) – 0.5V 2.0V
# of OUTPUT
Pins
C
VDD2
f VOL (MEASURED) +0.5V 1.0V
VOL VOL
Address, DMS 8 × 10 pF × 52 V × 26 MHz = 52.00 mW (MEASURED) tDECAY (MEASURED)
Data Output, WR 9 × 10 pF × 52 V × 13 MHz = 29.25 mW
RD 1 × 10 pF × 52 V × 13 MHz = 3.25 mW OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
CLKOUT 1 × 10 pF × 52 V × 26 MHz = 6.50 mW
91.00 mW HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Total power dissipation for this example is PINT + 91 mW. Figure 8. Output Enable/Disable

TEST CONDITIONS
Output Disable Time IOL

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY, TO
as shown in the Output Enable/Disable diagram. The time is the OUTPUT +1.5V
PIN
interval from when a reference signal reaches a high or low 50pF

voltage level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the IOH

following equation: Figure 9. Equivalent Device Loading for AC Measure-

C × 0.5 V ments (Including All Fixtures)
t DECAY = L
IL
from which
t DIS = t MEASURED − t DECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

REV. B –11–
ADMC401
PIN FUNCTION DESCRIPTION

Pin Pin Pin Pin Pin Pin Pin Pin

No. Name No. Name No. Name No. Name
1 A9 37 RFS1/IRQ0/SROM 73 GND 109 CONVST
2 A8 38 TFS1/IRQ1 74 D10 110 GND
3 A7 39 SCLK1 75 D9 111 VDD
4 A6 40 DR0 76 D8 112 GND
5 VDD 41 DT0 77 D7 113 AVDD
6 A5 42 RFS0 78 D6 114 AVSS
7 A4 43 TFS0 79 D5 115 VIN7
8 A3 44 SCLK0 80 D4 116 VREF
9 GND 45 VDD 81 D3 117 VIN6
10 A2 46 GND 82 GND 118 REFCOM
11 A1 47 PWMTRIP 83 D2 119 VIN5
12 A0 48 PWMSYNC 84 D1 120 CAPT
13 PWD 49 CL 85 D0 121 VIN4
14 PWDACK 50 CH 86 P11 122 BSHAN
15 BR 51 VDD 87 P10 123 ASHAN
16 NC 52 GND 88 P9 124 VIN0
17 NC 53 BL 89 P8 125 CAPB
18 BMODE 54 BH 90 VDD 126 VIN1
19 MMAP 55 AL 91 GND 127 CML
20 VDD 56 AH 92 P7 128 VIN2
21 GND 57 BGH 93 P6 129 GAIN
22 PWMSR 58 D23 94 P5 130 VIN3
23 POR 59 D22 95 P4 131 SENSE
24 RESET 60 D21 96 P3 132 AVSS
25 GND 61 D20 97 P2 133 AVDD
26 GND 62 D19 98 GND 134 BMS
27 GND 63 GND 99 P1 135 PMS
28 PWMPOL 64 D18 100 P0 136 DMS
29 CLKIN 65 D17 101 AUX1 137 RD
30 XTAL 66 D16 102 AUX0 138 GND
31 CLKOUT 67 D15 103 ETU1 139 BG
32 VDD 68 D14 104 ETU0 140 WR
33 GND 69 D13 105 EIS 141 A13
34 DR1A/FI 70 D12 106 EIZ 142 A12
35 DRIB/FI 71 VDD 107 EIB 143 A11
36 DT1/FO 72 D11 108 EIA 144 A10
NC: These pins must be left unconnected

–12– REV. B
 ADMC401
PIN CONFIGURATION

102 AUX0
101 AUX1
104 ETU0
103 ETU1

82 GND

73 GND
98 GND

91 GND
90 VDD

74 D10
87 P10
86 P11
108 EIA
107 EIB

105 EIS
106 EIZ

85 D0
84 D1
83 D2

81 D3
80 D4
79 D5
78 D6
77 D7
76 D8
75 D9
100 P0

89 P8
88 P9
99 P1

97 P2
96 P3
95 P4
94 P5
93 P6
92 P7
CONVST 109 72 D11
GND 110 71 VDD
VDD 111 70 D12
GND 112 69 D13
AVDD 113 68 D14
AVSS 114 67 D15
VIN7 115 66 D16
VREF 116 65 D17
VIN6 117 64 D18
REFCOM 118 63 GND
VIN5 119 62 D19
CAPT 120 61 D20
VIN4 121 60 D21
BSHAN 122 59 D22
ASHAN 123 58 D23
VIN0 124 57 BGH
CAPB 125 56 AH
VIN1 126 55 AL
CML 127
ADMC401
54 BH
VIN2 128 TOP VIEW 53 BL
(Not to Scale)
GAIN 129 52 GND
VIN3 130 51 VDD
SENSE 131 50 CH
AVSS 132 49 CL
AVDD 133 48 PWMSYNC
BMS 134 47 PWMTRIP
PMS 135 46 GND
DMS 136 45 VDD
RD 137 44 SCLK0
GND 138 43 TFS0
BG 139 42 RFS0
WR 140 41 DT0
A13 141 40 DR0
A12 142 39 SCLK1
PIN 1
A11 143 IDENTIFIER 38 TFS1/IRQ1
A10 144 37 RFS1/IRQ0/SROM
MMAP 19
VDD 20
GND 21
PWMSR 22
POR 23
RESET 24
GND 25
GND 26
GND 27
PWMPOL 28
CLKIN 29
XTAL 30
CLKOUT 31
VDD 32
GND 33
DR1A/F1 34
DR1B/FI 35
DT1/FO 36
A2 10
A1 11
A0 12
PWD 13
PWDACK 14
BR 15
NC 16
NC 17
BMODE 18
1
2
3
4
5
6
7
8
9
A9
A8
A7
A6
VDD
A5
A4
A3
GND

NC = NO CONNECT

REV. B –13–
ADMC401
(Continued from Page 1) data address generators and a program sequencer. The computa-
Programmable Digital I/O (PIO) Port tional units comprise an ALU, a multiplier/accumulator (MAC)
12-Pin Configurable Digital I/O Port and a barrel shifter. The DSP core also adds instructions for bit
Flexible Interrupt Generation manipulation, squaring (x2), biased rounding and global inter-
Four Dedicated PIO Interrupt Vectors rupt masking. In addition, two flexible double-buffered, bidirec-
Each I/O Line Configurable as PWM Shutdown tional synchronous serial ports are included in the ADMC401.
Two 8-Bit Auxiliary PWM Outputs The ADMC401 provides 2K × 24-bit internal program memory
Programmable Switching Frequency RAM, 2K × 24-bit internal program memory ROM and 1K ×
Independent or Offset Modes 16-bit internal data memory RAM. The program and data
Two-Channel Event Timer (Capture) Unit memory RAM can be boot loaded through the serial port from
Configurable Event Definition either a serial E2PROM, through a UART connection (either
Single-Shot or Free-Running Modes from external host microprocessor or from the Motion Control
Peripheral Interrupt Controller Debugger) or via a synchronous serial interface from a host
Manages Peripheral Interrupts microprocessor. Alternatively, the internal program and data
16-Bit Watchdog Timer memory RAM may be booted from an external device across the
Internal Power-On Reset System address and data buses. The program memory ROM includes a
Programmable 16-Bit Interval Timer with Prescaler monitor that adds software debugging features through the serial
Two Double Buffered Synchronous Serial Ports port.
Boot Load Protocols via SPORT1: Additionally, the ADMC401 device adds significant external
Synchronous E2PROM/SROM Booting
memory and peripheral expansion capabilities by making avail-
UART Boot Loader with Autobaud
able the full address and data bus of the DSP core. This feature
Synchronous Master or Slave Boot Loader permits expansion of both external program and data memory
Debugger Interface via SPORT1:
and means that the DSP core can address up to 14K × 24 bits of
UART Interface with Autobaud
external program memory and up to 13K × 16 bits of external
Synchronous Master or Slave Interface data memory.
Full Debugger for Program Development
Industrial Temperature Range –40C to +85C The ADMC401 contains a number of special purpose, motor
Operating Voltage 5.0 V  5% control peripherals. The first is a high performance, 8-channel,
Package: 144-Lead LQFP 12-bit ADC system with dual channel simultaneous sampling
ability across 4 pair of inputs. An internal precision voltage refer-
ence is also available as part of the ADC system. In addition, a
GENERAL DESCRIPTION three-phase, 16-bit, center-based PWM generation unit can be
The ADMC401 is a single-chip DSP-based controller, suitable used to produce high-accuracy PWM signals with minimal pro-
for high performance control of ac induction motors (ACIM), cessor overhead. The ADMC401 also contains a flexible incre-
permanent magnet synchronous motors (PMSM), brushless dc mental encoder interface unit for position sensor feedback;
motors (BDCM) and switched reluctance (SR) motors in indus- two adjustable-frequency auxiliary PWM outputs, 12 lines of
trial applications. The ADMC401 integrates a 26 MIPS, fixed- digital I/O; a 2-channel event capture system; a 16-bit watchdog
point DSP core with a complete set of motor control peripherals timer; two 16-bit interval timers (one of which can be linked to
that permits fast motor control in a highly integrated environment. the encoder interface unit) and an interrupt controller that man-
The DSP core of the ADMC401 is the ADSP-2171 which is ages all peripheral interrupts. Finally, the ADMC401 contains
completely code compatible with the ADSP-21xx DSP family an integrated power-on-reset (POR) circuit that can be used to
(as well as other members of the integrated motor controllers of generate the required reset signal for the device on power-on.
the ADMC3xx family) and combines three computational units,

–14– REV. B
 ADMC401
INSTRUCTION PM ROM 2
REGISTER POWER DOWN
2K
24 BOOT CONTROL
DM RAM
ADDRESS LOGIC
1K
16 GENERATOR
DATA DATA PM RAM
ADDRESS ADDRESS PROGRAM 2K
24
GENERATOR GENERATOR SEQUENCER
#1 #2

14 PMA BUS
14
EXTERNAL
14 DMA BUS ADDRESS BUS

24 PMD BUS

24
BUS EXTERNAL
EXCHANGE DATA BUS
16 DMD BUS

CONTROL COMPANDING
INPUT REGS INPUT REGS INPUT REGS CIRCUITRY TIMER
LOGIC

ALU MAC SHIFTER

TRANSMIT REG TRANSMIT REG
RECEIVE REG RECEIVE REG
OUTPUT REGS OUTPUT REGS OUTPUT REGS
SERIAL SERIAL
16 PORT 0 PORT 1

R BUS 5 6

Figure 10. DSP Core Block Diagram

ARCHITECTURE OVERVIEW The processor contains three independent computational units:

Figure 10 is a functional block diagram of the DSP core of the the arithmetic and logic unit (ALU), the multiplier/accumulator
ADMC401. The DSP core is based on the fixed-point ADSP- (MAC) and the shifter. The computational units process 16-bit
2171 core that is a member of the fixed-point ADSP-21xx data directly and have provisions to support multiprecision
family of general purpose DSPs from Analog Devices Inc. computations. The ALU performs a standard set of arithmetic
The ADSP-2171 flexible architecture and comprehensive in- and logic operations; division primitives are also supported. The
struction set allow the processor to perform multiple operations MAC performs single-cycle multiply, multiply/add, multiply/
in parallel. subtract operations with 40 bits of accumulation. The shifter
In one processor cycle (38.5 ns with a 13 MHz crystal) the DSP performs logical and arithmetic shifts, normalization, denormal-
core can: ization and derive exponent operations. The shifter can be used
to implement numeric format control efficiently, including
• Generate the next program address. floating-point representations. The internal result (R) bus di-
• Fetch the next instruction. rectly connects the computational units so that the output of
• Perform one or two data moves. any unit may be the input of any unit on the next cycle.
• Update one or two data address pointers. A powerful program sequencer and two dedicated data address
• Perform a computational operation. generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
This all takes place while the ADMC401 continues to:
routine calls and returns in a single cycle. With internal loop
• Receive and transmit through the serial ports. counters and loop stacks, the ADMC401 executes looping code
• Decrement the interval timers. with zero overhead; no explicit jump instructions are required to
• Generate PWM signals. maintain the loop.
• Convert the ADC input signals.
• Operate the encoder interface unit.
• Operate all other peripherals including the auxiliary PWM and
event timer subsystem.

REV. B –15–
ADMC401
Two data address generators (DAGs) provide addresses for register. When the value of the counter reaches zero, an inter-
simultaneous dual operand fetches from data memory and pro- rupt is generated and the count register is reloaded from a 16-
gram memory. Each DAG maintains and updates four address bit period register (TPERIOD).
pointers (I registers). Whenever the pointer is used to access The ADMC401 instruction set provides flexible data moves and
data (indirect addressing), it is post-modified by the value in multifunction (one or two data moves with a computation)
one of four modify (M) registers. A length value may be associ- instructions. Each instruction is executed in a single 38.5 ns
ated with each pointer (L registers) to implement automatic processor cycle (for a 13 MHz crystal). The ADMC401 assem-
modulo addressing for circular buffers. The circular buffering bly language uses an algebraic syntax for ease of coding and
feature is also used by the serial ports for automatic data trans- readability. A comprehensive set of development tools supports
fers to and from on-chip memory. DAG1 generates only data program development.
memory addresses but provides an optional bit-reversal capabil-
ity. DAG2 may generate either program or data memory ad- Serial Ports
dresses, but has no bit-reversal capability. The ADMC401 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
Efficient data transfer is achieved with the use of five internal multiprocessor communication. The following is a brief list of
buses: the capabilities of the ADMC401 SPORTs. Refer to the ADSP-
• Program Memory Address (PMA) Bus. 2100 Family User’s Manual, Third Edition for further details.
• Program Memory Data (PMD) Bus. • SPORTs are bidirectional and have a separate, double-
• Data Memory Address (DMA) Bus. buffered transmit and receive section.
• Data Memory Data (DMD) Bus. • SPORTs can use an external serial clock or generate their
• Result (R) Bus. own serial clock internally.
Program memory can store both instructions and data, permit- • SPORTs have independent framing for the receive and trans-
ting the ADMC401 to fetch two operands in a single cycle, one mit sections. Sections run in a frameless mode or with frame
from internal program memory and one from internal data synchronization signals internally or externally generated.
memory. The ADMC401 can fetch an operand from on-chip Frame synchronization signals are active high or inverted,
program memory and the next instruction in the same cycle. with either of two pulsewidths and timings.
SPORTs support serial data word lengths from 3 bits to 16
The ADMC401 writes data from its 16-bit registers to the 24-
bits and provide optional A-law and µ-law companding.
bit program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit • SPORT receive and transmit sections can generate unique
program memory to a 16-bit data register, the lower eight bits interrupts on completing a data word transfer.
are placed in the PX register. • SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An inter-
The ADMC401 can respond to a number of distinct DSP core
rupt is generated after a data buffer transfer.
and peripheral interrupts. The DSP core interrupts include
serial port receive and transmit interrupts, timer interrupts, • SPORT0 has a multichannel interface to selectively receive
software interrupts and external interrupts. In addition, there is and transmit a 24-word or 32-word, time-division multi-
a master RESET signal. The motor control peripherals also plexed, serial bitstream.
produce interrupts to the DSP core. • SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals. The
The two serial ports (SPORTs) provide a complete synchronous
internally generated serial clock may still be used in this
serial interface with optional companding in hardware and a
configuration.
wide variety of framed and unframed data transmit and receive
modes of operation. Each SPORT can generate an internal The following are additional capabilities of the ADMC401
programmable serial clock or accept an external serial clock. SPORTs that are not part of the ADSP-21xx products:
• SPORT1 is the input for single pin program and data
Boot loading of both the program and data memory RAM of the
memory boot loading. The RFS1 pin can be configured
ADMC401 can be through the serial port SPORT1. Alterna-
internally to the ADMC401 as an SROM/E2PROM reset
tively the ADMC401 can be boot loaded from an external byte-
signal.
wide memory connected to the external address and data buses.
After reset, seven wait states are automatically generated. This • SPORT1 has two data receive pins (DR1A and DR1B). The
permits, for example, a 38.5 ns ADMC401 to use an external DR1A pin is intended only for synchronous data receive
250 ns EPROM as boot memory. The internal boot address from the external E2PROM. The DR1B pin can be used as
generator provides the addresses for booting from an external the data receive pin for a general purpose SPORT after boot-
byte-wide memory. ing or as the data receive pin for other boot load modes or as
the UART/debugger interface. The DR1A and DR1B pins
A programmable interval counter is also included in the DSP are internally multiplexed onto the one data receive pin of
core and can be used to generate periodic interrupts. A 16-bit the SPORT. The particular data receive pin selected is deter-
count register (TCOUNT) is decremented every n processor mined by Bit 4 of the MODECTRL register.
cycles, where n-1 is a scaling value stored in the 8-bit TSCALE

–16– REV. B
 ADMC401
PIN FUNCTION DESCRIPTION INTERRUPT OVERVIEW
The ADMC401 is available in an 144-lead TQFP package. Table The ADMC401 can respond to different interrupt sources, some
I contains the pin descriptions. of which are internal DSP core interrupts and others from the
motor control peripherals. The DSP core interrupts include a:
Table I. Pin List • Power up (or RESET) interrupt.
Pin # • A peripheral (or IRQ2) interrupt.
Group of Input/ • A SPORT0 receive and a SPORT0 transmit interrupt.
Name Pins Output Function • A SPORT1 receive (or IRQ0) and a SPORT1 transmit (or
A13–A0 14 O Address Lines IRQ1) interrupt.
D23–D0 24 I/O Data Lines • Two software interrupts.
PMS, DMS, BMS 3 O External Memory Select Lines • An interval timer timeout interrupt.
RD, WR 2 O External Memory Read/Write Enable • A power-down interrupt.
MMAP 1 I Memory Map Select In addition, the motor control peripherals add other interrupts
POR 1 O Internal Power On Reset Output that include:
RESET 1 I Processor Reset Input • A PWMSYNC interrupt.
CLKOUT 1 O Processor Clock Output • An ADC end of conversion interrupt.
CLKIN, XTAL 2 I, O External Clock or Quartz Crystal • An encoder loop timer timeout interrupt.
Input
• Five peripheral input/output (PIO) interrupts.
BR 1 I Bus Request
• An event timer interrupt.
BG, BGH 2 O Bus Grant and Bus Hang Control
• An encoder count error interrupt.
BMODE 1 I Boot Mode Select
• A PWM trip interrupt.
PWD, PWDACK 2 I, O Power-Down and Power-Down
Acknowledge The interrupts are internally prioritized and individually maskable
SPORT0 5 I/O Serial Port 0 Pins (TFS0, RFS0, except for the nonmaskable power-down interrupt.
DT0, DR0, SCLK0) Memory Map
SPORT1 6 I/O Serial Port 1 (TFS1/IRQ1, RFS1/ The ADMC401 has two distinct memory types; program memory
IRQ0/SROM, DT1/FO, DR1A/FI, and data memory (in addition to external boot memory). In
DR1B/FI, SCLK1) general, program memory contains user code and coefficients,
VIN0–VIN7 8 I Analog Inputs while the data memory is used to store variables and data during
ASHAN, BSHAN 2 I Inverting Inputs to Sample and program execution. Both program memory RAM and ROM is
Hold Amplifiers provided internally on the ADMC401. The program memory
GAIN 1 I Analog Input for Gain Calibration map of the ADMC401 can be altered depending on the state of
VREF 1 I/O Reference Voltage Input/Output the MMAP and BMODE pins. The various program memory
maps are illustrated in Figure 11 for the permissible settings of
REFCOM 1 GND Reference Common
MMAP and BMODE. The state of these pins also impact the
CML 1 O Common-Mode Level (Midsupply) way in which the internal memory of the ADMC401 is booted,
CAPT, CAPB 2 O Noise Reduction Pins as described later.
SENSE 1 I Voltage Reference Select
There is 2K of internal ROM on the ADMC401. Setting the
CONVST 1 I External Convert Start ROMENABLE bit on the Data Memory Wait State Control
AH-CL 6 O PWM Outputs Register (at address DM (0x3FFE)) enables the ROM. When the
PWMTRIP 1 I PWM Shutdown Signal ROMENABLE bit is set to 1, addressing program memory in the
PWMPOL 1 I PWM Polarity Control ROM range will access the on-chip ROM. When ROMENABLE
PWMSYNC 1 O PWM Synchronization Output is set to zero, addressing program memory in this range will
PWMSR 1 I PWM Switched Reluctance Mode
access external program memory. The ROMENABLE bit is
Control initialized to zero after reset unless MMAP and BMODE = 1.
PIO0–PIO11 12 I/O Digital I/O Port When MMAP = BMODE = 0, the ADMC401 provides 2K × 24
ETU0, ETU1 2 I Event Timer Inputs bits of internal program memory RAM starting at address
AUX0–AUX1 2 O Auxiliary PWM Outputs
0x0000 that is booted from a byte-wide interface on the address
and data buses. Following boot loading, program execution
EIA, EIB, EIZ,
starts at address 0x0000. In this mode, the remainder of the
EIS 4 I Encoder Interface Inputs and
program memory space, a 12K × 24-bit block starting at address
External Registration Inputs
0x1000, is assigned to external memory.
NC 2 No Connect
AVDD 2 SUP Analog Power Supply When MMAP = BMODE = 1, the program memory map is
identical to the previous case, but ROMENABLE defaults to 1 at
AVSS 2 GND Analog Ground
reset, and execution starts from the internal program memory
VDD 8 SUP Digital Power Supply ROM located at address 0x0800. This permits the internal (and
GND 16 GND Digital Ground external if desired) memory to be boot loaded across the various
serial interfaces on SPORT1.

REV. B –17–
ADMC401
0x0000 0x0000 0x0000
2K INTERNAL RAM 2K INTERNAL RAM
(BOOTED FROM 2K EXTERNAL (BOOTED VIA
BYTE-WIDE EPROM) MEMORY SPORT1)
0x07FF 0x07FF 0x07FF
0x0800 2K INTERNAL ROM 0x0800 2K INTERNAL ROM 0x0800
(ROMENABLE = 1) (ROMENABLE = 1) 2K INTERNAL ROM
OR OR (ROMENABLE
2K EXTERNAL 2K EXTERNAL DEFAULTS TO 1
(ROMENABLE = 0) (ROMENABLE = 0) DURING RESET)
0x0FFF 0x0FFF 0x0FFF
0x1000 0x1000 0x1000

10K EXTERNAL
12K EXTERNAL MEMORY 12K EXTERNAL
MEMORY MEMORY

0x3800
2K INTERNAL RAM
0x3FFF 0x3FFF 0x3FFF
MMAP = 0 MMAP = 1 MMAP = 1
BMODE = 0 BMODE = 0 BMODE = 1

Figure 11. Program Memory Map of ADMC401

When MMAP = 1 and BMODE = 0, the internal program DWAIT3 and DWAIT4 fields of the Data Memory Wait State
memory RAM is mapped to the top of the program memory space Register (MEMWAIT) as illustrated in Figure 13. Following
(starting at address 0x3800) and no boot loading occurs. Program reset, DWAIT0 = DWAIT1 = DWAIT2 = DWAIT 3 =
execution starts from external program memory at address 0x0000. DWAIT4 = 7. However, in standalone mode with MMAP =
BMODE = 1, the internal monitor code writes 0 to these five
Only with ROMENABLE = 1 are the internal ROM monitor
fields. For correct operation DWAIT2 must always be 0. The
and debugger features of the ADMC401 available for program
configuration of the MEMWAIT register is shown at the end of
development. Additionally, certain spaces of the memory map
the data sheet.
have predefined functions as illustrated in Figure 12 where it
can be seen that address space 0x0000 to 0x005F is reserved for 0x0000 0x0000
the interrupt vector table. 0x03FF
DWAIT0

8K EXTERNAL 0x0400
DWAIT1
0x000 MEMORY 0x07FF
VECTOR TABLE 0x0800
DWAIT2
0x05F 0x1FFF
0x060 USER 0x2000 PERIPHERAL
PROGRAM REGISTERS 0x2FFF
SPACE 0x23FF
0x7FF 0x3000
0x2400 DWAIT3
0x800
5K EXTERNAL 0x3400
ROM MEMORY DWAIT4
MONITOR
0x37FF 0x3800
0xFEF 0x3800 INTERNAL USER
0xFF0
RESERVED 0x3B5F RAM
0xFFF 0x3B60
0x1000 RESERVED BY NO WAIT
0x3BFF MONITOR STATES
EXTERNAL 0x3C00 DSP CORE
MEMORY
REGISTERS/
RESERVED
0x3FFF 0x3FFF

Figure 13. Data Memory Map of the ADMC401

Figure 12. Detailed View of Program Memory Map with
MMAP = BMODE = 1 ROM Code
The 2K × 24-bit block of internal program memory ROM start-
The program memory interface can generate 0 to 7 wait states ing at address 0x800 contains a monitor function that can be
for external memory devices. The program memory wait state used to download and execute user programs via the serial port.
field (PWAIT) in the System Control Register controls the number In addition, the monitor function supports an interactive mode
of inserted wait states and defaults to 7. The structure of the in which commands are received and processed from a host that
System Control Register is shown at the end of the data sheet. is configured as a UART device. An example of such a host is
The data memory map of the ADMC401 is shown in Figure 13. the Windows-based Motion Control Debugger that is part of
The internal data memory RAM of the ADMC401 is arranged the software development system for the ADMC401. In the
as a single 1K × 16-bit block starting at address 0x3800. In interactive mode, the host can access both the internal DSP and
addition, there are two 1K blocks of reserved data memory peripheral motor control registers of the ADMC401, read and
space; one block starting at address 0x2000 that is reserved for write to both program and data memory, implement break-
the peripheral registers and one starting at address 0x3C00 that points and perform single-step operation as part of the program
is reserved for internal DSP core registers. Data memory wait debugging cycle. Again, this debugging feature is only available
states are controlled by the DWAIT0, DWAIT1, DWAIT2, when ROMENABLE = 1.

–18– REV. B
 ADMC401
SYSTEM INTERFACE voltage, VRST level. As soon as the threshold voltage is attained,
CLOCK SIGNALS the power on reset circuit enables a 17-bit counter that is
The ADMC401 uses an input clock with a frequency equal to clocked at the CLKOUT rate. While the counter is counting the
half the instruction rate; a 13 MHz input clock yields a 38.5 ns POR pin is held low. When the counter overflows, after a time:
processor cycle (which is equivalent to 26 MHz). Normally
instructions are executed in a single processor cycle. All device t RST = 216 × 38.5 × 10–9 = 2.52 ms
timing is relative to the internal instruction rate, which is indi- the POR pin is brought high and if the POR and RESET pins
cated by the CLKOUT signal (when enabled). Throughout this are connected, the device is brought out of reset.
data sheet, the period of the CLKIN signal is denoted by tCKI.
The DSP instruction period is tCK (the period of the CLKOUT The internal power-on reset circuit also acts as a power supply
signal), and tCK = 0.5 × tCKI. For 26 MIPS operation, a 13 MHz monitor and puts the POR pin at a LO level if it detects a volt-
CLKIN signal is used, corresponding to tCKI = 76.9 ns and tCK age less than VRST–VHYST, where VHYST is the hysteresis voltage
= 38.5 ns. Additionally, tCK is the fundamental time increment built into the POR circuit. The supply voltage must then exceed
of the motor control peripherals. Therefore, unless otherwise VRST to initiate another power-on reset sequence.
specified, the motor control peripherals are clocked at a rate
equal to CLKOUT. The ADMC401 can be clocked by either a
VDD VRST VRST - VHYST
crystal or by an external clock source. The CLKIN input cannot
be halted, changed in frequency, or operated below the specified t RST t RST
minimum frequency during normal operation. POR

If an external clock source is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is con- Figure 14. Operation of Power-On Reset (POR) Circuit of
nected to the CLKIN pin of the ADMC401. In this mode, with ADMC401
an external clock signal, the XTAL pin must be left unconnected. The master reset (RESET = LO) causes a Full System Reset,
Because the ADMC401 includes an on-chip oscillator circuit, which sets all internal stack pointers to the empty stack condi-
an external crystal may be used instead of a clock source. The tion, masks all interrupts, clears the MSTAT register, restores
crystal should be connected across the CLKIN and XTAL pins. the program counter to its initial value and performs a full reset
A parallel-resonant, fundamental frequency, microprocessor- of all of the motor control peripherals including the watchdog
grade crystal should be used. The frequency value selected for timer. Following a power-up, it is possible to initiate a Full
the crystal should be equal to half the desired instruction rate System Reset by simply pulling the RESET low. For these
for the processor. Figure 15 shows a 13 MHz crystal properly resets, there is no need to wait for PLL stabilization and the
connected to yield a 26 MHz processor rate. RESET signal must meet the minimum pulsewidth specifica-
tion, tRSP. To generate the external RESET signal, it is recom-
The CLKOUT output can be enabled and disabled by the mended to use either an RC circuit with a Schmitt trigger or a
CLKODIS bit of the SPORT0 Autobuffer Control Register, commercially available reset IC.
DM (0x3FF3). However, extreme care must be exercised when
using this bit (and is thus discouraged) since disabling CLKOUT Separate from a Full System Reset, a software controlled Periph-
effectively disables all motor control peripherals, except the eral Reset (excluding the watchdog timer) is achieved by toggling
watchdog timer. the DSP FL2 flag with the following code segment:
PRESET: SET FL2;
RESET AND POWER-ON RESET CIRCUIT TOGGLE FL2;
The RESET pin initiates a complete hardware reset of the TOGGLE FL2;
ADMC401 when pulled low. The RESET signal must be asserted RTS;
when the device is powered up to assure proper initialization.
The ADMC401 contains an integrated power-on reset circuit A full DSP and peripheral reset (except the watchdog timer
that provides an output reset signal, POR, from the ADMC401 itself) will occur automatically on a watchdog trip.
on power up and if the power supply voltage falls below the
threshold level. The ADMC401 may be reset from an external EXTERNAL MEMORY INTERFACE
source using the RESET signal or alternatively the internal The ADMC401 can address 14K × 24 bits of external program
power-on reset circuit may be used by connecting the POR pin memory and up to 13K × 16 bits of external data memory. The
to the RESET pin. During power-up the RESET line must be ADMC401 provides the address on a 14-bit address bus
activated for long enough to allow the DSP core’s internal clock (A13–A0). Instructions or data are transferred across the 24-bit
to stabilize. The power-up sequence is defined as the total time data bus (D23–D0) during program memory accesses. During
required for the crystal oscillator to stabilize after a valid VDD is data memory accesses, data is transferred on the 16 most signifi-
applied to the processor and for the internal phase locked loop cant bits (D23–D8) of the data bus. For a dual off-chip fetch,
(PLL) to lock onto the specific crystal frequency. A minimum of the data from program memory is read first, then the data from
2000tCKI cycles will ensure that the PLL has locked (this does not data memory. The program memory select pin, PMS, is acti-
include the crystal oscillator start-up time). vated during external program memory accesses and can be
used as a chip select signal for the external program memory
The operation of the internal power-on reset circuit is illustrated devices. Similarly, for external data memory accesses, the DMS
in Figure 14. On power-up, the circuit maintains the POR pin pin is activated.
low until it detects that the VDD line has attained the threshold

REV. B –19–
ADMC401
Two control lines indicate the direction of the transfer. Memory
read, RD, is active low, signaling a read from external memory ADMC401 20pF
and memory write; WR, is active low, signaling a write to exter- CLKOUT XTAL
nal memory. Typically, the PMS line is connected to the CE 13MHz 20pF
(chip enable) of the external program memory and the RD line MMAP
CLKIN
is connected to the CE line of the external data memory. The VDD
DATA
BMODE
RD line is connected to the OE (output enable) and the WR DR1A
CLK SERIAL ROM
line is connected to the WE (write enable) of both memories. SCLK1 OR
RESET E2PROM
RESET RFS1/ SROM
On-chip accesses (to internal program memory RAM and ROM)
do not drive any of the external signals. The PMS, RD and the
WR lines remain high (deasserted) and the address and data Figure 15. Basic System Configuration in Standalone
buses are three-stated during these internal accesses. Similarly, Mode
internal accesses to data memory (including internal DM RAM
and peripheral and DSP core memory mapped registers) do not If boot loading from an SROM or E2PROM is unsuccessful, the
drive external signals and the DMS, RD and the WR lines re- monitor code reconfigures SPORT1 as a UART (setting both
main high (deasserted) and the address and data buses are also Bit 4 and Bit 5 of the MODECTRL register) and attempts to
three-stated. receive commands from an external device on this serial port
using the DR1B pin. The monitor now waits for two bytes of
External peripherals can also be connected externally and memory information. These bytes are received asynchronously so that no
mapped to the external memory space of the ADMC401. The clock is needed. The first byte is the autobaud byte and it is
16 MSBs of the external data bus are connected internally to the used to calculate the baud rate at which data is being received.
16 bits of the internal data memory bus. Therefore, the data This is known as the autobaud feature. The ADMC401 will
lines D23–D8 should be used for 16-bit peripherals. automatically lock onto the baud rate of the external device if
it is sent a byte of 0x70. The maximum baud rate that the
BOOT LOADING ADMC401 will lock onto is 300 kb/s for a 26 MHz CLKOUT.
Standalone Mode (MMAP = BMODE = 1)
Boot loading of the ADMC401 may occur in a number of differ- The second byte of information received is the header byte that
ent ways and is determined by the state of both the MMAP and uniquely identifies to the monitor which type of interface it is
BMODE pins. If both MMAP and BMODE are tied to VDD connected to. There are six different interfaces supported on the
(HI), the ADMC401 is placed in the so-called standalone mode ADMC401. These includes:
and execution starts from internal program memory ROM at • A UART boot loader such as from a Motorola 68HC11
address 0x0800 following a power-on or reset. This starts execu- communicating over its Serial Communications Interface
tion of the internal monitor function that first performs some (SCI) port.
initialization functions (including writing 0 to the three data • A synchronous slave boot loader (the clock is external).
memory wait state fields) and copies a default interrupt vector • A synchronous master boot loader (the ADMC401 provides
table to addresses 0x0000–0x005F of program memory RAM. the clock).
The monitor program next clears Bit 4 of the MODECTRL
• A UART debugger interface such as the Motion Control
register to connect the DR1A pin to the internal data receive
Debugger from Analog Devices. The monitor then processes
port (DR1) of SPORT1. In addition, Bit 5 of the MODECTRL
commands received from the debugger over the UART
register is set. This connects the FL1 port of the DSP core to
interface.
the RFS1/SROM pin to act as a reset for a serial memory device.
• A synchronous master debugger interface.
The monitor next attempts to boot load from an external Serial
• A synchronous slave debugger interface.
ROM (SROM) or Serial E2PROM on SPORT1 using the three
wire connection of Figure 15. This SROM or E2PROM should be Detailed information on these software interfaces can be
programmed with the protocol of the MAKEPROM utility found in the “UART Boot Loader Protocol” and “UART
provided with the Motion Control Debugger. The monitor Debugger Protocol” appendices of the ADMC401 Developer’s
program first toggles the RFS1/SROM pin of the ADMC401 to Reference Manual.
reset the serial memory device with the following code segment: Byte-Wide EPROM Boot Mode (MMAP = BMODE = 0)
SROMRESET: SET FL1; If both the MMAP and BMODE pins are tied to GND, the
TOGGLE FL1; ADMC401 operates in the so-called EPROM Boot mode. In this
TOGGLE FL1; mode the entire internal program memory, or any portion of it,
RTS; can be loaded from an external source using a boot sequence
over the memory interface. To allow boot loading from inexpen-
If a properly programmed SROM or E2PROM is connected to sive 8-bit wide EPROM devices, the processor loads data one
SPORT1, data is clocked synchronously into the ADMC401 at byte at a time. The boot sequence can also be initiated after
a rate of 1 Mb/s. Both internal and external program and data reset by software.
memory RAM can be loaded from the SROM/E2PROM, up to
the available capacity of the serial memory device. After the Boot memory is organized into eight pages, each of which is 8k
entire boot load is complete, program execution begins at ad- bytes long. Every fourth byte of a page is an empty byte except
dress 0x0060. This is where the first instruction of the user code for the first one, which contains the page length. Each set of
should be placed. three bytes between successive empty bytes contains one 24-bit
instruction to be loaded into the internal PM RAM of the DSP.

–20– REV. B
 ADMC401
The page length is read first and then bytes are loaded from the BUS REQUEST/GRANT
top of the page downwards. This causes shorter booting times The ADMC401 can relinquish control of the external data and
for shorter pages. The length of the boot page is given as: address buses to an external device. The external device requests
page length = (number of 24-bit PM words/8) – 1 the bus by asserting (low) the bus request signal BR. BR is an
asynchronous input and if the ADMC401 is not performing an
That is, a page length of 0 causes the boot address generator to external access, it responds to the active BR input in the follow-
generate byte addresses for eight words that reside in 32 sequen- ing processor cycle by:
tial EPROM locations.
• Three-stating the data and address buses and the PMS,
A PROM splitter utility (SPL21), part of the Motion Control DMS, BMS, RD and WR output drivers.
Debugger tool set, calculates the proper page length for your • Asserting the bus grant (BG) signal, and
program and orders the bytes of your program according to the
• Halting program execution (unless Go Mode is enabled).
proper protocol. More detailed information about the use of
this PROM splitter utility can be found in the “Booting from If Go Mode is enabled, (using the ENA G-MODE instruction)
External EPROM with MMAP = BMODE = 0” chapter of the the ADMC401 continues to execute instructions from its inter-
ADMC401’s Developer’s Reference Manual. nal memory. It will not halt program execution until it encoun-
ters an instruction that requires an external access, which includes
Following a reset, if both MMAP and BMODE are LO, the
an access to any motor control peripheral register. If Go Mode
boot sequence always boot loads page 0. After reset, boot load-
is not enabled, the ADMC401 always halts before granting the
ing can occur under program control from any one of up to
bus. The processor’s internal state is not affected by granting
eight different boot pages. The boot page select field (BPAGE)
the bus, and the serial ports remain active during a bus grant,
in the memory mapped System Control Register specifies which
whether or not the processor core halts.
boot page is to be loaded. To boot from a specific boot page,
first set the BPAGE bits to the desired value and set the boot If the ADMC401 is performing an external access when the BR
force bit (BFORCE) of the System Control Register to initiate a signal is asserted, it will not grant the buses until the cycle after
boot sequence. the access completes. The entire instruction does not need to be
completed when the bus is granted. If a single instruction re-
The ADMC401 can boot its internal program memory from a
quires two external accesses, the bus will be granted between the
single byte-wide CMOS EPROM such as the 27C64 or the
two accesses. The second access is performed after BR is re-
27C512. A low cost commodity-grade EPROM with an indus-
moved. When the BR input is released, the ADMC401 releases
try-standard access time can be used. The number of wait states
the BG signal, re-enables the output drivers and continues pro-
for the boot memory access is selected in the BWAIT field of
gram execution from the point where it stopped. BG is always
the System Control Register. This field can be set to any value
deasserted in the same cycle that the removal of BR is recognized.
from 0 to 7 to set the number of wait states. The default value
for the BWAIT field is 7 so that seven wait states are inserted The bus request feature operates at all times, including when
into the reset-initiated boot loading sequence. the ADMC401 is booting and when RESET is active. During
RESET, BG is asserted in the same cycle that BR is recognized.
Timing of the boot memory access is identical to that of external
During booting, the bus is granted after the completion of load-
program memory or external data memory accesses, except that
ing of the current byte (including any wait states). Using the bus
the active strobe is BMS rather than PMS or DMS. To address
request during booting is one way to bring the booting operation
eight pages of 8K bytes each, 16 address lines are needed. The
under control of a host computer.
least significant 14 bits are output on the 14-bit address bus
(A13 to A0) while the most significant two bits are output on The ADMC401 has an additional output, Bus Grant Hang,
the 2 MSBs of the data bus (D23 and D22) during boot memory BGH, which lets it operate in a multiprocessor system with a
accesses. The data is read from the middle eight bits of the data minimum number of wasted cycles. The BGH pin asserts when
bus (D15 to D8). the ADMC401 is ready to execute an instruction but is stopped
because the external bus is granted to another device. The other
The development tools for the ADMC401 support the creation
device can release the bus by deasserting bus request. Once the
of EPROM target files capable of boot loading both internal and
bus is released, the ADMC401 deasserts BG and BGH and
external program and data memory.
executes the external access.
External Memory Mode (BMODE = 0, MMAP = 1)
In this mode, with BMODE tied to GND and MMAP tied to POWER-DOWN MODES
VDD, the ADMC401 is placed in external memory mode and The ADMC401 includes a power-down feature that allows the
there is no boot loading. The effect of this mode is that the device to enter a very low power dormant state through hard-
internal 2K bank of program memory RAM is relocated from ware or software control. In the power-down mode:
the bottom of memory (starting at address 0x0000) to the top of
• Internal clocks are disabled
the program memory space (at address 0x3800). In this mode,
program execution starts at external memory address 0x0000, at • Processor registers and memory contents are maintained
which point the first instruction must be placed. • Ability to recover from power-down in less than 100tCKI
cycles
The mode in which BMODE = 1 and MMAP = 0 is not allowed
on the ADMC401 and is an illegal state. The operation of the • Interrupt support for housekeeping code before entering
ADMC401 is neither guaranteed nor defined with BMODE = 1 power-down and after recovering from power-down
and MMAP = 0. • User-selectable power-up context

REV. B –21–
ADMC401
Entering Power-Down exiting power-down with RESET, the XTALDELAY control bit
The power-down sequence is initiated by applying a high-to-low is ignored.
transition on the PWD pin or by setting the power-down force Startup Time After Power-Down
control bit (PDFORCE) of the SPORT1 autobuffer/power- The time required to exit the power-down state depends on the
down control register. The DSP core then vectors to the non- method used to exit power-down. Unlike the standard ADSP-
maskable power-down interrupt vector at address 0x002C. Care 21xx products, the XTALDIS bit of the Power-Down Register
must be taken to ensure that multiple power-down interrupts do has no effect on the ADMC401 so that it is not possible to avoid
not occur or else stack overflow may result. The interrupt ser- the power drain caused by the XTAL pin toggling. When the
vice routine at address 0x002C can be used to execute any num- processor comes out of power-down by either the PWD or RESET
ber of housekeeping instructions prior to the processor entering pins, it will begin executing after a maximum startup time of
the power-down mode. Typically, this is used to configure the 100 CLKIN cycles as long as the clock oscillator is stable and at
power-down state, disable on-chip peripherals and clear pending the same frequency as before power-down.
interrupts. The DSP subsequently enters the power-down mode
when it executes the IDLE instruction (while PWD is asserted). If the external clock is unstable when the ADMC401 exits
The processor may take either one or two cycles to power down, power-down, the XTALDELAY control bit can be used to
depending on internal clock states during execution of the IDLE insert an additional 4096 cycle delay into the startup time. This
instruction. All register and memory contents are maintained in delay can only be inserted when the ADMC401 is brought out
power-down. Also, all active outputs are held in whatever state of power-down by the PWD pin.
they are in before going into power-down. If an RTI instruction If the processor is taken out of power-down by the RESET line,
is executed before the IDLE instruction, the processor returns and the clock is stable and at the same frequency as before
from the power-down interrupt and the power-down sequence is power-down, the RESET need only be held for five cycles.
aborted.
The PWDACK Pin
Exiting Power-Down The PWDACK pin is an output that indicates when the ADMC401
The power-down mode can be exited with the use of the PWD is in the power-down mode. This pin is driven high by the pro-
pin or with the RESET pin. There are also several user-select- cessor when it has powered down. It is driven low after the
able modes for startup from power-down which specify a start- processor has completed the power-up sequence. A low level on
up delay as well as specify the program flow after startup. This the PWDACK pin also indicates that there is a valid CLKOUT
allows the program to resume from where it left off before signal and that instruction execution has begun.
power-down, or for the program context to be cleared. Applying
When power-down is terminated with the RESET pin or a start-
a low-to-high transition on the PWD pin will take the processor
up delay is selected, a low level on the PWDACK pin only indi-
out of power-down. The amount of time it takes for the proces-
cates the start of oscillations on the CLKOUT pin. It will not
sor to come out of power-down is controllable with the delay
necessarily indicate the start of instruction execution.
startup from power-down control bit (XTALDELAY, Bit 14 of
the Power-Down Control Register or SPORT1 Autobuffer The state of PWDACK and also the CLKOUT signal is unde-
Control Register). If this bit is cleared, no additional delay over fined during the first 100 cycles of the initial reset.
the quick startup (100 cycles) is introduced. If this bit is set, a Using Power-Down as a Nonmaskable Interrupt
delay of 4096 cycles is introduced. The power-down interrupt is never masked. It is possible to use
The context for exiting power-down is set by Bit 12 (PUCR) of this interrupt for other purposes, if desired. The ADMC401 does
the Power-Down Control Register. If this bit is cleared, after not go into power-down until the IDLE instruction is executed.
exiting power-down the processor will continue to execute in- If an RTI is executed instead, before an IDLE instruction, the
structions following the IDLE instruction after the low-to-high processor returns from the power-down interrupt service outline
transition on the PWD pin. When the RTI instruction is en- and the power-down sequence is aborted.
countered in the interrupt service routine for the power-down,
operation is returned to the main routine. If the PUCR bit is THE ANALOG-TO-DIGITAL CONVERSION
set, for a “clear context”, the processor resumes operation from SYSTEM
power-down by clearing the PC, STATUS, LOOP and CNTR OVERVIEW OF ADC SYSTEM
registers. The IMASK and ASTAT registers are cleared and the The ADMC401 contains a fast, high accuracy, multiple-input
SSTAT goes to 0x55. The processor starts execution at address analog-to-digital conversion system with simultaneous sampling
0x0000. capabilities. This A/D conversion system permits the fast, accu-
Active output pins retain their states during power-down. In rate conversion of currents, voltages and other signals needed in
addition, interrupts are latched and can be serviced if the high performance motor control systems. A functional block
ADMC401 exits power-down with PUCR = 0. It is possible to diagram of the entire ADC system is shown in Figure 16.
clock data into or out of the serial ports during power-down The ADC system permits up to eight dedicated analog inputs all
by supplying an external serial clock. Data clocked into the to be converted in under 2 µs (at 26 MHz) through a single 12-
ADMC401 will remain in the RX registers. These activities bit pipeline flash ADC. The entire ADC system (including
cause additional power consumption. multiplexing and the sample and hold amplifiers) operates at a
If RESET is activated while the ADMC401 is in the power- clock rate equal to a quarter of the DSP instruction rate. Analog
down mode, power down is exited, and a normal Full System input voltages of up to 4.0 V p-p can be converted. The input
Reset Sequence is initiated, (which depends upon the settings of signals are divided into two banks of four signals each, with
MMAP and BMODE for the boot method as usual). When VIN0 to VIN3 making up one bank and VIN4 to VIN7 making
up the second bank. There are also two dedicated inputs (ASHAN
–22– REV. B
 ADMC401
and BSHAN) to the inverting terminal of the two sample and The conversion sequence may be initiated either internally (syn-
hold amplifiers (SHA) so that external signals can be correctly chronized to the PWM generation) or from an external event on
biased about the nominal operating range of the ADC. the CONVST pin. In the default Simultaneous Sampling mode of
operation, the internal control logic simultaneously samples the
first pair of input signals (VIN0 and VIN4) following the con-
ASHAN vert start command. Subsequently, these inputs are multiplexed
VIN0 SHA A ADC0(15...0) into the 12-bit analog-to-digital converter. After a delay of two
VIN1 ADC clock cycles, the second pair of analog inputs (VIN1 and
ADC1(15...0)
VIN2 MUX
VIN3
ADC2(15...0) VIN5) are sampled simultaneously and then multiplexed into
DATA ADC3(15...0) the ADC. This process continues until all four pairs of analog
ADC4(15...0)
GAIN
12-BIT inputs have been sampled and converted. As the conversion for
MUX PIPELINE ADC5(15...0)
FLASH ADC ADC6(15...0)
a given analog input channel is completed, the corresponding
OUT ADC7(15...0) digital number is written to a dedicated 16-bit, twos comple-
VIN4
VIN5
OF ADCXTRA(15...0) ment, left-aligned register that is memory mapped to the data
MUX RANGE
VIN6 END OF ADCOTR(7...0) memory space of the DSP core. The ADC data register ADC0
CONVERSION
VIN7 SHA B ADCSTAT(4...0) stores the conversion result for the signal on VIN0, etc.
CONTROL SIGNALS ADCCTRL(4...0)
BSHAN Following the end of conversion of each pair of analog inputs, a
dedicated bit is set in the ADCSTAT register. The result of this
PWMSYNC
CONVST MULTIPLEXER, SHA AND ADC CONTROL
highly efficient pipelined structure is that all eight ADC data
CLKOUT registers will contain valid conversion results less than 2 µs (at
26 MHz) after the convert start command. At this point a dedi-
PWMSYNC (FROM PWM PERIPHERAL)
cated ADC interrupt will be generated. Alternatively, if data is
CAPT
required sooner, the ADCSTAT register can be polled to detect
CAPB when a given pair of analog inputs have been successfully con-
VOLTAGE INTERNAL
VREF REFERENCE REFERENCE
verted, except in Sequential Sampling mode.
REFCOM GENERATION SIGNALS
& CONTROL Once the conversion sequence has been completed and all eight
SENSE
CML
ADC data registers have been updated, the entire ADC structure
automatically reverts to the Single Channel mode and continu-
ously converts the analog input on the VIN0 pin. The results of
Figure 16. Functional Block Diagram of the ADC System
this conversion are placed in the additional ADCXTRA register
of the ADMC401
and are updated once every ADC clock cycle. This feature could
The basic architecture of the ADC system consists of a four- be used to continuously monitor a single analog input on the
stage pipeline architecture (the A/D core) with wideband input VIN0 pin.
sample and hold amplifiers. Excluding the last stage, each stage There are two additional modes of operation of the ADC system
of the pipeline consists of a low resolution flash A/D connected that may be used for offset and gain calibration of the entire
to a switched capacitor DAC and interstage residue amplifier system. In the Offset Calibration mode, all analog inputs (VIN0
(MDAC). The reside amplifier amplifies the difference between to VIN7, GAIN, ASHAN and BSHAN) are disconnected from
the reconstructed DAC output and the flash input for the next the inputs to the sample and hold amplifiers. Instead, both
stage in the pipeline. The last stage of the pipeline simply con- terminals of each sample and hold amplifiers are connected
sists of a flash A/D. The pipeline architecture allows a greater together and to the voltage reference. Following a conversion
throughput rate at the expense of pipeline delay or latency. This sequence, the data in the ADC data register can be taken as a
means that while the converter is capable of capturing a new measure of any offset in the sample and hold amplifiers and
input sample every ADC clock cycle, it actually takes 3 1/2 ADC ADC. Additionally, in the Gain Calibration mode, the dedicated
clock cycles for the conversion process of any input to be fully analog input GAIN is applied to the noninverting terminal of
processed and appear at the output. both sample and hold amplifiers. Any number of precise exter-
The ADC may operate in two basic conversion modes, Simulta- nal voltages can be applied to this pin to measure and correct
neous Sampling or Sequential Sampling. The operating mode is for any gain errors, if required.
selected by dedicated bits in the ADCCTRL register. In the Along with each data output from the A/D converter, an Out-of-
Simultaneous Sampling mode, two analog inputs (one from each Range (OTR) bit is set if the signal exceeds the permissible
bank) are sampled simultaneously so that VIN0 and VIN4, input voltage span. In normal conversion, the eight OTR bits for
VIN1 and VIN5, VIN2 and VIN6, VIN3 and VIN7 represent the eight analog inputs are stored in the ADCOTR register, with
four pairs of simultaneously sampled inputs. In the alternative one bit for each analog input. The OTR bit for the ADCXTRA
sequential operating mode, there is no simultaneous sampling, register is stored in the ADCSTAT register.
and the analog inputs are sampled and converted one after the
other (i.e., VIN0 followed by VIN1 followed by VIN2, etc.). In The ADC may use either an internally generated 2.0 V precision
this mode, successive analog inputs are sampled an ADC clock reference voltage or an externally supplied reference voltage
period (or four DSP clock cycles) apart. level at the VREF pin. The operating mode is selected by the
connection of the SENSE pin.

REV. B –23–
ADMC401
CONVERT START COMMAND +VREF
The analog-to-digital conversion process of the ADMC401 may VIN0
VCORE 12
be started by either an internal or an external command. Bit 0 of 
A/D
CORE
the ADCCTRL register determines whether internal or external
convert start mode is enabled. If Bit 0 of the ADCCTRL regis- ASHAN
–VREF
ter is cleared, internal convert start mode is selected, and the
ADC conversion process is started on the rising edge of the Figure 17. Equivalent Functional Input Circuit of ADC
PWMSYNC signal. This results in one conversion sequence per System
PWM switching period (at the start of each period) when the
PWM generation unit operates in the single update mode. In the The dc voltage on the VREF pin sets the common-mode voltage
double update operating mode, there are two conversion se- of the A/D converter of the ADMC401. For example, when
quences per PWM switching period (one at the start and one in using the internal 2.0 V reference, the input level will also be
the middle of each period). In internal convert start mode, in centered about 2.0 V. The ADC inputs of the ADMC401 can
order to ensure correct synchronization and jitter-free operation, be configured for single ended operation, where the inverting
it is essential that the value written to the PWMTM register be a terminals (ASHAN and BSHAN) are connected directly to the
multiple of four. In other words, the two LSBs of the value reference voltage level, and the analog inputs (VIN0 to VIN7)
written to the PWMTM register must both be 0. are driven by analog signals with a 4.0 V p-p range. The VIN0
to VIN7 inputs are unipolar so that when operating from the
If Bit 0 of the ADCCTRL register is set, external convert start internal 2.0 V reference, these signals can range from 0 V to
mode is selected. In this mode, the conversion process is started 4 V. The recommended single-ended input configuration for a
on the occurrence of a rising edge on the CONVST pin. Addi- single analog input channel of the ADMC401 is shown in Fig-
tionally, the start of conversion can be placed under software ure 18. The input to the A/D converter must be driven by an
control by externally connecting one of the programmable input/ operational amplifier with sufficient drive strength so that the
output (PIO) lines to the CONVST pin and generating a rising A/D performance is not degraded. Sufficient drive strength is
edge by writing to the appropriate bit of the PIODATA register. the ability to drive a load of 6 pF static and 4 pF switched from
By default, following reset, Bit 0 of the ADCCTRL register is ground (capacitive) to settle within ± 1.0 mV within 70 ns. In
cleared so that internal convert start mode is selected. Figure 18, the operational amplifier is shown configured as a
simple noninverting input buffer. Of course, the operational
ADC CLOCK SIGNALS amplifier stage could also be used to implement any necessary
The ADC consists of a pipeline flash architecture and is clocked level shifting and/or filtering of the input signal.
at a quarter of the DSP instruction rate. All of the timing of the
+V
ADC system (including control of the multiplexers and sample 4V
0V
and hold amplifiers) is regulated by this clock signal and it de- RS
VIN0
termines the total conversion time for all of the channels as well
as the delay between sampling of successive pairs of analog
ADMC401
inputs. The ADC clock rate is internally fixed and may not be –V
RS
changed. The period of the ADC clock, tCKADC is related to the ASHAN
DSP CLKOUT period by:
VREF
10F 0.1F
tCKADC = 4 × tCK SENSE
A DSP rate of 26 MHz corresponds to a tCKADC of approxi-
mately 154 ns.
Figure 18. Typical Single-Ended Input Configuration for
ANALOG INPUT CONFIGURATION AND OVERVIEW ADMC401
Figure 17 is a simplified model of the ADC input structure for From Figure 17, it is clear that the input to the A/D core is
one channel (VIN0) of the ADC system of the ADMC401. This simply given by:
model applies to all eight input channels. The internal multi-
plexers are used to switch the various analog inputs to the A/D VCORE = VIN 0 – ASHAN
converter. For analog inputs VIN0 to VIN3, there is a single which must satisfy the condition:
common terminal (ASHAN) that is the inverting input to the
internal differential sample and hold amplifier. For the input –VREF ≤ VCORE ≤ VREF
signals, VIN4 to VIN7, the equivalent input is BSHAN. The
where VREF is the voltage at the VREF pin of the ADMC401
value VREF (internally generated voltage reference or externally
(either internally generated or externally supplied). There is an
applied voltage reference on the VREF pin) defines the maximum
additional limit placed on the valid operating range for the VIN0
input voltage to the A/D core. The minimum input voltage to
and ASHAN inputs that is bounded by the power supply of the
the A/D core is automatically defined as –VREF.
ADMC401:

AVSS – 0.3 V ≤ VIN 0 ≤ AVDD + 0.3 V

AVSS – 0.3 V ≤ ASHAN ≤ AVDD + 0.3 V

–24– REV. B
 ADMC401
Table II. Digital Data Format of ADC

VIN0 (V) ASHAN (V) VCORE (V) Digital Data (Hex) Digital Data (Binary) OTR
≥2 × VREF VREF ≥+VREF 0x7FF0 0111 1111 1111 0000 1
2 × VREF – 1 LSB VREF VREF – 1 LSB 0x7FF0 0111 1111 1111 0000 0
2 × VREF – 2 LSB VREF VREF – 2 LSB 0x7FE0 0111 1111 1110 0000 0
VREF + 1 LSB VREF 0 + 1 LSB 0x0010 0000 0000 0001 0000 0
VREF VREF 0 0x0000 0000 0000 0000 0000 0
VREF – 1 LSB VREF 0 – 1 LSB 0xFFF0 1111 1111 1111 0000 0
0 + 1 LSB VREF –VREF + 1 LSB 0x8010 1000 0000 0001 0000 0
0 VREF –VREF 0x8000 1000 0000 0000 0000 0
<0 VREF <–VREF 0x8000 1000 0000 0000 0000 1

where AVSS is nominally at 0 V and AVDD is nominally at +5 V. Of Simultaneous Sampling Mode

course, identical input constraints and requirements apply for This operating mode is selected by clearing both Bits 3 and 4 of
the other analog inputs VIN1 to VIN7 as well as the BSHAN the ADCCTRL register. In this mode, the eight analog inputs
and GAIN inputs. are sampled as four pairs of simultaneously sampled inputs with
VIN0 and VIN4 being the first pair of sampled inputs, followed
ADC DATA FORMAT AND OUT-OF-RANGE DETECTION by VIN1 and VIN5, followed by VIN2 and VIN6, followed by
The digital data from the A/D core that is stored in the dedi- VIN3 and VIN7. Following the rising edge of the convert start
cated, memory mapped ADC registers (ADC0 to ADC7 as well command (either internally or externally derived), the internal
as ADCXTRA) is stored as left-aligned, twos complement data. control logic simultaneously samples the VIN0 and VIN4 analog
The output data format for normal operation in the single- inputs using the dual internal sample and hold amplifiers. The
ended configuration of Figure 18 is given in Table II for one internal control logic subsequently multiplexes these two signals
analog input (VIN0 and ASHAN). Naturally, identical condi- into the A/D core of the ADMC401. The conversion of each
tions apply for all other analog inputs. signal requires 3 1/2 ADC clock cycles. Following the hold
As well as the 12-bit data word, the A/D core produces an out- operation, the VIN0 input is applied to the first stage of the
of-range bit that is set when the analog input to the core exceeds pipeline during the next ADC clock cycle. For the next clock
the allowable range (–VREF to +VREF). There is a dedicated 8-bit cycle, the VIN0 signal is applied to the second stage of the
ADCOTR register that stores the eight OTR bits for the A/D pipeline and the VIN4 input is applied to the first stage of this
conversions of the signals on the VIN0 to VIN7 inputs. There is pipeline. In this clock cycle, the second pair of inputs is also
a single bit for each analog input; if Bit 0 of the ADCOTR register simultaneously sampled. This process continues to feed signals
is set, the VIN0 input has exceeded the permissible input range. into the A/D core until all eight channels have been converted.
Therefore, following a complete conversion cycle, if this register The timing of this conversion sequence is shown in Figure 19.
is zero, no signal has exceeded the input range. If the OTR bit tCKADC
for a given analog input is set, it is possible to determine if the
signal has overranged (less than 2 × VREF) or underranged (less ADC
CLOCK
than 0 V) by monitoring the MSB of the data word and the
OTR bit, as outlined in Table III. CONVERT
START
Table III. Out-of-Range Truth Table
S&H VIN0 & VIN4
OTR MSB Condition CONVERT VIN0

0 0 In Range: VREF ≤ VIN0 ≤ 2 × VREF –1 LSB CONVERT VIN4

0 1 In Range: 0 ≤ VIN0 ≤ VREF – 1 LSB S&H VIN1 & VIN5

CONVERT VIN1

1 0 Overrange: VIN0 ≥ 2 × VREF CONVERT VIN5

1 1 Underrange: VIN0 < 0 S&H VIN2 & VIN6

CONVERT VIN2
CONVERT VIN6
ADC OPERATING MODES S&H VIN3 & VIN7
CONVERT VIN3
The A/D conversion system of the ADMC401 may be config- CONVERT VIN7
ured to operate in four basic modes that are selected by Bits 3
Figure 19. ADC Timing for Simultaneous Sampling Oper-
and 4 of the ADCCTRL register. Following reset, the default
ating Mode
setting is that both of these bits are cleared and Simultaneous
Sampling mode is selected. In this operating mode, there is a unique status bit in the
ADCSTAT register that is set as soon as data is available for
• Simultaneous Sampling Mode (ADCCTRL(4 . . . 3) = 00)
each pair of simultaneously sampled signals. Bit 0 of the
• Sequential Sampling Mode (ADCCTRL(4 . . . 3) = 01) ADCSTAT is set as soon as the data in both the ADC0 and
• Offset Calibration Mode (ADCCTRL(4 . . . 3) = 10) ADC4 registers is valid, Bit 1 is set as soon as the data in ADC1
and ADC5 is valid, Bit 2 is set as soon as the data in ADC2 and
• Gain Calibration Mode (ADCCTRL(4 . . . 3) = 11)

REV. B –25–
ADMC401
ADC6 is valid and Bit 3 is set when the data in ADC3 and entire input voltage span of the A/D system. The Gain Calibra-
ADC7 is valid. At the start of the next conversion sequence, all tion mode, selected by setting both Bits 3 and 4 of the ADCCTRL
bits of the ADCSTAT register are cleared. Additionally, at the register, is designed to offer significant user flexibility in deter-
end of the complete conversion sequence (when the data in the mining the amount of gain compensation that may be required.
ADC7 register is valid), a dedicated ADC interrupt is generated. In this mode the dedicated GAIN input pin is internally con-
This interrupt can be masked and controlled by the PIC block. nected directly to the noninverting input of each sample and
Depending on initial synchronization delays, the worst case total hold amplifier. The user may apply different precise analog
conversion time (defined as the duration from the rising edge of voltages across the input voltage span to this pin to measure
the convert start command to the generation of the ADC inter- gain errors over the operating range.
rupt) for all eight channels is: A complete conversion sequence for each different GAIN input
must be initiated. Following the end of conversion, the data in
tCONV = 49 × tCK
the ADC0 to ADC3 registers may be used to calculate four
which corresponds to 1.88 µs for a DSP instruction rate of separate measurements of the gain error of the first sample and
26 MHz. Additionally, in this operating mode, the time delay hold amplifier. Similarly, the data in the ADC4 to ADC7 regis-
between sampling of successive pairs of analog inputs is 8tCK or ters may be used to calculate the gain associated with the second
308 ns (at 26 MHz). sample and hold amplifier. These data values could be averaged
to obtain gain error values for each sample and hold amplifier
Sequential Sampling Mode
that could be stored and used to compensate all future measure-
This operating mode is selected by setting Bit 3 and clearing
ments. The end of conversion status bits are updated and the
Bit 4 of the ADCCTRL register. In this operating mode, simul-
interrupt is generated in a manner identical to the Simulta-
taneous sampling is abandoned and the A/D conversion se-
neous Sampling mode.
quence samples each analog input sequentially. Therefore, in
the first ADC clock period, VIN0 is sampled and held by the
ADCXTRA REGISTER
first sample and hold amplifier. In the second clock period, the
Following the end of conversion sequence in any of the four
held sample of VIN0 is applied to the first stage of the ADC
operating modes, the A/D system reverts to its Single Channel
pipeline and the VIN1 signal is sampled. This process continues
mode. In this configuration, the multiplexers are set such that
until each of the analog inputs has been sequentially sampled
the VIN0 input is continuously sampled and converted. The results
and converted (i.e., VIN0 followed by VIN1 followed by VIN2,
of these conversions are placed in the dedicated ADCXTRA
etc.). In this operating mode, the total conversion time is the
register that is updated with the results of a new conversion
same as the Simultaneous Sampling mode. However, successive
every ADC clock period (or 154 ns at 26 MHz). This feature
channels are sampled at 4tCK (or 154 ns at 26 MHz) intervals.
permits the continuous tracking of a single analog input, if re-
In this mode, Bits 0 to 3 of the ADCSTAT register are all set
quired. The OTR bit for these conversions is placed in Bit 4 of
together when all eight conversions are complete. The interrupt
the ADCSTAT register. No interrupt is generated following
is generated, as before, when the data in the ADC7 register is valid.
these conversions and no other status bits are generated. The
Offset Calibration Mode ADCXTRA register is not updated during the conversion se-
In order to maintain the high accuracy of the ADC system of quence of any of the four operating modes.
the ADMC401, it may be necessary to measure and compensate
for any intrinsic offset and/or gain errors in the A/D conversion VOLTAGE REFERENCE OPERATION
system. The Offset Calibration mode, which is selected by setting The ADMC401 contains an onboard bandgap reference that
Bit 4 and clearing Bit 3 of the ADCCTRL register, is intended can be used to provide a precise 2.0 V output for use by the A/D
to be used for measuring any offsets in the sample and hold system and externally on the VREF pin for biasing and level–
amplifiers. When this mode is selected, all analog inputs (VIN0 shifting functions. Additionally, the ADMC401 may be config-
to VIN7, ASHAN and BSHAN) are disconnected from the ured to operate with an external reference applied to the VREF
inputs to the sample and hold amplifiers, and the SHA inputs pin. The SENSE pin is used to select between internal and
are internally connected together and to the reference voltage external references.
(at the VREF pin). Since these connections are in effect only
The actual reference voltages used by the internal ADC circuitry
during the conversion sequence, a complete conversion se-
of the ADMC401 appear on the CAPT and CAPB pins. For
quence must be initiated. Following the end of conversion,
correct operation of the internal voltage reference generation
the data in the ADC0 to ADC3 registers may be taken as four
circuitry, either with internal or external reference, it is neces-
separate measurements of the offset of the first sample and hold
sary to add a capacitor network between these pins, as shown in
amplifier. Similarly, the data in the ADC4 to ADC7 registers
Figure 20. A 10 µF tantalum capacitor in parallel with a 0.1 µF
may be taken as measurements of the offset associated with the
ceramic is recommended as well as two 0.1 µF capacitors to
second sample and hold amplifier. These data values could be
analog ground. The internal bias circuitry may take up to 15 ms
averaged to obtain an offset value for each sample and hold
after power-up to settle. Any ADC conversions performed prior
amplifier that could be stored and used to compensate all future
to this may not be as accurate as possible. The start-up time
measurements. The end of conversion status bits are updated
may be evaluated by measuring how long it takes for the voltage
and the interrupt is generated in a manner identical to the Si-
difference between CAPT and CAPB to settle to VREF. Addi-
multaneous Sampling mode.
tionally, a 0.1 µF ceramic capacitor must be connected between
Gain Calibration Mode the CML pin and analog ground. Finally, the VREF pin should
It may be desirable to measure and compensate for any gain be decoupled to analog ground by a 10 µF tantalum capacitor in
errors associated with the A/D conversion process across the parallel with a 0.1 µF ceramic capacitor.

–26– REV. B
 ADMC401
The SENSE pin controls whether the A/D system operates with THE PWM CONTROLLER
an internal or an external reference. For operation with the internal OVERVIEW
reference, the SENSE pin should be tied to the REFCOM pin. The PWM generator block of the ADMC401 is a flexible, pro-
In this mode, the internally derived 2 V voltage reference ap- grammable, three-phase PWM waveform generator that can be
pears at the VREF pin. To operate with an external voltage refer- programmed to generate the required switching patterns to drive
ence, the SENSE pin should be tied to the AVDD pin and the a three-phase voltage source inverter for ac induction (ACIM)
external voltage reference may be applied at the VREF pin. or permanent magnet synchronous (PMSM) motor control. In
addition, the PWM block contains special functions that consid-
0.1F erably simplify the generation of the required PWM switching
CAPT patterns for control of the electronically commutated motor
10F 0.1F
(ECM) or brushless dc motor (BDCM). A special mode for
CAPB
0.1F switched reluctance motors (SRM) exists as well, enabled by a
ADMC401 dedicated pin.
VREF
10F 0.1F
The PWM generator produces three pairs of PWM signals on
REFCOM the six PWM output pins (AH, AL, BH, BL, CH and CL). The
six PWM output signals consist of three high side drive signals
CML
0.1F (AH, BH and CH) and three low side drive signals (AL, BL and
SENSE CL). The polarity of the generated PWM signals may be pro-
grammed by the PWMPOL pin, so that either active HI or
Figure 20. Recommended Capacitor Decoupling Networks active LO PWM patterns can be produced by the ADMC401.
for the ADMC401 The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using respec-
OPTIMIZING ADC PERFORMANCE tively, the PWMTM, PWMDT and PWMPD registers. In addi-
The optimum noise and dc linearity performance is achieved tion, three duty-cycle control registers (PWMCHA, PWMCHB
with the largest input signal voltage span (i.e., 4 V input span) and PWMCHC) directly control the duty cycles of the three
and with matching impedance in series with each of the analog pairs of PWM signals.
inputs (VIN0 to VIN7, ASHAN and BSHAN). Additionally,
Each of the six PWM output signals can be enabled or disabled
the operational amplifier must exhibit source impedance that is
by separate output enable bits of the PWMSEG register. In
both low and resistive, up to and beyond the sampling frequency.
addition, three control bits of the PWMSEG register permit
When a capacitive load is switched onto the output of the opera-
crossover of the two signals of a PWM pair for easy control of
tional amplifier, the output will momentarily drop, due to its
ECM or BDCM. In crossover mode, the PWM signal destined
effective output impedance. As the output recovers, ringing may
for the high side switch is diverted to the complementary low-
occur. To remedy this situation, a series resistor can be inserted
side output and the signal destined for the low side switch is
between the op amp output and the ADC input (RS as shown in
diverted to the corresponding high side output signal. In addi-
Figure 18). Recommended configurations include using the
tion to ease of use of the PWM controller for ECM or BDCM,
OP27 amplifiers with an RS of 20 Ω. Alternative recommended
this crossover mode can also be used to transition the PWM
op amps are the AD8051 and AD8054.
signals into the overmodulation range with relative ease.
Figure 18 shows ASHAN driven by the internally generated
In many applications, there is a need to provide an isolation
reference voltage at VREF. When driving ASHAN with an inter-
barrier in the gate-drive circuits that turn on the power devices
nally generated VREF, better performance will result if the driv-
of the inverter. In general, there are two common isolation tech-
ing impedance of ASHAN matches the driving impedance of the
niques, optical isolation using opto-isolators and transformer
other analog inputs. This can be implemented with the addition
isolation using pulse transformers. The PWM controller of the
of a second amplifier to Figure 18, between VREF and ASHAN,
ADMC401 permits mixing of the output PWM signals with a
to match the amplifier on VIN0.
high-frequency chopping signal to permit easy interface to such
For noise sensitive applications, it may also be beneficial to add pulse transformers. The features of this gate-drive chopping
some shunt capacitance between the inputs (VIN0 and ASHAN mode can be controlled by the PWMGATE register. There is an
of Figure 18) and analog ground. Since this additional capaci- 8-bit value within the PWMGATE register that directly controls
tance combines with the equivalent input capacitance of the the chopping frequency. In addition, high frequency chopping
analog inputs, a lower series resistance may be possible. The can be independently enabled for the high side and the low side
input RC combination also provides some antialiasing filtering outputs using separate control bits in the PWMGATE register.
on the analog inputs. To optimize performance when noise is Also, all PWM outputs have sufficient sink and source capability
the primary consideration, increase the shunt capacitance as to directly drive most opto-isolators.
much as the transient response of the input signal will allow.
The PWM generator is capable of operating in two distinct
Increasing the capacitance too much may adversely affect the
modes, single update mode or double update mode. In single
op amp’s settling time, frequency response and distortion
update mode the duty cycle values are programmable only once
performance.
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
ADC REGISTERS
update mode, a second updating of the PWM registers is imple-
The configuration and structure of the ADC registers is de-
mented at the midpoint of the PWM period. In this mode, it is
scribed at the end of this data sheet.
possible to produce asymmetrical PWM patterns that produce

REV. B –27–
ADMC401
lower harmonic distortion in three-phase PWM inverters. This occurrence of a rising edge of the PWMSYNC pulse and the
technique also permits closed loop controllers to change the other is generated on the occurrence of any PWM shutdown
average voltage applied to the machine windings at a faster rate action.
and so permits faster closed loop bandwidths to be achieved. PWM PWM
The operating mode of the PWM block (single or double update CONFIGURATION DUTY CYCLE
REGISTERS REGISTERS
mode) is selected by a control bit in MODECTRL register.
PWMTM (15…0)
PWMCHA (15…0)
PWMDT (9…0)
The PWM generator of the ADMC401 also provides an output PWMPD(9…0) PWMCHB (15…0) PWMSEG PWMGATE
PWMCHC (15…0)
pulse on the PWMSYNC pin, which is synchronized to the PWM PWMSYNCWT(7…0) (8…0) (9…0)
MODECTRL (6)
switching frequency. In single update mode a PWMSYNC pulse
is produced at the start of each PWM period. In double update
AH
mode, an additional PWMSYNC pulse is produced at the mid- AL
point of each PWM period. The width of the PWMSYNC pulse is THREE-PHASE OUTPUT GATE
BH
PWM TIMING CONTROL DRIVE
programmable through the PWMSYNCWT register. UNIT UNIT UNIT BL
CH
The PWM signals produced by the ADMC401 can be shut off CLK SYNC SR RESET SYNC CLK POL CL
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin, PWMTRIP, that, when brought PWMSR
CLKOUT
LO, instantaneously places all six PWM outputs in the OFF PWMSYNC
PWMSYNC
state (as determined by the state of the PWMPOL pin). In
TO INTERRUPT PWMPOL
addition, each of the PIO lines of the ADMC401 (PIO0 to CONTROLLER
PIO11) can be configured to act as an additional PWM shut- PWMTRIP
PWMTRIP
down. By setting the appropriate bit in the PIOPWM register, OR PIO PIO0
PWM
the corresponding PIO line acts as an asynchronous PWM shut- DETECT PIO11
down source in a manner identical to the PWMTRIP pin. These
two hardware shutdown mechanisms are asynchronous so that PWMSWT PIOPWM
(11…0)
(0)
the associated PWM disable circuitry does not go through any
clocked logic, thereby ensuring correct PWM shutdown even in PWM SHUTDOWN CONTROLLER
the event of a loss of the DSP clock. In addition to the hardware
shutdown features, the PWM system may be shut down in soft- Figure 21. Overview of the ADMC401 PWM Controller
ware by writing to the PWMSWT register.
THREE-PHASE TIMING UNIT
Status information about the PWM system of the ADMC401 is The 16-bit three-phase timing unit is the core of the PWM
available to the user in the SYSSTAT register. In particular, the controller and produces three pairs of pulsewidth modulated
state of the PWMTRIP and PWMPOL pins is available, as well signals with high resolution and minimal processor overhead.
as status bits that indicates whether operation is in the first half The outputs of this timing unit are active LO such that a low
or the second half of the PWM period. level is interpreted as a command to turn ON the associated
A functional block diagram of the PWM controller is shown in power device. There are four main configuration registers
Figure 21. The generation of the six output PWM signals on (PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
pins AH to CL is controlled by four important blocks: determine the fundamental characteristics of the PWM outputs.
• The Three-Phase PWM Timing Unit, which is the core of In addition, the operating mode of the PWM (single or double
the PWM controller, generates three pairs of complemented update mode) is selected by Bit 6 of the MODECTRL register.
and dead time adjusted center based PWM signals. These registers, in conjunction with the three 16-bit duty cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
• The Output Control Unit allows the redirection of the out- output of the three-phase timing unit.
puts of the Three-Phase Timing Unit for each channel to
either the high side or the low side output. In addition, the PWM Switching Frequency, PWMTM Register
Output Control Unit allows individual enabling/disabling of The PWM switching frequency is controlled by the 16-bit PWM
each of the six PWM output signals. period register, PWMTM. The fundamental timing unit of the
PWM controller is tCK (DSP instruction rate). Therefore, for a
• The Gate Drive Unit provides the correct polarity output 26 MHz CLKOUT, the fundamental time increment is 38.5 ns.
PWM signals based on the state of the PWMPOL pin. The The value written to the PWMTM register is effectively the
Gate Drive Unit also permits the generation of the high- number of tCK clock increments in half a PWM period. The
frequency chopping frequency and its subsequent mixing required PWMTM value as a function of the desired PWM
with the PWM signals. switching frequency (fPWM) is given by:
• The PWM Shutdown Controller takes care of the various
PWM shutdown modes (via the PWMTRIP pin, the PIO fCLKOUT fCLKIN
PWMTM = =
lines or the PWMSWT register) and generates the correct 2 × f PWM f PWM
RESET signal for the Timing Unit.
Therefore, the PWM switching period, Ts, can be written as:
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, tCK and is capable of generating two TS = 2 × PWMTM × tCK
interrupts to the DSP core. One interrupt is generated on the

–28– REV. B
 ADMC401
For example, for a 26 MHz CLKOUT and a desired PWM duty cycles of the PWM signals can be updated only once per
switching frequency of 10 kHz (TS = 100 µs), the correct value PWM period at the start of each cycle. The result is that PWM
to load into the PWMTM register is: patterns that are symmetrical about the midpoint of the switch-
ing period are produced.
26 × 106
PWMTM = = 1300 In double update mode, an additional PWMSYNC pulse is
2 × 10 × 103 produced at the midpoint of each PWM period. The rising edge
The largest value that can be written to the 16-bit PWMTM of this new PWMSYNC pulse is again used to latch new values
register is 0xFFFF = 65,535, which corresponds to a minimum of the PWM configuration registers, duty cycle registers and the
PWM switching frequency of: PWMSEG register. As a result it is possible to alter the charac-
teristics (switching frequency, dead time, minimum pulsewidth
26 × 106 and PWMSYNC pulsewidth) as well as the output duty cycles
f PWM, MIN = = 198 Hz at the midpoint of each PWM cycle. Consequently, it is possible
2 × 65,535
with double update mode to produce PWM switching patterns
PWM Switching Dead Time, PWMDT Register that are not symmetrical about the midpoint of the period (asym-
The second important parameter that must be set up in the metrical PWM patterns).
initial configuration of the PWM block is the switching dead
In the double update mode, it may be necessary to know whether
time. This is a short delay time introduced between turning off
operation at any point in time is in either the first half or the
one PWM signal (say AH) and turning on the complementary
second half of the PWM cycle. This information is provided by
signal, AL. This short time delay is introduced to permit the
Bit 3 of the SYSSTAT register, which is cleared during opera-
power switch being turned off (AH in this case) to completely
tion in the first half of each PWM period (between the rising
recover its blocking capability before the complementary switch
edge of the original PWMSYNC pulse and the rising edge of the
is turned on. This time delay prevents a potentially destructive
new PWMSYNC pulse introduced in double update mode). Bit
short-circuit condition from developing across the dc link capacitor
3 of the SYSSTAT register is set during operation in the second
of a typical voltage source inverter.
half of each PWM period. This status bit allows the user to make a
The dead time is controlled by the 10-bit PWMDT register. determination of the particular half-cycle during implementation
There is one dead time register that controls the dead time of the PWMSYNC interrupt service routine, if required.
inserted into the three pairs of PWM output signals. The dead The advantage of the double update mode is that lower harmonic
time, TD, is related to the value in the PWMDT register by: voltages can be produced by the PWM process and faster
TD = PWMDT × 2 × tCK control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
Therefore, for a 26 MHz CLKOUT, a PWMDT value of rate in the double update mode. Since new duty cycle values
0x00A (= 10) introduces a 770 ns delay between the turn-off must be computed in each PWMSYNC interrupt service routine,
on any PWM signal (say AH) and the turn-on of its complemen- there is a larger computational burden on the DSP in the double
tary signal (AL). The amount of the dead time can therefore be update mode. Alternatively, the same PWM update rate may be
programmed in increments of 2tCK (or 77 ns for a 26 MHz maintained at half the switching frequency to give lower switch-
CLKOUT). The PWMDT register is a 10-bit register so that its ing losses.
maximum value is 0x3FF (= 1023) corresponding to a maximum
programmed dead time of: Width of the PWMSYNC Pulse, PWMSYNCWT Register
The PWM controller of the ADMC401 produces an output
TD, MAX = 1023 × 2 × tCK = 1023 × 2 × 38.5 × 10–9 = 78.8 µs PWM synchronization pulse at a rate equal to the PWM switch-
ing frequency in single update mode and at twice the PWM
for a CLKOUT rate of 26 MHz. Obviously, the dead time can frequency in the double update mode. This pulse is available
be programmed to be zero by writing 0 to the PWMDT register. for external use at the PWMSYNC pin. The width of this
PWM Operating Mode, MODECTRL and SYSSTAT Registers PWMSYNC pulse is programmable by the 8-bit read/write
The PWM controller of the ADMC401 can operate in two PWMSYNCWT register. The width of the PWMSYNC pulse,
distinct modes; single update mode and double update mode. TPWMSYNC, is given by:

( )
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is TPWMSYNC = tCK × PWMSYNCWT + 1
cleared, the PWM operates in the single update mode. Setting so that the width of the pulse is programmable from tCK to 256 ×
Bit 6 places the PWM in the double update mode. By default, tCK (corresponding to 38.5 ns to 9.85 µs for a CLKOUT rate of
following reset, Bit 6 of the MODECTRL register is cleared so 26 MHz). Following a reset, the PWMSYNCWT register con-
that the default operating mode is in single update mode. tains 0x27 (= 39) so that the default PWMSYNC width is
In single update mode, a single PWMSYNC pulse is produced 1.54 µs, again for a 26 MHz CLKOUT.
in each PWM period. The rising edge of this signal marks the PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC
start of a new PWM cycle and is used to latch new values from Registers
the PWM configuration registers (PWMTM, PWMDT, PWMPD The duty cycles of the six PWM output signals on Pins AH to
and PWMSYNCWT) and the PWM duty cycle registers CL are controlled by the three 16-bit read/write duty cycle
(PWMCHA, PWMCHB and PWMCHC) into the three-phase registers, PWMCHA, PWMCHB and PWMCHC. The integer
timing unit. In addition, the PWMSEG register is also latched value in the register PWMCHA controls the duty cycle of the
into the output control unit on the rising edge of the PWMSYNC signals on AH and AL, in PWMCHB controls the duty cycle of
pulse. In effect, this means that the characteristics and resultant the signals on BH and BL and in PWMCHC controls the duty

REV. B –29–
ADMC401
cycle of the signals on CH and CL. The duty cycle registers are Obviously negative values of TAH and TAL are not permitted and
programmed in integer counts of the fundamental time unit, the minimum permissible value is zero, corresponding to a 0%
tCK, and define the desired on-time of the high side PWM signal duty cycle. In a similar fashion, the maximum value is TS, corre-
produced by the three-phase timing unit over half the PWM pe- sponding to a 100% duty cycle.
riod. The switching signals produced by the three-phase timing The output signals from the timing unit for operation in double
unit are also adjusted to incorporate the programmed dead time update mode are shown in Figure 23. This illustrates a com-
value in the PWMDT register. The three-phase timing unit pletely general case where the switching frequency, dead time
produces active LO signals so that a LO level corresponds to a and duty cycle are all changed in the second half of the PWM
command to turn on the associated power device. period. Of course, the same value for any or all of these quanti-
A typical pair of PWM outputs (in this case for AH and AL) ties could be used in both halves of the PWM cycle. However, it
from the timing unit are shown in Figure 22 for operation in can be seen that there is no guarantee that symmetrical PWM
single update mode. All illustrated time values indicate the signals will be produced by the timing unit in this double update
integer value in the associated register and can be converted to mode. Additionally, it is seen that the dead time is inserted into
time by simply multiplying by the fundamental time increment, the PWM signals in the same way as in the single update mode.
tCK. First, it is noted that the switching patterns are symmetrical
about the midpoint of the switching period in this single up- PWMCHA1 PWMCHA2
date mode since the same values of PWMCHA, PWMTM and
PWMDT are used to define the signals in both half cycles of the
period. It can be seen how the programmed duty cycles are AH

adjusted to incorporate the desired dead time into the resultant 2
PWMDT1 2
PWMDT2
pair of PWM signals. Clearly, the dead time is incorporated by AL
moving the switching instants of both PWM signals (AH and
AL) away from the instant set by the PWMCHA register. Both PWMSYNC PWMSYNCWT1 + 1 PWMSYNCWT2 + 1
switching edges are moved by an equal amount (PWMDT ×
tCK) to preserve the symmetrical output patterns. Also shown is SYSSTAT (3)
the PWMSYNC pulse whose width is set by the PWMSYNCWT
register and Bit 3 of the SYSSTAT register, which indicates PWMTM1 PWMTM2
whether operation is in the first or second half cycle of the PWM
period. Figure 23. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode (Active LO Waveforms)
PWMCHA PWMCHA
In general the on-times of the PWM signals over the full PWM
period in double update mode can be defined as:
AH

2
PWMDT 2
PWMDT (
TAH = PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2 × tCK )
AL (
TAL = PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 – PWMDT1 – PWMDT2 × tCK )
where the subscript 1 refers to the value of that register during
PWMSYNC PWMSYNCWT + 1
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
SYSSTAT (3)
TAH PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2
d AH = =
TS PWMTM1 + PWMTM2
PWMTM PWMTM
TAL PWMTM1 + PWMTM2 – PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2
d AL = =
TS PWMTM1 + PWMTM2
Figure 22. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode (Active LO Waveforms) since for the completely general case in double update mode,
the switching period is given by:
The resultant on-times of the PWM signals over the full PWM
period (two half periods) produced by the PWM timing unit, (
TS = PWMTM1 + PWMTM2 × tCK)
and illustrated in Figure 22, may be written as:
Again, the values of TAH and TAL are constrained to lie between
(
TAH = 2 × PWMCHA – PWMDT × tCK ) zero and TS. Similar PWM signals to those illustrated in Figure
22 and Figure 23 can be produced on the BH, BL, CH and CL
(
TAL = 2 × PWMTM – PWMCHA – PWMDT × tCK ) outputs by programming the PWMCHB and PWMCHC registers
in a manner identical to that described for PWMCHA.
and the corresponding duty cycles are: Special Consideration for PWM Operation in
Overmodulation
TAH PWMCHA – PWMDT The PWM Timing Unit is capable of producing PWM signals
d AH = =
TS PWMTM with variable duty cycle values at the PWM output pins. At the
extremities of the modulation process, both 0% and 100%
TAL PWMTM – PWMCHA – PWMDT modulation are possible. These two modes are termed full OFF
d AL = =
TS PWMTM and full ON respectively. In between, for other duty cycle val-
ues, the operation is termed normal modulation.

–30– REV. B
 ADMC401
• Full ON: The PWM for any pair of PWM signals is said to Minimum Pulsewidth, PWMPD Register
operate in FULL ON when the desired HI side output of the In many power converter switching applications, it is desirable
three-phase Timing Unit is in the ON state (LO) between to eliminate PWM switching signals below a certain width. It
successive PWMSYNC pulses. This state may be entered by takes a certain finite time to both turn on and turn off power
virtue of the commanded duty cycle values (in conjunction semiconductor devices. Therefore, if the width of any of the
with the PWMDT register) or by virtue of the correct opera- PWM signals goes below some minimum value, it may be desir-
tion of the pulse deletion circuit. able to completely eliminate the PWM switching for that par-
• Full OFF: The PWM for any pair of PWM signals is said to ticular cycle. The allowable minimum pulsewidth for any of the
operate in FULL OFF when the desired HI side output of six PWM outputs that can be produced by the PWM controller
the three-phase Timing Unit is in the OFF state (HI) be- may be programmed using the 10-bit PWMPD register. The
tween successive PWMSYNC pulses. This state may be minimum pulsewidth, TMIN, is programmed in increments of
entered by virtue of the commanded duty cycle values (in tCK as:
conjunction with the PWMDT register) or by virtue of the TMIN = PWMPD × tCK
correct operation of the pulse deletion circuit. so that a PWMPD value of 0x00A defines a permissible mini-
• Normal Modulation: The PWM for any pair of PWM mum on time of 0.39 µs for a 26 MHz CLKOUT. The opera-
signals is said to operate in normal modulation when the tion of the minimum pulsewidth control ensures that the time
desired output duty cycle is other than 0% or 100% between from turning ON to turning OFF (or alternatively from turning
successive PWMSYNC pulses. OFF to turning ON) any PWM signal is never less than the
There are certain situations when transitioning either into or out TMIN value as specified by the PWMPD register. If the PWM
of either full ON or full OFF where it is necessary to insert controller detects that the time between turning ON and turning
additional dead time delays to prevent potential shoot through OFF any one PWM signal (say AH) is less than TMIN, the PWM
conditions in the inverter. The particular situation also depends pulse is deleted and the PWM signal remains completely OFF
on whether operation is in single or double update mode. In over the PWM period. The complementary signal, AL in this
double update mode, it is also necessary to consider whether the case, is then turned completely ON.
PWM unit is transitioning from the first half cycle to the second Effective PWM Resolution
half cycle or vice versa. These transitions are detected automati- In single update mode, the same values of PWMCHA, PWMCHB
cally by the ADMC401 and, if appropriate, the dead time is and PWMCHC are used to define the on-times in both half
inserted. cycles of the PWM period. As a result, the effective resolution of
The insertion of the additional dead time into one of the PWM the PWM generation process is 2tCK (or 77 ns for a 26 MHz
signals of a given pair during these transitions is only needed if CLKOUT), since incrementing one of the duty cycle registers
otherwise both PWM signals would be required to toggle at the by one changes the resultant on-time of the associated PWM
PWMSYNC boundary. The additional dead time delay is in- signals by tCK in each half period (or 2tCK for the full period). In
serted into the PWM signal that is toggling into the ON state. double update mode, improved resolution is possible since
In effect the turn ON of this signal is delayed by an amount different values of the duty cycles registers are used to define the
2 × PWMDT × tCK from the rising edge of PWMSYNC. After on-times in both the first and second halves of the PWM period.
this delay, the PWM signal is allowed to turn ON, provided the As a result, it is possible to adjust the on-time over the whole
desired output is still the ON state after the dead time delay. period in increments of tCK. This corresponds to an effective
PWM resolution of tCK in double update mode (or 38.5 ns for a
Figure 24 illustrates two examples of such transitions where in 26 MHz CLKOUT). The achievable PWM switching frequency
Figure 24(a) when transitioning from normal modulation to full at a given PWM resolution is tabulated in Table IV.
ON at the half cycle boundary in double update mode, no special
action is needed. However, in Figure 24(b) when transitioning into Table IV. Achievable PWM Resolution in Single and Double
full OFF at the same boundary, it can be seen that an additional Update Modes (CLKOUT = 26 MHz)
dead time is necessary.
PWMCHA1 Resolution Single Update Mode Double Update Mode
(Bits) PWM Frequency (kHz) PWM Frequency (kHz)
FULL ON
AH
8 50.8 102
2
PWMDT 9 25.4 50.8
(a)
AL 10 12.7 25.4
11 6.35 12.7
FULL OFF 12 3.17 6.35
AH

(b) OUTPUT CONTROL UNIT, PWMSEG REGISTER

AL 2
PWMDT The operation of the Output Control Unit is controlled by the
DEAD TIME INSERTED
9-bit read/write PWMSEG register which controls two distinct
features that are directly useful in the control of ECM or BDCM.
PWMTM PWMTM
Crossover Feature
Figure 24. Examples of transitioning form normal modu- The PWMSEG register contains three crossover bits; one for
lation into either Full ON or Full OFF where it may be nec- each pair of PWM outputs. Setting Bit 8 of the PWMSEG regis-
essary to insert additional dead times. ter enables the crossover mode for the AH/AL pair of PWM
REV. B –31–
ADMC401
signals, setting Bit 7 enables crossover on the BH/BL pair of PWMCHA PWMCHA
= PWMCHB = PWMCHB
PWM signals and setting Bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
AH
of PWM signals, the high side PWM signal from the timing unit 2
2
PWMDT
(AH say) is diverted to the associated low side output of the PWMDT

Output Control Unit so that the signal will ultimately appear at AL

the AL pin. Of course, the corresponding low side output of the

Timing Unit is also diverted to the complementary high side BH
output of the Output Control Unit so that the signal appears at
the AH pin. Following a reset, the three crossover bits are cleared BL
so that the crossover mode is disabled on all three pairs of PWM
signals.
CH
Output Enable Function
The PWMSEG register also contains six bits (Bits 0 to 5) that CL

can be used to individually enable or disable each of the six

PWMTM PWMTM
PWM outputs. The PWM signal of the AL pin is enabled by
setting Bit 5 of the PWMSEG register while Bit 4 controls AH, Figure 25. Example active LO PWM signals suitable for
Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL and Bit ECM control, PWMCHA = PWMCHB, crossover BH/BL pair
0 controls the CH output. If the associated bit of the PWMSEG and disable AL, BH, CH and CL outputs. Operation is in
register is set, the corresponding PWM output is disabled irre- single update mode.
spective of the value of the corresponding duty cycle register.
This PWM output signal will remain in the OFF state as long as GATE DRIVE UNIT, PWMGATE REGISTER
the corresponding enable/disable bit of the PWMSEG register is High Frequency Chopping
set. This output enable function is implemented after the cross- The Gate Drive Unit of the PWM controller adds features that
over function. Following a reset, all six enable bits of the simplify the design of isolated gate drive circuits for PWM invert-
PWMSEG register are cleared so that all PWM outputs are ers. If a transformer-coupled power device gate drive amplifier is
enabled by default. In a manner identical to the duty cycle used, the active PWM signal must be chopped at a high fre-
registers, the PWMSEG is latched on the rising edge of the quency. The 10-bit PWMGATE register allows the program-
PWMSYNC signal so that changes to this register only become ming of this high frequency chopping mode. The chopped active
effective at the start of each PWM cycle in single update mode. PWM signals may be required for the high-side drivers only, for
In double update mode, the PWMSEG register can also be the low side drivers only or for both the high side and low side
updated at the midpoint of the PWM cycle. switches. Therefore, independent control of this mode for both
Brushless DC Motor (Electronically Commutated Motor) high and low side switches is included with two separate control
Control bits in the PWMGATE register.
In the control of an ECM only two inverter legs are switched at Typical PWM output signals with high frequency chopping
any time and often the high side device in one leg must be switched enabled on both high side and low side signals are shown in
ON at the same time as the low side driver in a second leg. Figure 26. Chopping of the high side PWM outputs (AH, BH
Therefore, by programming identical duty cycle values for two and CH) is enabled by setting Bit 8 of the PWMGATE register.
PWM channels (i.e., PWMCHA = PWMCHB) and setting Bit 7 Chopping of the low side PWM outputs (AL, BL and CL) is
of the PWMSEG register to crossover the BH/BL pair of PWM enabled by setting Bit 9 of the PWMGATE register. The high
signals, it is possible to turn ON the high side switch of Phase A frequency chopping frequency is controlled by the 8-bit word
and the low side switch of phase B at the same time. In the (GDCLK) placed in Bits 0 to 7 of the PWMGATE register.
control of ECM, it is usual that the third inverter leg (Phase C The period of this high frequency carrier is:
in this example) be disabled for a number of PWM cycles. This
function is implemented by disabling both the CH and CL
PWM outputs by setting Bits 0 and 1 of the PWMSEG register.
[ (
TCHOP = 4 × GDCLK + 1 × tCK )]
This situation is illustrated in Figure 25, where it can be seen and the chopping frequency is therefore an integral subdivision
that both the AH and BL signals are identical, since PWMCHA of the CLKOUT frequency:
= PWMCHB and the crossover bit for Phase B is set. In addi-
fCLKOUT
tion, the other four signals (AL, BH, CH and CL) have been fCHOP =
disabled by setting the appropriate enable/disable bits of the
PWMSEG register. For the situation illustrated in Figure 25,
[4 × (GDCLK +1)]
the appropriate value for the PWMSEG register is 0x00A7. In The GDCLK value may range from 0 to 255, corresponding
normal ECM operation, each inverter leg is disabled for certain to a programmable chopping frequency rate from 25.4 kHz to
periods of time, so that the PWMSEG register is changed based 6.5 MHz for a 26 MHz CLKOUT rate. The gate drive features
on the position of the rotor shaft (motor commutation). must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following reset, all bits of the PWMGATE
register are cleared so that high frequency chopping is disabled,
by default.

–32– REV. B
 ADMC401
PWMCHA PWMCHA PWMCHA1 PWMCHA2

AH AH

2
PWMDT 2
PWMDT

AL AL

[4
(GDCLK+1)]
PWMCHB1 PWMCHB2
BH
PWMTM PWMTM

Figure 26. Typical active LO PWM signals with high fre-

BL
quency gate chopping enabled on both high side and low
side switches. PWMCHC1 PWMCHC2
CH
PWM Polarity Control, PWMPOL Pin
The polarity of the PWM signals produced at the output pins
AH to CL may be selected in hardware by the PWMPOL pin. CL
Connecting the PWMPOL pin to DGND selects active LO
PWMTM PWMTM
PWM outputs, such that a LO level is interpreted as a com-
mand to turn on the associated power device. Conversely, con- Figure 27. Active LO PWM signals in SR Mode (PWMPOL
necting the PWMPOL pin to VDD selects active HI PWM and = PWMSR = DGND) for ADMC401 in double update mode.
the associated power devices are turned ON by a HI level at the
PWM outputs. There is an internal pull-up on the PWMPOL PWM SHUTDOWN
pin, so that if this pin becomes disconnected (or is not connected), In the event of external fault conditions, it is essential that the
active HI PWM will be produced. The level on the PWMPOL PWM system be instantaneously shutdown in a safe fashion. A
pin may be read from Bit 2 of the SYSSTAT register, where a low level on the PWMTRIP pin provides an instantaneous,
zero indicates a measured LO level at the PWMPOL pin. asynchronous (independent of the DSP clock) shutdown of the
PWM controller. All six PWM outputs are placed in the OFF
SWITCHED RELUCTANCE MODE state (as defined by the PWMPOL pin). Note, however, when
The PWM block of the ADMC401 contains a switched reluc- the PWMSR pin is in the SR mode, the three low side PWM
tance (SR) mode that is controlled by the PWMSR pin. The signals from the three-phase timing unit will remain in the ON
switched reluctance mode is enabled by connecting the PWMSR state. In addition, the PWMSYNC pulse is disabled and the
pin to DGND. In this SR mode, the low side PWM signals from associated interrupt is stopped. The PWMTRIP pin has an
the three-phase timing unit assume permanently ON states, internal pull-down resistor so that if the pin becomes uncon-
independent of the value written to the duty-cycle registers. The nected the PWM will be disabled. The state of the PWMTRIP
duty cycles of the high side PWM signals from the timing unit pin can be read from Bit 0 of the SYSSTAT register.
are still determined by the three duty cycle registers. Using the The 12 PIO lines of the ADMC401 can also be configured to
crossover feature of the output control unit, it is possible to operate as PWM shutdown pins using the PIOPWM register.
divert the permanently ON PWM signals to either the high-side The 12-bit PIOPWM has a control bit for each PIO line (Bit 0
or low-side outputs. This mode is necessary because in the typi- controls PIO0, etc.). Setting the control bit enables the corre-
cal power converter configuration for switched or variable reluc- sponding PIO line as a PWM shutdown pin. A falling edge on
tance motors, the motor winding is connected between the two the PIO line will then generate an instantaneous, asynchronous
power switches of a given inverter leg. Therefore, in order to shutdown of the PWM system, in a manner identical to the
build up current in the motor winding, it is necessary to turn on PWMTRIP pin. Also like PWMTRIP, all of the PIO lines have
both switches at the same time. Typical active LO PWM signals internal pull-down resistors, so that if a PIO pin becomes uncon-
during operation in SR mode are shown in Figure 27 for opera- nected and is configured as a PWM shutdown pin, the PWM will
tion in double update mode. It is clear that the three low-side be disabled. Following a reset, all PIO lines are configured as
signals (AL, BL and CL) are permanently ON and the three high inputs, have pull-downs and are programmed as PWM shut
side signals are modulated in the usual manner so that the cor- down pins (PIOPWM = 0x0FFF) so that the PWM is shut-
responding high side power switches are switched between the down. Correct operation of the PWM is not possible without
ON and OFF states. The SR mode can only be enabled by con- first correctly configuring the PIO system.
necting the PWMSR pin to GND. There is no software means
by which this mode can be enabled. There is an internal pull-up In addition, it is possible to initiate a PWM shutdown in soft-
resistor on the PWMSR pin so that if this pin is left unconnected ware by writing to the 1-bit PWMSWT register. The act of
or becomes disconnected the SR mode is disabled. Of course, writing to this register generates a PWM shutdown command in
the SR mode is disabled when the PWMSR pin is tied to VDD. a manner identical to the PWMTRIP or PIO pins. A hardware
trip has no effect on the PWMSWT register. It does not matter
which value is written to the PWMSWT register. However,
following a PWM shutdown, it is possible to read the PWMSWT
register to determine if the shutdown was generated by hard-
ware or software. If the PWM shutdown was caused by the
PWMSWT register, a 1 will be read back from the PWMSWT
register. Reading the PWMSWT register automatically clears
its contents.
REV. B –33–
ADMC401
Table V. Fundamental Characteristics of PWM Generation Unit of ADMC401 (CLKOUT = 26 MHz)

Parameter Test Conditions Min Typ Max Unit

Counter Resolution 16 Bits
Edge Resolution Double Update Mode 38.5 ns
TD Programmable Dead Time 0 78.8 µs
Dead Time Increments 77.0 ns
TMIN Programmable Minimum Pulsewidth 0 39.4 µs
Minimum Pulsewidth Increments 38.5 ns
fPWM PWM Switching Frequency 16-Bit Resolution 198 Hz
fPWM PWM Switching Frequency1 8-Bit Resolution 102 kHz
TPWMSYNC PWMSYNC Pulsewidth 38.5 9850 ns
PWMSYNC Pulsewidth Increments 38.5 ns
fCHOP Gate Drive Chopping Frequency 25.4 6500 kHz
NOTE: Higher switching frequencies are possible at reduced resolutions (i.e., 202.8 kHz at 7 bits, 405.6 kHz at 6 bits, etc.)

On the occurrence of a PWM shutdown command (either from with encoder signals at frequencies of up to 4.33 MHz, corre-
the PWMTRIP pin, the PIO lines or the PWMSWT register), sponding to a maximum quadrature frequency of 17.3 MHz
a PWMTRIP interrupt will be generated. In addition, the (assuming an ideal quadrature relationship between the input
PWMSYNC pulse no longer appears at the output pin. How- EIA and EIB signals).
ever, internal operation of the PWM timer continues. Following
a PWM shutdown, the PWM can only be re-enabled (in a
ENCODER LOOP TIMER ENCODER EVENT
PWMTRIP interrupt service routine, for example) by writing to TIMER BLOCK
all of the PWMTM, PWMCHA, PWMCHB and PWMCHC
registers. Provided the external fault has been cleared and the CLOCK DIVIDER EETDIV(15…0)
TIMEOUT
PWMTRIP or appropriate PIO lines have returned to a HI EIUSCALE (7…0) ENCODER EVENT
TIMER
EETSTAT(0)
EIUTIMER (15…0) EETT(15…0)
level, the PWM controller will restart. PULSE EETDELTAT(15…0)
EIUPERIOD (15…0)
DECIMATOR EETN(7…0)
PWM REGISTERS
The PWM registers are described in at the end of this data sheet.
The parameters of the PWM block for operation at 26 MHz are DIRECTION QUADRATURE SIGNAL
tabulated in Table V.
ENCODER INTERFACE BLOCK

ENCODER INTERFACE UNIT A EETCNT(15…0)

EIA 16-BIT
QUADRATURE EIUCNT(15…0)
OVERVIEW OF ENCODER INTERFACE UNIT EIB B UP/DOWN EIUMAXCNT(15…0)
The ADMC401 incorporates a powerful encoder interface to PROGRAMMABLE
COUNTER EIUCTRL(8…0)
incremental shaft encoders, that are often used for position NOISE FILTERS EIUSTAT(7…0)
EIZ Z
ENCODER EISLATCH(15…0)
feedback in high performance motion control systems. The EIS S COUNTER EIZLATCH(15…0)
functional block diagram of the entire encoder interface system CONTROL EIUFILTER(5…0)
of the ADMC401 is shown in Figure 28.
The encoder interface unit (EIU) includes a 16-bit quadrature
up/down counter, programmable input noise filtering of the Figure 28. Configuration of Encoder Interface System of
encoder input signals and the zero markers, and has four dedi- ADMC401
cated pins on the ADMC401. The quadrature encoder signals The EIU may be programmed to use the zero marker on EIZ to
(or alternatively, frequency and direction inputs) are applied at reset the quadrature encoder in hardware, if required. Alterna-
the EIA and EIB pins. In addition, two zero marker/strobe in- tively, the zero marker can be ignored and the encoder quadra-
puts are provided on pins EIZ and EIS. These inputs may be ture counter is reset according to the contents of a maximum
used to latch the contents of the encoder quadrature counter count register, EIUMAXCNT. There is also a “single north
into dedicated registers, EIZLATCH and EISLATCH, on the marker” mode available in which the encoder quadrature
occurrence of external events at the EIZ and EIS pins. These counter is reset only on the first zero marker pulse. Both modes
events may be programmed to be either rising edge only (latch are enabled by dedicated control bits in the EIU control regis-
event) or rising edge if the encoder is moving in the forward ter, EIUCTRL. A status bit is set in the EIUSTAT register on
direction and falling edge if the encoder is moving in the reverse the first occurrence of the zero marker.
direction (software latched zero marker functionality). The
The encoder interface unit can also be made to implement some
encoder interface unit incorporates programmable noise filtering
error checking functions. If the error checking mode is enabled,
on the four encoder inputs to prevent spurious noise pulses from
upon the occurrence of a zero pulse, the contents of the encoder
adversely affecting the operation of the quadrature counter. The
counter register are compared with the expected value (0 or
encoder interface unit operates at a clock frequency equal to the
EIUMAXCNT depending on the direction of rotation). If an
DSP instruction rate. The encoder interface unit operates correctly
encoder count error is detected, a status bit in the EIUSTAT

–34– REV. B
 ADMC401
register is set and an EIU count error interrupt is generated. written to, the encoder interface unit is not initialized and
An additional status bit is provided in the EIUSTAT register Bit 2 of the EIUSTAT register is set. The contents of the
that indicates the initialization state of the EIU. Until the EIUMAXCNT register are used in certain operating modes to
EIUMAXCNT register is written to, the EIU is not initialized. reset the quadrature counter. The contents of the EIUMAXCNT
Four status bits in the EIUSTAT register provide the state of the register are also used for error checking of the EIU. Operation
four EIU inputs, EIA, EIB, EIZ and EIS. of the encoder interface is controlled by the EIUCTRL register.
The encoder interface unit of the ADMC401 contains a 16-bit Programmable Input Noise Filtering of Encoder Signals
loop timer that behaves in a manner similar to the program- A functional block diagram of the input stages of the encoder
mable interval timer of the DSP core. The loop timer consist of interface is shown in Figure 29. The four encoder input signals
a timer register, period register and scale register so that it can (EIA, EIB, EIZ and EIS) are first synchronized in input syn-
be programmed to timeout and reload at appropriate intervals. chronization buffers. This eliminates the asynchronous nature of
A control bit in the EIUCTRL register is used to enable/disable real world encoder signals prior to use in the encoder interface
this loop timer. When this loop timer times out, an EIU loop unit logic. Subsequently, all four synchronized signals (EIAS,
timer timeout interrupt is generated. This interrupt could be EIBS, EIZS and EISS) are applied to programmable noise filter-
used to control the timing of speed and position control loops in ing circuits that can be programmed to reject pulses that are
high performance drives. shorter than some suitable value. The outputs of the filter stage
The encoder interface unit also includes a high performance are applied to the quadrature counter stage.
encoder event timer (EET) block that permits the accurate
timing of successive events of the encoder inputs. The EET can EIA
EIAS
A
be programmed to time the duration between up to 255 encoder EIBS
EIB B
pulses and can be used to enhance velocity estimation, particu- INPUT
SYNCHRONIZA- THREE STAGE
larly at low speeds of rotation. The information from the regis- EIZ TION EIZS DIGITAL FILTER Z
STAGE
ters of the EET block can be latched in two ways. In one mode, EISS
EIS S
the contents of the EIU quadrature count register, EIUCNT
and all relevant EET registers (EETT and EETDELTAT) are
latched when the EIU loop timer times out. In the second mode,
the act of reading the EIUCNT register also simultaneously CLKOUT CLOCK EIUFILTER(5…0)
DIVIDE
latches the EET registers. The EET data latching mode is se-
lected by a control bit in the EIUCTRL register. Figure 29. Functional Block Diagram of Input Stage
of Encoder Interface
ENCODER LOOP TIMER
Each of the four synchronized input signals (EIAS, EIBS, EIZS
The EIU contains a 16-bit loop timer that is structured in a
and EISS) is applied to a three clock cycle delay filter such that
manner similar to the interval timer of the DSP core (TCOUNT,
the filtered output signals are not permitted to change until a
TPERIOD and TSCALE registers). The corresponding regis-
stable value has been registered for three successive clock cycles.
ters of the encoder loop timer are the 16-bit EIUTIMER and
While the encoder signals are changing, the filter maintains the
EIUPERIOD registers and the 8-bit EIUSCALE register. The
previous output value. The clock frequency used for the filter
EIU loop timer is clocked at the CLKOUT rate, tCK.
circuits is programmed by Bits 0 to 5 of the EIUFILTER regis-
The EIU loop timer can be used to generate periodic interrupts ter. The 6-bit quantity written to Bits 0 to 5 of the EIUFILTER
based on multiples of the DSP cycle time. The EIU loop timer register is used to divide the CLKOUT frequency and provide
is enabled by setting Bit 5 of the EIUCTRL register. When the clock source for the encoder noise filters. If the value written
enabled, the 16-bit timer register (EIUTIMER) is decremented to Bits 0 to 5 of the EIUFILTER register is N, the period of the
every N cycles, where N-1 is the scaling value stored in the 8-bit clock source used in the encoder filters is (N + 1) × tCK. This
EIUSCALE register. When the value of the EIUTIMER register filter structure guarantees that encoder pulses of less width than
reaches zero, the EIU loop timer timeout interrupt is generated 2 × (N + 1) × tCK will always be rejected by the filter stage.
and the EIUTIMER register is reloaded with the 16-bit value in Additionally, pulses greater than 3 × (N + 1) × tCK will always
the EIUPERIOD register. The scaling feature of this timer, get through the filter stage and be passed to the internal quadra-
provided by the EIUSCALE register, allows the 16-bit timer to ture counter. Encoder pulses of widths between 2 × (N + 1) ×
generate periodic interrupts over a wide range of periods. For a tCK and 3 × (N+1) × tCK may either pass through or be rejected
26 MHz CLKOUT rate (38.5 ns period), the timer can gener- by the encoder filter. Whether or not such pulses pass through
ate interrupts with periods of 38.5 ns up to 2.52 ms with a zero the filter depends on the exact nature of the synchronization
scale value (EIUSCALE = 0). When scaling is used, time peri- between the external asynchronous pulses and the internal DSP
ods can range up to 0.645 sec. The EIU loop timer timeout clock and is impossible to predict.
interrupt can be masked in the PICMASK register.
For example, writing a value of 3 to the EIUFILTER register,
means that the clock frequency used in the encoder filters is
ENCODER INTERFACE STRUCTURE AND OPERATION
6.5 MHz (for a CLKOUT rate of 26 MHz). In order to register
Introduction
as a stable value, the encoder input signals must be stable for
The encoder interface section consists of a 16-bit quadrature
three of these 6.5 MHz cycles (or 462 ns). Consequently, the
up/down counter and a 16-bit EIUCNT register that allows the
smallest period that will be registered on the synchronized en-
up/down counter to be read by the DSP. There is also a 16-bit
coder inputs is 924 ns, corresponding to a maximum encoder
EIUMAXCNT register that must be written to, to initialize the
encoder system. Until the EIUMAXCNT register has been
REV. B –35–
ADMC401
rate of 1.08 MHz. In general, the maximum encoder rate that each edge. This (A signal leads the B signal) is defined as the
can be consistently recognized is given by: forward direction of motion. Setting Bit 0 of the EIUCTRL regis-
ter causes the signal at the EIA pin to be fed to the B input to
fCLKOUT
f ENCMAX = the quadrature counter and the signal EIB becomes the A input
6 × ( N + 1) to the quadrature counter. Therefore, if the EIA signal led the
Operation of both the input synchronization logic and the EIB signal at the pins of the ADMC401, the A input to the
noise filters is shown in Figure 30 for the default case where quadrature counter will now lag the B input. This will be recog-
EIUFILTER(5::0) = 0x00 and the noise filters are clocked at nized as rotation in the reverse direction and the counter will be
CLKOUT. decremented on each quadrature pulse. Following a reset, the
REV bit is cleared.
1tCK The two encoder signals are used to derive a quadrature signal
CLKOUT that is used, in conjunction with a direction bit, to increment or
decrement the encoder counter and also the encoder event
EIA timer. The status of the direction signal is indicated at Bit 1
of the EIUSTAT register. While the encoder counter is incre-
NOISE PULSE
menting, Bit 1 is set. Alternatively, when the encoder counter
EIB
is decrementing, Bit 1 of the EIUSTAT register is cleared.
Alternative Frequency and Direction Inputs
EIAS
Instead of the quadrature EIA and EIB encoder inputs, the
encoder interface unit can also accept alternative Frequency and
EIBS Direction Inputs. This mode is enabled by setting Bit 6 of the
3tCK EIUCTRL register. In this so-called FD Mode, the EIA input
A
pin accepts a frequency signal and the EIB pin accepts the di-
rection signal. The signal on these pins are subject to the same
3tCK
synchronization and filtering logic as described previously. How-
B
ever, in this mode the quadrature counter is incremented or
decremented on both the falling and rising edges of the signal
Figure 30. Operation of input synchronization and noise on the EIA pin. If the EIB pin is LO, forward operation is as-
filters of encoder interface with EIUFILTER(5:0) = 0x00 sumed and the counter is incremented on each edge of the fre-
such that the filters are operated at CLKOUT. quency signal on the EIA input. On the other hand, if the EIB
The default value for EIUFILTER(5::0) following a power on pin is HI, reverse rotation is assumed and the quadrature
or reset is 0x00 so that the EIU filters are clocked at the CLK- counter is decremented at each edge of the signal on the EIA
OUT rate and minimal filtering is applied. There is a direct pin. On power-up or reset, Bit 6 of the EIUCTRL register is
trade-off between the amount of filtering applied to the encoder cleared so that this mode is disabled by default. The following
inputs and the maximum possible encoder signal rate. In effect, modes are not supported when FD Mode is enabled: Encoder
the larger the value of EIUFILTER(5::0), the more filtering that Counter Reset mode, Single North Marker mode, and Encoder
is applied to the encoder signals, so that, for a given number of Error Checking mode. In other words, when Bit 6 of EIUCTRL
encoder lines, the maximum speed of rotation is lower. is set, Bits 1, 2, and 3 should be cleared.

The influence of the encoder filter on the zero marker signals Encoder Counter Reset
(EIZ and EIS) can be somewhat different that on the EIA or The ZERO bit (Bit 1) of the EIUCTRL register determines if
EIB signals, depending on the exact nature of the encoder. In the encoder zero marker is used to hardware reset the up/down
common incremental encoders, the width of the zero marker counter of the encoder interface. When Bit 1 of the EIUCTRL
can be equal to a quarter, a half or a full period of one of the register is set, the zero marker signal on the EIZ pin is used to
quadrature signals (say EIA). Applying the three-stage delay reset the up/down counter to zero (if moving in the forward
filter to a zero marker whose width is either equal to half or a direction) or to the value in the EIUMAXCNT register (if mov-
full quadrature pulse period does not change the achievable ing in the reverse direction). The reset operation takes place on
maximum encoder rate. However, the maximum possible en- the next quadrature pulse after the zero marker has been recog-
coder rate is changed if the three-stage filter is applied in the nized. In order to ensure correct encoder counting (no missing
case where the width of the zero marker is equal to a quarter of or spurious codes) the logic in the encoder counter latches the
the EIA or EIB period. In this case the influence of the three- conditions (appropriate encoder edge) at which the first reset is
stage delay filter is to effectively half the maximum encoder performed. Thereafter, irrespective of operating conditions, the
signal rate to that described above (or 2.15 MHz for a 26 MHz encoder reset operation is always aligned with the same encoder
CLKOUT rate). edge. For example, if the first reset operation occurs on the
rising edge of B and the encoder is moving in the forward direc-
Encoder Counter Direction tion, then all subsequent reset operations are aligned with the
The direction of quadrature counting is determined by Bit 0 rising edge of the B signal (while moving in the forward direc-
(REV) of the EIUCTRL register. If the REV bit is cleared, the tion) and on the falling edge of B for rotation in the reverse
signal at the EIA pin is fed to the A input to the quadrature direction. In order to account for zero marker signals of differ-
counter and the EIB pin is fed to the B input. Thus, if the EIA- ent widths, the zero marker will be recognized as the rising edge
encoder signal leads the EIB-signal (and therefore the A signal of the EIZ signal when moving in the forward direction. When
leads the B signal), the quadrature counter is incremented on

–36– REV. B
 ADMC401
moving in the reverse direction, the zero marker is recognized at register is set, the operation is slightly different to that for the Z
the falling edge of the signal at the EIZ pin. input. With the S input, the EIUCNT contents are latched to
When the ZERO bit of the EIUCTRL register is cleared, the the EISLATCH register on the occurrence of a rising edge of
zero marker is not used to reset the counter. In this mode, the the S signal if the quadrature counter is incrementing (count
contents of the EIUMAXCNT register are used as the reset up). If the quadrature counter is decrementing, the EIUCNT
value for the up/down counter. For example, for an N-line contents are latched to the EISLATCH register on the occur-
incremental encoder, the appropriate value to write to the rence of the falling edge of the S signal. The difference is that
EIUMAXCNT register is 4N–1. Therefore, for a 1024 line the latching occurs at the event on the S input and not at the
encoder, a value of 0x0FFF (= 4095) would be written to the next quadrature event (as with this case on the Z input).
EIUMAXCNT register. However, since absolute position infor- EIZLATCH and EISLATCH are 16-bit read-only registers
mation is not available in this mode, due to the absence of the whose state is undefined on power-up. On power-up or follow-
zero marker, the full 16-bit range of the quadrature counter may ing a reset, both Bits 7 and 8 of the EIUCTRL register are
be employed by writing a value of 0xFFFF to the EIUMAXCNT cleared.
register. Following a reset, the ZERO bit is cleared. The value Single North Marker Mode
written to the EIUMAXCNT register must be in the form A further reset mode, called Single North Marker Mode, is avail-
4N–1, where N is any integer. able in the encoder interface unit . This mode is enabled by
Registration Inputs and Software Zero Marker setting Bit 2 (SNM) of the EIUCTRL register. For this mode to
The encoder interface unit of the ADMC401 provides two operate the ZERO bit (Bit1) of the EIUCTRL register must
marker signals, EIZ and EIS that are both filtered and synchro- also be set. In this mode, the EIUCNT register is reset (to zero
nized in a manner identical to the other encoder signals to pro- or EIUMAXCNT, depending on direction) only on the first
duce the Z and S signals. Z can be used as a hardware reset of occurrence of the zero marker. Subsequently, the EIUCNT
the encoder counter, as described above. However, in many register is reset by the natural roll-over to zero or the value in
applications a hardware reset of the counter may not be desir- the EIUMAXCNT register. Following a reset, this SNM bit is
able. Instead, the encoder counter can be programmed to cleared. Bit 7 of the EIUSTAT register is used to signal the first
operate in full 16-bit roll-over mode, by clearing Bit 1 of the occurrence of a zero marker. When the first zero marker has been
EIUCTRL register and programming EIUMAXCNT to be recognized by the EIU, Bit 7 of the EIUSTAT register is set.
0xFFFF. In this case, the quadrature counter will use the full Encoder Error Checking
16-bit range of the EIUCNT register. Error checking in the EIU is enabled by setting Bit 3 (MON) of
The signals on Z and S can be configured to latch the contents the EIUCTRL register. To be enabled, the ZERO bit of the
of the EIUCNT register into dedicated memory mapped regis- EIUCTRL register must also be set for error checking. In this
ters (EIZLATCH for the Z signal and EISLATCH for the S mode, the contents of the EIUCNT register are compared with
signal) on the occurrence of definite events on these pins. The the expected value (zero or EIUMAXCNT depending on direc-
exact nature of the events are determined by Bit 7 of the tion) when the zero marker is detected. If a value other than the
EIUCTRL register for the Z input and Bit 8 of the EIUCTRL expected value is detected, an error condition is generated by
register for the S signal. setting Bit 0 of the EIUSTAT register and triggering an EIU
If Bit 7 of the EIUCTRL register is cleared, the contents of the count error interrupt. This EIU count error interrupt is man-
EIUCNT register are latched to the EIZLATCH register on the aged and may be masked by the programmable interrupt con-
occurrence of a rising edge on the Z signal. In this mode, the troller (PIC) block. The encoder continues to count encoder
signals can be used to latch or freeze the EIUCNT contents on edges after an error has been detected. Bit 0 of the EIUSTAT
the occurrence of an external event such as that from limit switches register is cleared on the occurrence of the next zero marker
or other triggers. If Bit 7 of the EIUCTRL register is set, then provided the error condition no longer exists and the EIUCNT
the EIUCNT contents are latched to the EIZLATCH register register again matches the expected value. Following a reset, the
on the occurrence of the next quadrature pulse following the MON bit is cleared.
rising edge of the Z signal if the quadrature counter is incre- Encoder Input Status
menting (count up). If the quadrature counter is decrementing, Four additional status bits are provided in the EIUSTAT regis-
the EIUCNT contents are latched to the EIZLATCH register ter that provide a measure of the state of the four EIU inputs
on the next quadrature pulse following the falling edge of the Z following the synchronization buffers and input filter. Bit 3 indi-
signal. In this mode, the action resembles that of a zero marker cates the state of the EIA signal, Bit 4 indicates the state of the
function. The advantage is that the EIUCNT register contents EIB signal, Bit 5 gives the state of the EIZ signal and Bit 6 gives
are latched at the appropriate zero marker inputs, but the con- the state of the EIS signal. The value of these status bits read is
tents of the quadrature counter are not affected. not affected by any of the control bits in the EIUCTRL register.
Bit 8 of the EIUCTRL register defines the S events that cause
the EIUCNT register to be latched to the EISLATCH register. ENCODER EVENT TIMER
When Bit 8 of the EIUCTRL register is cleared, the contents of Introduction and Overview
the EIUCNT register are latched to the EISLATCH register on The encoder event timer block forms an integral part of the EIU
the occurrence of a rising edge on the S signal, in a manner of the ADMC401, as shown in Figure 28. The EET accurately
identical to that for the Z input. If Bit 8 of the EIUCTRL times the duration between encoder events. The information
provided by the EET may be used to make allowances for the

REV. B –37–
ADMC401
asynchronous timing of encoder and DSP-reading events. As a EETLATCH bit causes the data to be latched on the timeout of
result, more accurate computations of the position and velocity the encoder loop timer (EIUTIMER). At that time, the contents
of the motor shaft may be performed. of the encoder quadrature counter (EIUCNT) are latched to a
The EET consists of a 16-bit encoder event timer, an encoder 16-bit register EETCNT. In addition, the contents of the inter-
pulse decimator and a clock divider. The EET clock frequency is mediate Interval Time register are latched to the EETT register
selected by the 16-bit read/write EETDIV clock divide register, and the contents of the encoder event timer are latched to the
whose value divides the CLKOUT frequency. The contents of EETDELTAT register. The three registers, EETCNT, EETT
the encoder event timer are incremented on each rising edge of and EETDELTAT, then contain the desired triplet of position/
the divided clock signal. An EETDIV value of zero gives the speed data required for the control algorithm. In addition, if the
maximum divide value of 0x10000 (= 65,536), so that the timeout of the EIUTIMER is used to generate an EIU loop
clock frequency to the encoder event timer is at its minimum timer interrupt, the required data is automatically latched and
possible value. waiting for execution of the interrupt service routine (which may
be some time after the timeout instant if there are multiple
The quadrature signal from the encoder interface unit is deci- interrupts in the system). By latching the EIUCNT register to
mated at a rate determined by the 8-bit read/write EETN regis- the EETCNT, the user does not have to worry about changes in
ter. For example, writing a value of two to EETN, produces a the EIUCNT register (due to additional encoder edges) prior to
pulse decimator output train at half the quadrature signal fre- servicing of the EIU loop timer interrupt.
quency, as shown in Figure 31. The rising edge of this deci-
mated signal is termed a velocity event. Therefore, for an EETN The other EET latch event is defined by clearing the EETLATCH
value of two, a velocity event occurs every two encoder edges, or bit of the EIUCTRL register. In this mode, whenever, the
on each edge of one of the encoder signals. An EETN value of 0 EIUCNT register is read by the DSP, the current value of the
gives an effective pulse decimation value of 256. intermediate Interval Time register is latched to the EETT
register and the contents of the encoder event timer are latched
On the occurrence of a velocity event, the contents of the en- to the EETDELTAT register. The three registers, EIUCNT,
coder event timer are stored in an intermediate Interval Time EETT and EETDELTAT now contain the desired triplet of
Register. Under normal operation, this register stores the elapsed position/speed data required for the control algorithm. Note the
time between successive velocity events. After the timer value difference from before, in that the encoder count value is now
has been latched at the velocity event, the contents of the en- available in the EIUCNT register.
coder event timer are reset to one.
It is important to realize that the EETT, and EETDELTAT regis-
ters are only updated by either the timeout of the EIUTIMER
A register (if EETLATCH bit is set) or the act of reading the
B EIUCNT register (if the EETLATCH bit is cleared). Therefore,
QUADRATURE
SIGNAL if the EETLATCH bit is set, the act of reading the EIUCNT
register will not update the EETT and EETDELTAT registers.
EIUCNT
Following reset, Bit 4 of the EIUCTRL is cleared.
VELOCITY EET Status Register
EVENTS
There is a 1-bit EETSTAT register that indicates whether or
EETDELTAT
ENCODER EVENT not an overflow of the EET has occurred. If the time between
TIMER VALUE EETT successive velocity events is sufficiently long, it is possible that
the encoder event timer will overflow. When this condition is
EET LATCH
EVENT
detected, Bit 0 of the EETSTAT register is set and the EETT
register is fixed at 0xFFFF. Reading the EETSTAT register
Figure 31. Operation of Encoder Interface Unit and EET of clears the overflow bit and permits the EETT register to be
ADMC401 in the Forward Direction with EETN = 2 updated at the next velocity event.
Latching Data from the EET If an encoder direction reversal is detected by the EIU, the
When using the data from the Encoder Event Timer, it is im- encoder event timer is set to 1 and the EETT register is set to
portant to latch a triplet set of data at the same instant in time. its maximum 0xFFFF value. Subsequent velocity events will
The three pieces of data are the contents of the encoder quadra- cause the EETT register to be updated with the correct value. If
ture up/down counter, the stored value in the Interval Time a value of 0xFFFF is read from the EETT register, Bit 0 of the
Register (giving the precise measured time between the last two EETSTAT register can be read to determine whether an over-
velocity events) and the present value of the encoder event timer flow or direction reversal condition exists.
(giving an indication of how much time has passed since the last
On reset the EETN, EETDIV, EETDELTAT and EETT regis-
velocity event).
ters are all cleared to zero. Whenever either the EETN or EETDIV
The data from the EET can be latched on the occurrence of registers are written to, the encoder event timer is reset to zero
two different events. The particular event is selected by and the EETT register is set to zero.
Bit 4 (EETLATCH) of the EIUCTRL register. Setting this

–38– REV. B
 ADMC401
Table VI. Fundamental Characteristics of Encoder Interface Unit of ADMC401 (At 26 MHz)

Parameter Test Conditions Min Typ Max Unit

fENC Encoder Input (EIA, EIB) Rate 4.33 MHz
fQUAD Quadrature Rate 17.3 MHz
Encoder Loop Timer Timeout Rate 38.5 ns
0.645 sec
TMINENC Minimum Encoder Pulsewidth EIUFILTER = 0x00 116 ns
EIUFILTER = 0x3F 7.39 µs

EIU/EET Registers PIO4 to PIO11 lines. The PICMASK register of the program-
The structure and functionality of the EIU and EET registers mable interrupt controller is used to enable interrupts on the
are illustrated at the end of the data sheet. The characteristics of four dedicated PIO lines, PIO0 to PIO3, and to enable the
the EIU block at 26 MHz are given in Table VI. usage of PIOINTEN for interrupts on the other PIOs.
Interrupts may be generated on either edge (rising or falling) or
PROGRAMMABLE DIGITAL INPUT/OUTPUT level (high or low) events by programming the appropriate bits
OVERVIEW of both the PIOMODE and PIOLEVEL registers. Both registers
The ADMC401 has 12 programmable digital input/output pins have a dedicated bit for each of the twelve PIO lines. Setting the
called PIO0 to PIO11. Each pin may be individually configured appropriate bit of the PIOMODE register configures the inter-
as either an input or an output. An associated data register may rupt as level sensitive whereas clearing the bit configures the
be used to read data from pins configured as inputs and write interrupt for edge sensitive. In level-sensitive mode (PIOMODE
data to pins configured as outputs. In addition, each I/O line bit is 1), setting the corresponding bit in the PIOLEVEL regis-
may be configured as an interrupt source. Both edge (rising and ter configures the interrupt as active high, whereas clearing the
falling) and level (high and low) interrupts may be detected. bit configures it for active low. In edge-sensitive mode (PIOMODE
Four of the PIO lines (PIO0 to PIO3) have dedicated vector bit is 0), setting the corresponding bit of the PIOLEVEL register
addresses in the interrupt table. The remaining eight interrupts configures the interrupt for rising edge, whereas clearing the bit
(PIO4 to PIO11) are multiplexed into a single additional inter- configures the interrupt for falling edge. On reset, all PIO inter-
rupt vector location. The PIOFLAG register is used to deter- rupts are disabled.
mine which line caused the interrupt. In addition, all PIO lines
The four dedicated PIO interrupts from PIO0 to PIO3 have
may be alternatively configured as PWM trip sources. The
interrupt vector addresses at program memory addresses 0x0048
PIOPWM register has dedicated bits that may be used to enable
for PIO0, 0x004C for PIO1, 0x0050 for PIO2 and 0x0054 for
this function on each PIO line. In this mode, a low level on any
PIO3. In the event of an interrupt on PIO4 to PIO11, the corre-
pins configured as a PWM trip source shuts down the PWM in
sponding bit of the PIOFLAG register is set and the general
a manner identical to the PWMTRIP pin.
PIO interrupt is activated. This interrupt has a dedicated vector
address at location 0x003C. In the interrupt service routine for
PIO CONFIGURATION
this interrupt, the user must poll the PIOFLAG register to de-
Each of the 12 programmable input/output lines may be config-
termine which of the PIO4 to PIO11 lines, that have interrupts
ured as either an input or an output by programming the appro-
enabled, caused the interrupt. Of course, if only one of the PIO4 to
priate bits of the PIODIR register. This 12-bit register has one
PIO11 lines has interrupts enabled, no polling is necessary.
bit associated with each I/O line; Bit 0 corresponds to PIO0, etc.
Clearing a bit in the PIODIR register will configure the corre- PIO lines that are configured as outputs may also be used to
sponding pin as an input line. Conversely, setting a bit config- generate interrupts. If, for example, one of the PIO lines is con-
ures the pin as an output pin. On reset, all bits of the PIODIR figured simultaneously as an output and as an interrupt source,
register are cleared so that all 12 PIO pins are configured as inputs. writing the appropriate data sequence to that line will trigger an
In addition, all PIO lines have internal pull-down resistors in the interrupt.
ADMC401 so that unconnected lines are seen as low level inputs.
PIO AS PWMTRIP SOURCES
PIO DATA READING/WRITING By setting the appropriate bits of the PIOPWM register, each of
Associated with the PIO system is a data register, PIODATA, the twelve PIO lines can be configured as a PWM shutdown
that also has a bit associated with each I/O line. Data written to source. In this mode, a low level on the PIO pin will cause a
the PIODATA register will appear on those pins configured as PWM shutdown command that will disable all six PWM out-
outputs. Reading the PIODATA register will read the data from puts on AH to CL. Since the disabling of the PWM is indepen-
those pins configured as inputs. dent of the DSP clock, so that the PWM stage can be fully
protected even in the event of a loss of clock signal to the DSP.
PIO INTERRUPT GENERATION In addition, a PWMTRIP interrupt will be generated when the
Each of the 12 PIO lines may be configured as an interrupt PWM is shutdown. However, it is also possible to generate the
source. Four of the PIO lines, PIO0 to PIO3, have dedicated normal PIO interrupts on the occurrence of a falling-edge on
interrupt vector locations, whereas the remaining eight are mul- the PIO line. The advantage of this highly flexible structure for
tiplexed into an additional interrupt vector. The PIOINTEN PWM shutdown is that multiple fault signals could be applied to
register is used to enable or disable the interrupt mode on the the ADMC401 at different PIO lines. The occurrence of a falling-

REV. B –39–
ADMC401
edge on any of them will instantaneously shut down the PWM. The clock frequency of the ETU timer may be expressed as
However, based on the particular PIO interrupt that is flagged, fCLKOUT/ETUDIVIDE and is common to both channels. At any
the user can easily determine the source of the shutdown. This time, the contents of the ETU timer may be read in the 16-bit
permits the action of the interrupt service routines following a read only ETUTIME register.
PWM shutdown to be tailored to the particular fault that occurred. Two events are used to trigger the ETU, termed Event A and
On reset, all PIO lines are configured as PWM shutdown sources. Event B. By setting the appropriate bits of the ETUCONFIG
Because all PIO lines are also configured as inputs and have register, it is possible to define both events A and B as either
internal pull-down resistors, any unconnected PIO lines will rising or falling edges on the appropriate pin. For example,
cause a PWM shutdown. Therefore, prior to using the PWM setting Bit 0 of the ETUCONFIG register defines Event A of
system of the ADMC401, it is imperative that the PIO stage be the ETU0 channel as a rising edge on the ETU0 pin. Similarly,
correctly configured for the particular application. setting Bit 4 of the ETUCONFIG register defines Event A of
the ETU1 channel as a rising edge on the ETU1 pin. Event A
PIO REGISTERS defines the start of the event capture sequence. Associated with
The configuration of all registers associated with the PIO system each ETU channel are three data registers, ETUA0, ETUB0
of the ADMC401 are shown at the end of the data sheet. Each and ETUAA0 for ETU Channel 0 and ETUA1, ETUB1 and
of the registers has a bit directly associated with one of the PIO ETUAA1 for ETU Channel 1. These data registers store the
lines. For example, Bit 0 of all registers affects only the PIO0 ETU timer value on the occurrence of the first A event, the first
line of the ADMC401. B event and the second A event, respectively. For example, for
ETU Channel 0, ETUA0 stores the timer value on the first
EVENT TIMERS occurrence of Event A on the ETU0 pin, ETUB0 stores the
OVERVIEW timer value on the first occurrence of Event B on the ETU0 pin
The ADMC401 contains a dual channel event timer (capture) and ETUAA0 store the timer value on the second occurrence
unit (ETU) that may be used to accurately measure the elapsed of Event A on the ETU0 pin. Registers ETUA1, ETUB1 and
time between defined instants on a particular channel. The ETU ETUAA1 perform the same function for events on ETU
has two dedicated input pins, ETU0 and ETU1. The ETU Channel 1.
system contains a set of 16-bit data registers that are used to
store the value of the dedicated ETU timer on the occurrence of ETU INTERRUPT GENERATION
defined events on the input pins. A configuration register is used The completion of the event capture sequence can be defined as
to define the nature of the events on each of the input pins. In either the occurrence of Event B or the second occurrence of
addition, a control register is used to initiate event capture on Event A by setting the appropriate bits of the ETUCONFIG
the inputs. A status register may be read to determine the state register. At the end of the capture sequence, the ETU generates
of the two capture channels. A dedicated ETU interrupt may be an interrupt. For example, if Bit 2 of the ETUCONFIG register
generated upon completion of a capture sequence on either the is set, ETU Channel 0 will generate an ETU interrupt on the
ETU0 or ETU1 channels. An event may be defined as either a occurrence of Event B on the ETU0 pin. On the other hand, if
rising or falling edge on the associated ETU0 and ETU1 input Bit 6 of the ETUCONFIG register is cleared, ETU Channel 1
pins. Therefore, the ETU system can be used to compute the will generate an ETU interrupt on the occurrence of the second
frequency, period, duty cycle or on-time of signals applied at the Event A on the ETU1 pin. Both ETU channels generate the
inputs. A block diagram of the ETU system of the ADMC401 is same interrupt to the DSP when capture is complete. If both
shown in Figure 32. ETU channels are used simultaneously, the ETUSTAT register
can be polled to determine the status of both channels and
determine which caused the interrupt. If capture on ETU Chan-
CAPTURE CHANNEL 0
nel 0 is complete, Bit 0 of the ETUSTAT register is set. Simi-
ETUA0(15…0)
EVENT ETUB0(15…0)
larly, if event capture on ETU Channel 1 is complete, Bit 1 of
ETU0
DETECTOR ETUAA0(15…0) the ETUSTAT register is set. Reading the ETUSTAT register
ETUDIVIDE(15…0) automatically clears all bits of the register.
ETUTIME(15…0)
ETU TIMER ETUCONFIG(7…0)
ETU OPERATING MODES
ETUCTRL(1…0)
ETUSTAT(1…0) The ETU channels of the ADMC401 can operate in two dis-
ETUA1(15…0) tinct modes; single shot and free-running. The particular mode
EVENT ETUB1(15…0)
ETU1 DETECTOR may be selected for ETU Channel 0 by programming Bit 3 of
ETUAA1(15…0)
the ETUCONFIG register and for ETU Channel 1 by program-
CAPTURE CHANNEL 1 ming Bit 7 of the ETUCONFIG register. Setting these bits puts
the respective ETU channel in free-running mode while clearing
Figure 32. Functional Block Diagram of Event Timer Unit the bits enables the single-shot mode. In single-shot mode, upon
of ADMC401 completion of the capture sequence and consequent generation
of the interrupt, further event capture is disabled until the inter-
ETU EVENT DEFINITION rupt has been serviced and the appropriate bit of the ETUCTRL
The ETU system of the ADMC401 contains a dedicated 16-bit register has been set. Setting Bit 0 of the ETUCTRL register
timer whose clock frequency may be programmed using the restarts the capture for ETU Channel 0, while Bit 1 restarts
ETUDIVIDE register. This register divides the CLKOUT capture for Channel 1. In the free-running mode, the bits of the
frequency to provide the clock signal for the ETU timer. ETUCTRL register remain set and the ETU channel continues
to capture following the generation of the interrupt.
–40– REV. B
 ADMC401
ETU REGISTERS this mode, the AUXTM1 register defines the offset time from
The configuration of the ETU registers is shown at the end of the rising edge of the signal on the AUX0 pin to that on the
the data sheet. AUX1 pin, according to:

AUXILIARY PWM TIMERS TOFFSET = 2 × ( AUXTM1+ 1) × tCK

The ADMC401 provides two variable-frequency, variable duty- For correct operation in this mode, the value written to the
cycle, 8-bit, auxiliary PWM outputs that are available at the AUXTM1 register must be less than the value written to the
AUX1 and AUX0 pins. These auxiliary PWM outputs can be AUXTM0 register. Typical auxiliary PWM waveforms in offset
used to provide switching signals to other circuits in a typical mode are shown in Figure (33)b. Again, duty cycles from 0% to
motor control system such as power factor corrected front-end 100% are possible in this mode.
converters or other switching power converters. Alternatively,
In both operating modes, the resolution of the auxiliary PWM
by addition of a suitable filter network, the auxiliary PWM out-
system is 8-bit only at the minimum switching frequency
put signals can be used as simple single-bit digital-to-analog
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
converters.
= 255 in offset mode). Obviously, as the switching frequency is
The auxiliary PWM system of the ADMC401 can operate in increased, the resolution is reduced.
two different modes, independent mode or offset mode. The oper-
Values can be written to the auxiliary PWM registers at any
ating mode of the auxiliary PWM system is controlled by Bit 8
time. However, new duty cycle values written to the AUXCH0
of the MODECTRL register. Setting Bit 8 of the MODECTRL
and AUXCH1 registers only become effective at the start of the
register places the auxiliary PWM system in the independent
next cycle. Writing to the AUXTM0 and AUXTM1 registers
mode. In this mode, the two auxiliary PWM generators are
causes the internal timers to be reset to 0 and new PWM cycles
completely independent, and separate switching frequencies and
to begin, only in independent mode.
duty cycles may be programmed for each auxiliary PWM out-
put. In this mode, the 8-bit AUXTM0 register sets the switch- By default, following reset, Bit 8 of the MODECTRL
ing frequency of the signal at the AUX0 output pin. Similarly, register is cleared and offset mode is enabled. AUXTM0 and
the 8-bit AUXTM1 register sets the switching frequency of the AUXTM1 default to 0xFF corresponding to minimum switch-
signal at the AUX1 pin. The fundamental time increment for ing frequency and zero offset. The on-time registers AUXCH0
the auxiliary PWM outputs is twice the DSP instruction rate (or and AUXCH1 default to 0x00.
2tCK) so that the corresponding switching periods are given by:
2
(AUXTM0+1)
TAUX 0 = 2 × ( AUXTM 0 + 1) × tCK
2
AUXCH0

TAUX1 = 2 × ( AUXTM1 + 1) × tCK AUX0

Since the values in both AUXTM0 and AUXTM1 can range

from 0 to 0xFF, the achievable switching frequency of the auxil- 2
(AUXTM1+1) (a)

iary PWM signals may range from 50.8 kHz to 13 MHz for a
CLKOUT frequency of 26 MHz. AUX1

The on-time of the two auxiliary PWM signals are programmed

2
AUXCH1
by the two 8-bit AUXCH0 and AUXCH1 registers, according
to:
2
(AUXTM0+1)
TON , AUX 0 = 2 × AUXCH 0 × tCK 2
AUXCH0

AUX0
TON , AUX1 = 2 × AUXCH1 × tCK
so that output duty cycles from 0% to 100% are possible. Duty (b)
2
(AUXTM0+1)
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent AUX1
mode are shown in Figure 33(a).
2
AUXCH1
When Bit 8 of the MODECTRL register is cleared, the auxiliary
PWM channels are placed in offset mode. In offset mode, the 2
(AUXTM1+1)

switching frequency of the two signals on the AUX0 and AUX1

Figure 33. Typical Auxiliary PWM Signals in (a) Indepen-
pins are identical and controlled by AUXTM0 in a manner
dent Mode and (b) Offset Mode
similar to that previously described for independent mode. The
on-times of both the AUX0 and AUX1 signals are controlled by
AUXILIARY PWM REGISTERS
the AUXCH0 and AUXCH1 registers as before. However, in
The registers of the auxiliary PWM system are illustrated at the
end of the data sheet.

REV. B –41–
ADMC401
WATCHDOG TIMER of PM. The priority of the peripheral interrupts is fixed in hard-
OVERVIEW ware. The ISR at address PM(0x30) has the highest priority
The watchdog timer is used as a protection mechanism against whereas the ISR at address PM(0x58) has the lowest.
unintentional software events causing the DSP to become stuck In the case of multiple simultaneous interrupts, the PIC will
in infinite loops. It can be used to cause a complete DSP and load the PICVECTOR register with the interrupt that has the
peripheral reset in the event of such a software error. The watch- highest priority. Between reads of the PICVECTOR register
dog timer consists of a 16-bit timer that is clocked at the CLKIN (while the DSP is servicing other interrupts for example)
rate, tCKI. PICVECTOR is updated with the highest priority of any periph-
The watchdog timer is disabled after a master reset (RESET = eral interrupts. This ensures that when the IRQ2 is reasserted,
LO). This also resets the WDFLAG bit in the SYSSTAT regis- the highest priority interrupt that occurred since the last reading
ter. The watchdog timer is enabled by writing a TIMEOUT value of the PICVECTOR register is now waiting to be serviced.
to the WDTIMER register. Once the watchdog timer has been When PICVECTOR is read, if another interrupt is pending in
initialized, the timer is decremented at the CLKIN rate. In the PIC, then the IRQ2 line to the DSP remains LO and no edge
order to prevent a watchdog timer trip, it is necessary to write will be seen. In order to catch all interrupts, IRQ2 interrupts
again to the WDTIMER register. For all writes to the WDTIMER should be configured as level sensitive in the ICNTL register.
register (subsequent to the initial write), it is unimportant which
value is written. The act of writing to the WDTIMER register The four least significant PIO pins are assigned unique vector
automatically reloads the initial TIMEOUT value. If the watch- addresses. An interrupt on any of the remaining eight lines
dog timer is not rewritten to after an interval: (PIO4 to PIO11) will trigger a separate fifth PIO interrupt that
has its own vector address. The PIOFLAG register can be read
TWDT = WDTIMER × tCKI to determine the exact source of this fifth interrupt. An 11-bit
the watchdog timer will decrement to zero and a watchdog trip PICMASK register can be used to enable or disable any or all of
will be generated. In this case, a complete reset of the DSP core the eleven peripheral interrupt sources. The program memory
and motor control peripherals (except the watchdog timer address reserved for each of the interrupts is summarized in
itself) is initiated and Bit 1 of the SYSSTAT register (WDFLAG) Table VII.
is set. Following a reset, the DSP core can determine if the reset
was caused by a watchdog trip (and if so take appropriate ac- Table VII. Interrupt Vector Addresses
tion) or if it was due to the normal reset sequence. The watchdog
timer remains disabled while the WDFLAG is set to prevent Function Vector Address
continuous watchdog trips. The watchdog timer can be restarted RESET Startup (or Power Up with
and the WDFLAG reset by writing a nonzero TIMEOUT value PUCR = 1) 0x00 (Highest Priority)
to the WDTIMER register. The WDFLAG will be reset, but Power-Down (Nonmaskable) 0x2C
the watchdog timer will remain disabled if 0x0000 is written to ADC End-of-Conversion Interrupt 0x30
the WDTIMER register. PWMSYNC Interrupt 0x34
The watchdog timer is only reset by a low input on the RESET EIU Loop Timer Timeout Interrupt 0x38
pin. The watchdog circuit is not reset by a software controlled PIO4 to PIO11 Interrupt 0x3C
Peripheral Reset. EIU Counter Error Interrupt 0x40
ETU Interrupt 0x44
PROGRAMMABLE INTERRUPT CONTROLLER PIO0 Interrupt 0x48
OVERVIEW PIO1 Interrupt 0x4C
The ADMC401 uses the IRQ2 pin of the DSP core to generate PIO2 Interrupt 0x50
a peripheral interrupt. There are multiple sources of peripheral PIO3 Interrupt 0x54
interrupts, e.g., the ADC block, PIO block, EIU block, ETU PWM Trip Interrupt 0x58
block and PWM block. A Programmable Interrupt Controller SPORT0 Transmit 0x10
(PIC) is used to avoid a software latency in determining the SPORT0 Receive 0x14
source of the interrupt. With the occurrence of an interrupt Software Interrupt 1 0x18
from the peripheral blocks, the PIC block generates an address Software Interrupt 0 0x1C
that points to the corresponding vector address in the DSP vector SPORT1 Transmit (or IRQ1) 0x20
table. The PIC consists of an output register, PICVECTOR, SPORT1 Receive (or IRQ0) 0x24
that contains a pointer to an entry in the DSP vector table. Interval Timer Interrupt 0x28 (Lowest Priority)
During normal operation, an interrupt service routine (ISR)
located at vector address 0x0004 (or the IRQ2/peripheral inter- Interrupt Masking
rupt) jumps to the address pointed to by the PICVECTOR Interrupt masking (or disabling) is controlled by the IMASK
register. The necessary code to perform this jump from address register of the DSP core and the PICMASK register. These
0x0004 is automatically placed there by the internal ROM code registers contain individual bits that must be set to enable the
when MMAP = BMODE = 1. various interrupt sources. It is important to remember that if
any peripheral interrupt is to be enabled both the IRQ2
The vector addresses between 0x00 and 0x2C are reserved
interrupt enable bit (Bit 9) of the IMASK register and the
for the DSP core interrupts. The vector table addresses from
appropriate bit of the PICMASK register must be set. The
PM(0x30) to PM(0x58) are reserved for use by peripheral inter-
rupt service routines. Each vector address occupies four addresses configuration of both the IMASK and PICMASK registers of
the ADMC401 is shown at the end of the data sheet.

–42– REV. B
 ADMC401
Interrupt Configuration Note that this default restores I4 to its value before the inter-
The IFC and ICNTL registers of the DSP core control and rupt. The user should replace the RTI with a JUMP to their
configure the interrupt controller of the DSP core. The IFC ISR. The PUT_VECTOR ROM subroutine can be used to
register is a 16-bit register that may be used to force and/or clear replace the RTI with the JUMP.
any of the eight DSP interrupts. Bits 0 to 7 of the IFC register
The PIC block manages the sequencing of the eleven motor
may be used to clear the DSP interrupts while Bits 8 to 15 can be
control peripheral interrupts. In the case of multiple simulta-
used to force a corresponding interrupt. Writing to Bits 11 and 12
neous interrupts, the PIC will load the PICVECTOR register
in IFC is the only way to create the two software interrupts.
with the vector address of the highest priority pending interrupt.
The ICNTL register is used to configure the sensitivity (edge or The contents of the PICVECTOR register will remain fixed
level) of the IRQ0, IRQ1 and IRQ2 interrupts and to enable/ until read by the DSP. This action is performed by the default
disable interrupt nesting. Setting Bit 0 of ICNTL configures the DSP code at location 0x0004. The PIC block only asserts a
IRQ0 as edge sensitive while clearing the bit configures it for new interrupt after the PICVECTOR register has been read.
level sensitive. Bit 1 is used to configure the IRQ1 interrupt and For other settings of MMAP and BMODE the user must cor-
Bit 2 is used to configure the IRQ2 interrupt. It is recommended rectly configure the vector table.
that the IRQ2 interrupt be always configured for level sensitive
as this ensures that no peripheral interrupts are lost. Setting Bit 4 SYSTEM CONTROLLER
of the ICNTL register enables interrupt nesting. The configura- MODECTRL REGISTER
tion of both IFC and ICNTL registers is shown at the end of The MODECTRL register controls three important features of
the data sheet. the ADMC401. It internally configures the SPORT1 pins for
Interrupt Operation boot loading and UART debugging. Dedicated bits in the
Following a reset (with ROMENABLE = 1), the ROM code MODECTRL register also control the operating mode of the
monitor of the ADMC401 copies a default interrupt vector table PWM generation unit (single or double update mode) and the
into program memory RAM from address 0x0000 to 0x005F. operating mode of the auxiliary PWM generation unit (indepen-
Since each interrupt source has a dedicated four word space in dent or offset mode).
this vector table, it is possible to code short interrupt service Two bits of the MODECTRL register control the internal con-
routines (ISR) in place. Alternatively, it may be required to figuration of the SPORT1 pins as illustrated in Figure 34. Bit 4
insert a JUMP instruction to the appropriate start address of the (DR1SEL) selects which of the two external receive pins (DR1A
interrupt service routine if more memory is required for the ISR. or DR1B) is connected to the internal data receive port of the
On the occurrence of an interrupt, the program sequencer en- DSP core. Clearing Bit 4 selects the DR1A pin, whereas setting
sures that there is no latency (beyond synchronization delay) Bit 4 selects the DR1B pin. Following reset, Bit 4 is cleared so
when processing unmasked interrupts. In the case of the timer, that DR1A is selected.
SPORT0, SPORT1 and software interrupts, the interrupt con-
troller automatically jumps to the appropriate location in the DT1 DT1
interrupt vector table. At this point, a JUMP instruction to the
DR1A
appropriate ISR is required.
DR1
In the event of a motor control peripheral interrupt, the opera-
DR1B
tion is slightly different. For any of the eleven peripheral inter-
rupts, the interrupt controller automatically jumps to location TFS1 TFS1
0x0004 in the interrupt vector table. In addition, the required
vector address (between 0x0030 and 0x0058) associated with DSP CORE
RFS1
the particular interrupt source is placed in the PICVECTOR
register of the PIC block. Code loaded at location 0x0004 by RFS1/SROM

the monitor on reset subsequently performs a JUMP from loca-

tion 0x0004 to the address specified in the PICVECTOR regis- SCLK1 SCLK1
ter. This operation with the PICVECTOR register results in a
slightly longer latency associated with processing any of the
peripheral interrupts, as compared with the latency of the inter- FL1
nal DSP core interrupts.
The code located at location 0x0004 by the monitor on reset is UARTEN DR1SEL
as follows: ADMC401 MODECTRL (5…4)

0x0004: DM (I4_SAVE) = I4;

I4 = DM (PICVECTOR); Figure 34. Internal Multiplexing of SPORT1 Pins
JUMP (I4);
Bit 5 (UARTEN) of the MODECTRL register is used to select
The default code for each of the motor control peripherals is:
between UART and SPORT mode of SPORT1. Setting the
I4 = DM (I4_SAVE); UARTEN bit connects DR1A to the RFS1 input which allows
RTI; SPORT1 to be used as a UART port. Additionally, the internal
FL1 flag of the DSP core is connected to the RFS1/SROM pin
of the ADMC401, to be used as a reset for the external serial

REV. B –43–
ADMC401
ROM or E2PROM. Clearing the UARTEN bit selects SPORT Bit 0 indicates the state of the PWMTRIP pin such that the bit
mode, so that SPORT1 is configured in a manner identical to is set if PWMTRIP is HI and cleared if the pin is LO. Similarly,
the standard serial ports of the ADSP-21xx family. Following Bit 2 indicates the state of the PWMPOL pin such that the bit is
reset, the UARTEN bit is cleared so that SPORT mode is selected. set if PWMPOL is HI (active high PWM selected) and cleared if
the pin is LO (active low PWM selected).
Bit 6 of the MODECTRL register is used to select between
single update and double update operating modes of the PWM Bit 1 is used to indicate if a watchdog timer timeout has oc-
generation unit. Clearing this bit selects single update mode, curred. This bit is set following a watchdog timeout and can be
while setting it selects double update mode. Following reset, read on reset to determine if the reset is a normal power-on
this bit is cleared so that single update mode is the default reset or due to a watchdog trip.
configuration. Bit 3 of the SYSSTAT register is used to identify the half cycle
Bit 8 of the MODECTRL register is used to select between of operation of the PWM generation unit. During the first half
independent and offset operating modes of the auxiliary PWM cycle, when the internal PWM timer is decrementing, this bit is
unit. Clearing this bit selects offset mode, while setting it selects cleared. During the second half cycle, this bit is set while the
independent mode. Following reset, this bit is cleared so that timer is incrementing.
offset mode is the default configuration.
SYSTEM CONTROL REGISTERS
SYSSTAT REGISTER The configuration of the MODECTRL and SYSSTAT register
The SYSSTAT register provides various status information of is shown at the end of the data sheet.
the ADMC401, such as the state of the PWMTRIP pin, the
state of the watchdog flag, the state of the PWMPOL pin and PERIPHERAL AND DSP CORE REGISTERS
phase of the PWM The address, name, type, used bits and reset value of all of the
peripheral registers of the ADMC401 are given in Table VIII.
Similarly, the DSP core registers of the ADMC401 are tabu-
lated in Table IX.

–44– REV. B
 ADMC401
Table VIII. Peripheral Register Map of the ADMC401

Address Name Type Bits Reset Value Function

0x2000–0x2007 Reserved
0x2008 PWMTM R/W [15 . . . 0] 0x0000 PWM Period Register
0x2009 PWMDT R/W [9 . . . 0] 0x0000 PWM Deadtime Register
0x200A PWMPD R/W [9 . . . 0] 0x0000 PWM Pulse Deletion Register
0x200B PWMGATE R/W [9 . . . 0] 0x000 PWM Chopping Control
0x200C PWMCHA R/W [15 . . . 0] 0x0000 PWM Channel A Duty Cycle Control
0x200D PWMCHB R/W [15 . . . 0] 0x0000 PWM Channel B Duty Cycle Control
0x200E PWMCHC R/W [15 . . . 0] 0x0000 PWM Channel C Duty Cycle Control
0x200F PWMSEG R/W [8 . . . 0] 0x000 PWM Crossover and Output Enable
0x2010 AUXCH0 R/W [7 . . . 0] 0x00 Aux. PWM Channel 0 Duty Cycle
0x2011 AUXCH1 R/W [7 . . . 0] 0x00 Aux. PWM Channel 1 Duty Cycle
0x2012 AUXTM0 R/W [7 . . . 0] 0xFF Aux. PWM Channel 0 Period
0x2013 AUXTM1 R/W [7 . . . 0] 0xFF Aux. PWM Channel 1 Period
0x2014 Reserved
0x2015 MODECTRL R/W [8, 6 . . . 4] 0x000 Mode Control Register
0x2016 SYSSTAT R [3 . . . 0] System Status Register
0x2017 Reserved
0x2018 WDTIMER R/W [15 . . . 0] Watchdog Timer Register
0x2019–0x201B Reserved
0x201C PICVECTOR R [15 . . . 0] Peripheral Interrupt Address
0x201D PICMASK R/W [10 . . . 0] 0x000 Peripheral Interrupt Mask Register
0x201E–0x201F Reserved
0x2020 EIUCNT R/W [15 . . . 0] 0x0000 Position Count Value
0x2021 EIUMAXCNT R/W [15 . . . 0] 0x0000 Maximum EIUCNT Value
0x2022 EIUSTAT R [7 . . . 0] EIU Status Register
0x2023 EIUCTRL R/W [8 . . . 0] 0x000 EIU Control Register
0x2024 EIUPERIOD R/W [15 . . . 0] 0x0000 EIU Loop Timer Period Register
0x2025 EIUSCALE R/W [7 . . . 0] 0x00 EIU Loop Timer Scale Register
0x2026 EIUTIMER R/W [15 . . . 0] 0x0000 EIU Loop Timer Register
0x2027 EETCNT R [15 . . . 0] 0x0000 Latched Copy of EIUCNT
0x2028 EIUFILTER R/W [5 . . . 0] 0x00 EIU Filter Control Register
0x2029 EIZLATCH R [15 . . . 0] EIZ Latch Register
0x202A EISLATCH R [15 . . . 0] EIS Latch Register
0x202B–0x202F Reserved
0x2030 ADC0 R [15 . . . 0] ADC0 Data Register
0x2031 ADC1 R [15 . . . 0] ADC1 Data Register
0x2032 ADC2 R [15 . . . 0] ADC2 Data Register
0x2033 ADC3 R [15 . . . 0] ADC3 Data Register
0x2034 ADC4 R [15 . . . 0] ADC4 Data Register
0x2035 ADC5 R [15 . . . 0] ADC5 Data Register
0x2036 ADC6 R [15 . . . 0] ADC6 Data Register
0x2037 ADC7 R [15 . . . 0] ADC7 Data Register
0x2038 ADCCTRL R/W [4 . . . 3,0] 0x00 ADC Control Register
0x2039 ADCSTAT R [4 . . . 0] ADC Status Register
0x203A Reserved
0x203B ADCXTRA R [15 . . . 0] Extra ADC Data Register
0x203C ADCOTR R [7 . . . 0] ADC Out of Range Register
0x203D–0x203F Reserved
0x2040 PIOLEVEL R/W [11 . . . 0] 0x000 PIO Interrupt Select
0x2041 PIOMODE R/W [11 . . . 0] 0x000 PIO Interrupt Edge/Level Select
0x2042 PIOPWM R/W [11 . . . 0] 0xFFF PIO PWMTRIP Enable Register
0x2043 Reserved
0x2044 PIODIR R/W [11 . . . 0] 0x000 PIO Direction Control
0x2045 PIODATA R/W [11 . . . 0] PIO Data Register

REV. B –45–
ADMC401
Address Name Type Bits Reset Value Function
0x2046 PIOINTEN R/W [11 . . . 4] 0x000 PIO Interrupt Enable
0x2047 PIOFLAG R [11 . . . 4] PIO Interrupt Flag (PIO4 to PIO11)
0x2048–0x204F Reserved
0x2050 ETUA0 R [15 . . . 0] Event A Capture–Channel 0
0x2051 ETUB0 R [15 . . . 0] Event B Capture–Channel 0
0x2052 ETUAA0 R [15 . . . 0] Event AA Capture–Channel 0
0x2053 ETUA1 R [15 . . . 0] Event A Capture–Channel 1
0x2054 ETUB1 R [15 . . . 0] Event B Capture–Channel 1
0x2055 ETUAA1 R [15 . . . 0] Event AA Capture–Channel 1
0x2056 ETUTIME R [15 . . . 0] ETU Timer Value
0x2057–0x205B Reserved
0x205C ETUCONFIG R/W [7 . . . 0] 0x00 ETU Configuration Register
0x205D ETUDIVIDE R/W [15 . . . 0] 0x0000 ETU Clock Divide Register
0x205E ETUSTAT R [1 . . . 0] ETU Status Register
0x205F ETUCTRL R/W [1 . . . 0] 0x0 ETU Control Register
0x2060 PWMSYNCWT R/W [7 . . . 0] 0x27 PWMSYNC Width Control
0x2061 PWMSWT R/W [0] 0x0 PWM Software Trip
0x2062–0x206F Reserved
0x2070 EETN R/W [7 . . . 0] 0x00 EET Pulse Decimator Register
0x2071 EETDIV R/W [15 . . . 0] 0x0000 EET Clock Divider Register
0x2072 EETDELTAT R [15 . . . 0] 0x0000 EET Delta Timer Register
0x2073 EETT R [15 . . . 0] 0x0000 EET Timer Period Register
0x2074 EETSTAT R [0] 0x0 EET Status Register
0x2075–0x23FF Reserved

Table IX. DSP Core Register Map of the ADMC401

Address Name Type Bits Function

0x3FFF SYSCNTL R/W [15 . . . 0] System Control Register
0x3FFE MEMWAIT R/W [15 . . . 0] Memory Wait State Control
0x3FFD TPERIOD R/W [15 . . . 0] Interval Timer Period Register
0x3FFC TCOUNT R/W [15 . . . 0 Interval Timer Count Register
0x3FFB TSCALE R/W [7 . . . 0] Interval Timer Scale Register
0x3FFA SPORT0_RX_WORDS1 R/W [15 . . . 0] SPORT0 Mutlichannel Word 1 Receive
0x3FF9 SPORT0_RX_WORDS0 R/W [15 . . . 0] SPORT0 Mutlichannel Word 0 Receive
0x3FF8 SPORT0_TX_WORDS1 R/W [15 . . . 0] SPORT0 Mutlichannel Word 1 Transmit
0x3FF7 SPORT0_TX_WORDS0 R/W [15 . . . 0] SPORT0 Mutlichannel Word 0 Transmit
0x3FF6 SPORT0_CTRL_REG R/W [15 . . . 0] SPORT0 Control Register
0x3FF5 SPORT0_SCLKDIV R/W [15 . . . 0] SPORT0 Clock Divide Register
0x3FF4 SPORT0_RFSDIV R/W [15 . . . 0] SPORT0 Receive Frame Sync Divide
0x3FF3 SPORT0_AUTOBUF_CTRL R/W [15 . . . 0] SPORT0 Autobuffer Control Register
0x3FF2 SPORT1_CTRL_REG R/W [15 . . . 0] SPORT1 Control Register
0x3FF1 SPORT1_SCLKDIV R/W [15 . . . 0] SPORT1 Clock Divide Register
0x3FF0 SPORT1_RFSDIV R/W [15 . . . 0] SPORT1 Receive Frame Sync Divide
0x3FEF SPORT1_AUTOBUF_CTRL R/W [15 . . . 0] SPORT1 Autobuffer Control Register

–46– REV. B
 ADMC401
ADC0 (R)
ADC1 (R)
ADC2 (R)
ADC3 (R)
ADC4 (R)
ADC5 (R)
ADC6 (R)
ADC7 (R)
ADCXTRA(R) DM (0x2030)
DM (0x2031)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2032)
DM (0x2033)
DM (0x2034)
0 0 0 0 DM (0x2035)
DM (0x2036)
DM (0x2037)
DM (0x203B)
ADC DATA

ADCOTR (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 DM (0x203C)

ADC7 OTR ADC0 OTR

ADC6 OTR ADC1 OTR

0 = IN RANGE 0 = IN RANGE
1 = OUT OF RANGE 1 = OUT OF RANGE
ADC5 OTR ADC2 OTR

ADC4 OTR ADC3 OTR

ADCCTRL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2038)

CONVERT 1 = EXTERNAL (CONVST)

START 0 = INTERNAL (PWMSYNC)
00 = SIMULTANEOUS SAMPLING
01 = SEQUENTIAL SAMPLING ADC
10 = OFFSET CALIBRATION MODE
11 = GAIN CALIBRATION

ADCSTAT (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 DM (0x2039)

0 = IN RANGE ADCXTRA OTR ADC0 & ADC4

1 = OUT OF RANGE
ADC1 & ADC5
0 = DATA REGISTERS NOT VALID
ADC2 & ADC6 1 = DATA REGISTERS VALID

ADC3 & ADC7

Figure 35. Structure of Registers of the ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B –47–
ADMC401
PWMCHA (R/W)
PWMCHB (R/W)
PWMCHC (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM (0x200C)
DM (0x200D)
DM (0x200E)

PWMTM (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2008)

PWMDT (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2009)

PWMPD (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x200A)

PWMGATE (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x200B)

1 = ENABLE LOW-SIDE CHOPPING

0 = DISABLE GDCLK
HIGH-SIDE CHOPPING

PWMSEG (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x200F)

AH/AL CROSSOVER CH ENABLE

1 = ENABLE
BH/BL CROSSOVER CL ENABLE
0 = DISABLE

CH/CL CROSSOVER BH ENABLE

1 = DISABLE
0 = ENABLE
BL ENABLE

AH ENABLE

AL ENABLE

PWMSYNCWT (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 DM (0x2060)

PWMSWT (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2061)

Figure 36. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–48– REV. B
 ADMC401
EIUCNT (R/W)
EIUMAXCNT (R/W)
EIUPERIOD (R/W)
EIUTIMER (R/W)
EETCNT (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM (0x2020)
DM (0x2021)
DM (0x2024)
DM (0x2026)
DM (0x2027)

EIUSCALE (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 DM (0x2025)

EIUSTAT (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 DM (0x2022)

1 = RECEIVED EIU COUNT 1 = ERROR

FIRST ZERO MARKER ERROR 0 = NO ERROR
0 = NOT RECEIVED
EIS STATE EIU COUNT 1 = UP
DIRECTION 0 = DOWN
1 = HI EIZ STATE
0 = LO EIU 1 = NOT INITIALIZED
EIB STATE STATE 0 = INITIALIZED
EIA STATE

EIUCTRL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2023)

1 = ZERO MARKER EIS LATCH DIRECTION 1 = SWAP EIA AND EIB

0 = REGISTRATION DEFINITION REVERSE 0 = DO NOT SWAP EIA/EIB

1 = ZERO MARKER EIZ LATCH ZERO 1 = USE FOR RESET

0 = REGISTRATION DEFINITION MARKER 0 = DO NOT USE

1 = ENABLE FREQUENCY & SINGLE NORTH 1 = ENABLE

0 = DISABLE DIRECTION MODE MARKER MODE 0 = DISABLE

1 = ENABLE ENABLE EIU EIU ERROR 1 = ENABLE

0 = DISABLE LOOP TIMER MONITORING 0 = DISABLE
1 = EIUTIMER TIMEOUT EET LATCH
0 = EIUCNT READ DEFINITION

Figure 37. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B –49–
ADMC401
EIUFILTER (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2028)

ENCODER FILTER CLOCK

DIVIDE VALUE

EIZLATCH (R)
EISLATCH (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x2029)
DM (0x202A)

EETDIV (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2071)

EETDELTAT (R)
EETT (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x2072)
DM (0x2073)

EETN (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2070)

EETSTAT(R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2074)

EET 0 = NO OVERFLOW
OVERFLOW 1 = OVERFLOW

Figure 38. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–50– REV. B
 ADMC401

PIOLEVEL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = FALLING EDGE (PIOMODE = 0)
= ACTIVE LOW (PIOMODE = 1)
1 = RISING EDGE (PIOMODE = 0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2040)
= ACTIVE HIGH (PIOMODE = 1)

PIOMODE (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = EDGE SENSITIVE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2041)
1 = LEVEL SENSITIVE

PIOPWM (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = PWM TRIP DISABLE
1 = PWM TRIP ENABLE 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 DM (0x2042)

PIODIR (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = INPUT
1 = OUTPUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2044)

PIODATA (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = LO LEVEL
0 0 0 0 DM (0x2045)
1 = HI LEVEL

PIOINTEN (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = INTERRUPT DISABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 = INTERRUPT ENABLE DM (0x2046)

PIOFLAG (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = NO INTERRUPT 0 0 0 0
1 = INTERRUPT FLAGGED DM (0x2047)

Figure 39. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—
these bits should always be written as shown.
REV. B –51–
ADMC401
ETUA0 (R)
ETUB0 (R)
ETUAA0 (R)
ETUA1 (R)
ETUB1 (R)
ETUAA1 (R)
ETUTIME (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x2050) – DM (0x2056)

ETUCONFIG (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205C)

ETU1 MODE ETU0 EVENT A

0 = SINGLE SHOT 0 = FALLING EDGE
1 = FREE-RUNNING 1 = RISING EDGE
ETU1 INTERRUPT ETU0 EVENT B
0 = NEXT EVENT A 0 = FALLING EDGE
1 = EVENT B 1 = RISING EDGE
ETU1 EVENT B ETU0 INTERRUPT
0 = FALLING EDGE 0 = NEXT EVENT A
1 = RISING EDGE 1 = EVENT B
ETU1 EVENT A ETU1 MODE
0 = FALLING EDGE 0 = SINGLE SHOT
1 = RISING EDGE 1 = FREE-RUNNING

ETUDIVIDE (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205D)

ETUSTAT (R)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205E)

ETU0
0 = NOT CAPTURED
ETU1 1 = SEQUENCE CAPTURE
0 = NOT CAPTURED
1 = SEQUENCE CAPTURED

ETUCTRL (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205E)

ETU0
0 = DO NOT CAPTURE
ETU1 1 = START CAPTURE
0 = DO NOT CAPTURE
1 = START CAPTURE

Figure 40. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–52– REV. B
 ADMC401

AUXCH0 (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2010)

TON, AUX0 = 2
AUXCH0
tCK

AUXCH1 (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2011)

TAUX1 = 2
AUXCH1
tCK

AUXTM0 (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DM (0x2012)

TON, AUX0 = 2
(AUXTM0+1)
tCK

AUXTM1 (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DM (0x2013)

TAUX1 = 2
(AUXTM1+1)
tCK IN INDEPENDENT MODE

TOFFSET = 2
(AUXTM1+1)
tCK IN OFFSET MODE

PICMASK (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = DISABLE INTERRUPT (MASK) DM (0x201D)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 = ENABLE INTERRUPT

PWM TRIP INTERRUPT ADC END OF CONVERSION

PIO3 INTERRUPT PWMSYNC

PIO2 INTERRUPT EIU LOOP TIMER TIMEOUT

PIO1 INTERRUPT PIO4 - PIO11 INTERRUPT

PIO0 INTERRUPT EIU COUNT ERROR INTERRUPT

ETU INTERRUPT

Figure 41. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—
these bits should always be written as shown.
REV. B –53–
ADMC401

MODECTRL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2015)

1 = INDEPENDENT AUXILIARY DATA RECEIVE 1 = DR1B

0 = OFFSET PWM MODE SELECT 0 = DR1A

1 = DOUBLE UPDATE PWM SPORT1 1 = UART MODE

0 = SINGLE UPDATE MODE MODE 0 = SPORT MODE

SYSSTAT (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2016)

PWMTRIP 1 = HI
PIN STATE 0 = LO

1 = SECOND HALF CYCLE PWM PHASE WATCHDOG 1 = WATCHDOG TRIP

0 = FIRST HALF CYCLE FLAG FLAG 0 = NO WATCHDOG TRIP

PWMPOL 1 = HI => ACTIVE HI

PIN STATE 0 = LO => ACTIVE LO

Figure 42. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–54– REV. B
 ADMC401

ICNTL (R/W) IMASK (R/W)

4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 DSP REGISTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP REGISTER

1 = ENABLE, 0 = DISABLE

IRQ0 SENSITIVITY IRQ2 TIMER

1 = EDGE HIP WRITE IRQ0 or SPORT1 RECEIVE
IRQ1 SENSITIVITY
0 = LEVEL HIP READ
IRQ2 SENSITIVITY IRQ1 or SPORT1 TRANSMIT
SPORT0 TRANSMIT SOFTWARE 0
INTERRUPT NESTING SPORT0 RECEIVE SOFTWARE 1
1 = ENABLE, 0 = DISABLE

IFC (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP REGISTER

INTERRUPT FORCE INTERRUPT CLEAR

IRQ2 TIMER
SPORT0 TRANSMIT SPORT1 RECEIVE or IRQ0
SPORT0 RECEIVE SPORT1 TRANSMIT or IRQ1
SOFTWARE1 SOFTWARE 0
SOFTWARE 0 SOFTWARE 1
SPORT1 TRANSMIT OR IRQ1 SPORT0 RECEIVE
SPORT1 RECEIVE OR IRQ0 SPORT0 TRANSMIT
TIMER IRQ2

Figure 43. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B –55–
ADMC401
ASTAT (R/W) SSTAT (R)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 DSP REGISTER 0 1 0 1 0 1 0 1 DSP REGISTER

AZ ALU RESULT ZERO PC STACK EMPTY

AN ALU RESULT NEGATIVE PC STACK OVERFLOW
AV ALU OVERFLOW COUNT STACK EMPTY
AC ALU CARRY COUNT STACK OVERFLOW
AS ALU X INPUT SIGN STATUS STACK EMPTY
AQ ALU QUOTIENT STATUS STACK OVERFLOW
MV MAC OVERFLOW LOOP STACK EMPTY
SS SHIFTER INPUT SIGN LOOP STACK OVERFLOW

MSTAT (R/W)
6 5 4 3 2 1 0

0 0 0 0 0 0 0 DSP REGISTER

DATA REGISTER BANK SELECT

0 = PRIMARY, 1 = SECONDARY
BIT REVERSE MODE ENABLE (DAG1)
ALU OVERFLOW LATCH MODE ENABLE
AR SATURATION MODE ENABLE
MAC RESU PLACEMENT
0 = FRACTIONAL,LT 1 = INTERGER
TIMER ENABLE
GO MODE ENABLE

SYSCNTL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 DM (0x3FFF)

SPORT0 ENABLE
1 = ENABLE, 0 = DISABLED PWAIT
PROGRAM MEMORY
SPORT1 ENABLE WAIT STATES
1 = ENABLE, 0 = DISABLED BWAIT
BOOT WAIT STATES
SPORT1 CONFIGURE BPAGE
1 = SERIAL PORT BOOT PAGE SELECT
0 = FI, FO, IRQ0, IRQ1, SCLK
BFORCE
BOOT FORCE BIT

TPERIOD (R/W)
TCOUNT (R/W)
TSCALE (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FFD)

DM (0x3FFC)

0 0 0 0 0 0 0 0 DM (0x3FFB)

Figure 44 Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–56– REV. B
 ADMC401
MEMWAIT (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM (0x3FFE)

DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAIT0

ROM ENABLE
1 = ENABLE NOTE: IN STANDALONE MODE (MMAP = BMODE = 1)
0 = DISABLE THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER.

SPORT0_RX_WORDS1 (R/W) SPORT0_TX_WORDS1 (R/W)

1 = CHANNEL ENABLE 1 = CHANNEL ENABLE
0 = CHANNEL IGNORED 0 = CHANNEL IGNORED

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DM (0x3FFA) DM (0x3FF8)

SPORT0_RX_WORDS0 (R/W) SPORT0_TX_WORDS0 (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FF9) DM (0x3FF7)

SPORT0_CTRL_REG (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x3FF6)

MULTICHANNEL ENABLE MCE

SLEN SERIAL WORD LENGTH
IINTERNAL SERIAL CLOCK GENERATION ISCLK
DTYPE DATA FORMAT
00 = RIGHT JUSTIFY, ZERO-FILLED UNUSED MSBS
RECEIVE FRAME SYNC REQUIRED RFSR
01 = RIGHT JUSTIFY, SIGN EXTEND INTO UNUSED MSBS
10 = COMPAND USING -LAW
RECEIVE FRAME SYNC WIDTH RFSW 11 = COMPAND USING A-LAW

MULTI CHANNEL FRAME DELAY MFD

INVRFS IINVERT RECEIVE FRAME SYNC
ONLY IF MULTICHANNEL MODE ENABLED)

INVTFS INVERT TRANSMIT FRAME SYNC

TRANSMIT FRAME SYNC REQUIRED TFSR (OR INVTDV INVERT TRANSMIT DATA VALID
ONLY IF MULTICHANNEL MODE ENABLED)
TRANSMIT FRAME SYNC WIDTH TFSW
IRFS INTERNAL RECEIVE FRAME SYNC ENABLE
ITFS INTERNAL TRANSMIT FRAME SYNC ENABLE
(OR MCL MULTICHANNEL LENGTH; 1 = 32 WORDS, 0 = 24 WORDS
ONLY IF MULTICHANNEL MODE ENABLED)

Figure 45. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.

REV. B –57–
ADMC401
SPORT0_SCLKDIV (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FF5)

SPORT0_RFSDIV (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FF4)

SPORT0_AUTOBUF_CTRL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 DM (0x3FF3)

CLKODIS RBUF
CLKOUT DISABLE CONTROL BIT RECEIVE AUTOBUFFERING ENABLE

BIASRND TBUF
MAC BIASED ROUNDING CONTROL BIT TRANSMIT AUTOBUFFERING ENABLE

TIREG RMREG
TRANSMIT AUTOBUFFER I REGISTER RECEIVE AUTOBUFFER M REGISTER

TMREG RIREG
TRANSMIT AUTOBUFFER MREGISTER RECEIVE AUTOBUFFER I REGISTER

Figure 46. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.

–58– REV. B
 ADMC401
SPORT1_SCLKDIV (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FF1)

SPORT1_RFSDIV (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x3FF0)

SPORT1_AUTOBUF_CTRL (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 DM (0x3FEF)

RBUF
RECEIVE AUTOBUFFER ENABLE

TBUF
TRANSMIT AUTOBUFFER ENABLE

RMREG
XTALDELAY RECEIVE M REGISTER
4096 CYCLE DELAY ENABLE
1 = DELAY, 0 = NO DELAY
RIREG
RECEIVE I REGISTER
PDFORCE
POWERDOWN FORCE TMREG
TRANSMIT M REGISTER
PUCR
POWERUP CONTEXT RESET ENABLE TIREG
1 = SOFT RESET (CONTEXT CLEAR), TRANSMIT I REGISTER
0 = RESUME EXECUTION

SPORT1_CTRL_REG (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x3FF2)

FLAG OUT (READ ONLY)

SLEN SERIAL WORD LENGTH
IINTERNAL SERIAL CLOCK GENERATION ISCLK
DTYPE DATA FORMAT
00 = RIGHT JUSTIFY, ZERO-FILLED UNUSED MSBS
RECEIVE FRAME SYNC REQUIRED RFSR
01 = RIGHT JUSTIFY, SIGN EXTEND INTO UNUSED MSBS
10 = COMPAND USING -LAW
RECEIVE FRAME SYNC WIDTH RFSW 11 = COMPAND USING A-LAW

TRANSMIT FRAME SYNC REQUIRED TFSR

TRANSMIT FRAME SYNC WIDTH TFSW INVRFS IINVERT RECEIVE FRAME SYNC

ITFS INTERNAL TRANSMIT FRAME SYNC ENABLE INVTFS INVERT TRANSMIT FRAME SYNC

IRFS INTERNAL RECEIVE FRAME SYNC ENABLE

Figure 47. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.

REV. B –59–
ADMC401
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

144-Lead Plastic Thin Quad Flatpack (LQFP)

ST-144

C3491b–1.5–6/00 (rev. B) 00108

0.063 (1.60)
MAX 0.866 (22.00) BSC SQ
0.030 (0.75) 0.787 (20.00) BSC SQ
0.024 (0.60) 144 109
0.018 (0.45) 1 108

SEATING
PLANE

TOP VIEW
(PINS DOWN)

36 73
0.003 (0.08)
MAX 37 72
0.006 (0.15)
0.002 (0.05) 0.020 (0.50) 0.011 (0.27)
BSC
0.057 (1.45) 0.009 (0.22)
0.053 (1.40) 0.007 (0.17)
0.048 (1.35)

Only dimensions in mm are accurate. The inch equivalents are

approximations rounded to three decimal places.
Only the mm values are recommended for use in PCB layout.

PRINTED IN U.S.A.

–60– REV. B