STATIC TIMING ANALYSIS

Setuptime

It is the minimum amount oftime

for which data should
be stable at the input before the activeedgeof the
clock
Hold Time
Holdtime is the minimum time which the data should
for
be stable at the input at the active edge of the clock
has arrived
Latency

latency is defined as the amount

oftimetaken by the clock
signal in travelling from its source to the sinks
Insertion Delay
to reach the farthest flop is
Time taken
by the clock
known as Max Insertion Delay

Jitter
Clock the deviation
is a clockedge from its ideal
jitter of
position in time
Types
oflatency
ounce latency the time taken
Source latency is defined as

by the clock signal in transversing from clock source

Network Latency Network latency is defined as the time
taken the clock signal in travelling from clock
by
definition point to the sink of the clock

Skew

ositive Skew
If the Capture clock comes late than the
launch clock then it is called the skew

Negative Skew If the Capture clock comes early than launch

clock it is called ve skew
Uncertainty
Check
Uncertainty is the time difference between the arrivals
of clock signals at the registers in one clock domain on
between domains

TUncertainty Skew Jitter t clock Margin Moise Ocu

Types of timing paths

1 Input pin part to Register In Reg

ii Register to Register Reg Reg
iii register to Output past Reg out
Iv Input In out
pin port to outputpinport
v Reg Cas
 Constraints
Setting Input output Delay

Sourcelatency

Create clock period 10 EgetportsA

set clock latency source Max 3 Egetports dKJ

Network latency

set clock latency source max2 Egetparts UK preCTS

set propagated clock getposts AT post cts

Setting Input Delay

Set wiped delay max 0.6 clock Uk getparts A

set output delay max 08 dock UK Egets parts B
 Timing Fines

Setup Hold
i
Upsizing Is Downsizing
Ut swapping Hut Lutlulut Gi UtswappingKut Hut Higheste

Buffer addition Breaking net Cis BufferAddition Near to

us Conning capture flop
e Pin
swapping
vis logic restructing

ImingException
Falsepath
False path refers to a timing path in timing Analysis is
not done on that particularhats it will never get captured
in a limited time frame whenexcited

Set path startpoint to Endpoint

false from
in Multicyclepath
where the
A multicycle path is flop to floppath
combi ational
logic delay in between the flops is permissible to
take more than one clock Cycle
Iii If cycle pa
Timingpath that is designed to take halfclock cycle
both
of the clock edges for the data to propagate from
the startpoint to the end point

Recovery and removal Checks

Is Recovery and removal analysis are done on asynchronoussignals
like resets

Is Recovery time
It is the minimum required time to the neat active edge
after the reset
Removal time
It is the minimum required time after which reset can
be released
G BA and PBA

GBI
In GBA mode the tool computes the path delay based worst
the instances
case timing arcs
of all
A GBA take less runtime as compared to PBA
 PBI
In path based timing analysis the tool considers each path inisolation
other paths which eliminates impossible combination
from of
worst stew and worstarrivals and similar combination
of effects
such as crosstalk and CRPR

As a result path basedtiming analysis reduces pessimism and

increases
accuracy
at the cost
of more runtime

leport timing Primetime Synopsys

Thereporttiming commands
report thetiming paths in the current design
that haveworstslack These are the paths that violate the timing
constraints the large amounts or paths with positive slack that comes
by
closest to causing timing violation
DEach pathhas a startpointand an endpoint Data is launched a
by
clockedge at the path start
point propagatedthrough combinationallogic
in thepath and then captured at the path endpoint another
clock edge The startpoint can be a registerclock pin
by
or an input
post The endpoint can be a register data inputpin or an output
port
command without options reports the
By default thereporttiming single
constraint violation
paths in the design with the worstmaxdelay setup
to consider constraints other than max delay use the delay type
option

To control the numberof paths reported use the nworst option which
specifies the maximum number of worstpaths reported per endpoint

The max paths option whichspecifies overall maximum number paths

of
by
reported the command

IING Reports
To invoke path based analysis use the pbamode option In pathbased
timing analysis the tool path in isolation fromother
considers each

paths
 u

Éo___

oom
 MINIMUM PULSE WIDTH CHECK

aMinimum pulse widthchecks are done to ensure that width ofthe

clock signal is wide enough the cell's internal operation
to i e to
for
stable output you need to ensure
complete
get a
that the clock signal at the clock pin ofthe flop is at least
of certain minimum width

a Minimum pulse width is the interval between the rising edge of

the signal crossing 50 ofUop and the falling edge of the
signal crossing 501of Unis
Command to report Minimum Pulse width violation
report timing check type pulse width
ON CHIP VARIATION

variationwithin a die
is termed as localvariation
 So inside a wafer there is a variation in each dia and
also there is variation in characteristics of transistors even
inside even inside a single IC along with the die

Sof variation

Profess 1 temperature
Voltage

ystematic onSystematic
Ambient Juridion
variations Variations temp Temp
Internal Variation
SupplyVoltage
voltage
variation

ProcessVariation
In processvariation there are two types of variation one is
systematic Variation and other is non systematic Variation

Systematic Variation come due to optical proximity correctioncord

or Mechanical Policing which are predictable
chemical in
nature and can be modeled in PVT Variations

Yon Systematic Variations come from the Random dopant Fluctuation

RDF line Edge Roughness Len or due to oxide thickness variation
highly unpredictable and cannot be
Otu which are modeled
easily
 I
lugs Vin Vds Uaf
Meg
So drain current depends on Tun s mobility
of
electrons

Eon Permittivity ofsiliconoxide

tox oxide thickness
w width transistor
of
gate lenght

To if any of these factors mentioned above varies during

fabrication process It will affect the drain current
going to vary
The
delay of a standard cell is

A photolithography process is a non ideal process and

it is hardto the exact on the silicon
very print layout
wafer

layout 7 pay iffy

actual layout
in Ideal us
condition

So in conclusion there are many factors and high Chances

of variation while
fabrication of a chip and these can
lead the vary the delay of the standard cells
WageVariation
one is due to the variation in external supply voltage and
other is internal Voltage Variation inside the Chip

25 Variations in supply Voltage

variations due to IR drop

The external but

volley variations is taken care in the PvtMethod
there could occur IR drop in your power delivery
which lead to variation in available voltage to operate
a
may
cell

Distance between the power pads andstandard cells could notbe

the same all So there will be variation
standardcells
for
of available Upp for the standard cells depending on the
design Delay of a cell is dependent on the available Upp
Upp is less delay will be more
If
UDD T
t Delay
Temperature Variations
There is ambient temperature on which the Chip is operating
and another temperature is junction temperature of the
transistors junction temperature is the sumof ambient
temperature
plus the temperature raised due to power
dissipation
of Chip
Junction Temperature is
always much greater than the ambient
temperature and the Characteristics
of any transistors majorly
depend on the junction temperature Ambienttemperature
can be taken care in Put but the junction
tempe ature
variations we need to take for
care in our

Sometimes there is also the formation of local hotspots base

on the placement density and power requirements
of cells
which affects the temperature of the junction and
ultimately lead to the variation in current and delayof
cells

Chip ariations
To take care of Ocu we need to addsome pessimism in
the timing of standard cells we basically apply Ix
of additional delay to all standard cells which is
called OCU derate
Ocu berate factors
A fixed derate factor is applied on throughout the design so
in that case any variation occurs will not cause failure of
the Chip But it added too much of timing pessimism
which leads to difficulties in the timing closure especially in the
lower nodes

Set timing derate o g early

set timing donate 1 I late

Issues in OCU
Fixed timing derate is used all the cells in the Ocu is
over pessimistic In reality for
there is cancellation Random
a
of
variation effect

So thelower technology node we want to resolve this issue

for
And so the concept of Advance on chip variation AOU
has involved which does notused the fired denates

In AOCU derate is applied on each cell based on path depth

and distance of the cell in the timing path and it also
varies with cell type anddrivestrength
ofthe cell
box
Distance is
defined by a bounding for netsandcells

D
LF c
Ho Mo r
Distance

y
logicdepth
 g
Distance
If the distance increases systematic variation would

increase and to mitigate the variation we need to use higherderate

value So the distance derate values increases
along with

Pathdepth
In the case of distance is fined andpath depthincreases systemal
variation would be constant but the random variation would tend
to cancel each other Therefore the pathdepthincreases the derate
factor would
decreases

teletypes
The dirate is based on the celltype as an ANDgate and or
gate doesnotexibit thesame variation Derate value also varies
with drive strength of the cell like ANDI and ANDY will have
drive derate values

AOcuderate values depend upon ID 2D look uptables

Depth
I 2 3 4 5 10 50 100
1000 1.099 1.055 1.053
2000 1.099 1.055 1.054

3000 1.100 1.056 1.055

4000 1.102 1057 1.055

EE sooo 1105 1.061 1.059
6000 1.107 1.070 1.06

I 7000 1.109 1.071 16062

IssuesinAo_
AON does not
perform very well below tomm technology node
and to improve that we need to improve the timing
pessimism further Distance and Depth basedderate factor used
in AOCU is good for technology nodes above to nm
but the belownode we need it toimprove it further
for
To address these issues Parametric on ChipVarition Poco

Poco
In Pev instead of applying the specific derate factor to
A cell cell
delay is calculated based on delayvariation
o the cell
of
In Poco it is assumed that the normal delayvalue of a

cell follows the normal distributed curve

central value

it

310 20 20 35
I Y I
7
95
2 995

DOCU
Analysis
Docu uses nominal delayvalues k instead
ofusing the
min or max value of delay to modelthe randomvariations
 using the nominal delay valued
and
Timing Analysis is
A done
delay variation o in thefollowing ways

Tool takes the valueof o from the timing or an

the
library
external Poco coefficient value c
file
containing

Each aretime is then calculated statically asthetotal

the variation
of nominal
delay and
fix the tool then calculates the delayofthepath
by
statistally combiningthese arc delay and perform
setup andhold timing analysis

PInputda
Is using single
POCu coefficient c

An external
file containing the delaycoefficientvalues C for each
heiarchial cell ordesign
library cell
There is only one valueof C for eachtiming arc ofthe
cell irrespective of the input transition or outputload
The cell
delay variation o is calculated based on Cas
follows
The delay variation o Ct Nominaldelay
 Poor Calculations

Delay of a Cell Nominal Delay44 I Powcoefficient T

where C POW Coefficient

N Number
of standard deviation

Prime time POW Analysis flows

Verilog library
SDC Parasitic RC

variation setup
Read POW Input andenable PoW Analysis

Timing Analysis
Subtraction
Apply statiscal Addition min
Max calculation

Generate N Sigma Conner timing reports

stageditayrepart
 Comparison between poor and AOcu

AOCU POCO
Is Random Variation modeled andsystematic variation
Random

through the depth based derate modeled through a delay

and systematic variation is variation coefficient o which is
modeled
through distancebased specific to eachcell
derate

I less accurate co relation More accurate correlation between

between GBA and PBA GrBA andPBA

Iii Transition variation andcell Transition Variation and cell

check variation notsupported check variation is supported in
LVFformat

Numericals
0 2 O 4
D a

I
Launcher
Wtf
µ O3 2 0 4

Tak 2ns Late donate I Ins

Tak q 0.2 ns derate 09ns
Early
Tsetup 0.2ns
T hold O Ins
 Setup Analysis
while calculating the setup Analysis we need to take late
derate along launch
path and early derate along
Capture path
Arrival time
Arrival time includes addition of cells wire delays
along the launch path

Arrival time A T

Wired delay lateiterate Ak to go latederate wire 2delay a

late derate inverter delay Late derate there 3delay
late derate

Arrival time A T o 1 Xl 1 02 11 o2 11 3 1 Dt Coax

Arrival Time A T 4.29nsec

Required time

Required time Rt Tak Tsetup Ewire delays a earlyderate

Tall delays earlydonate
RT 2 0.2 Co 3 x o g 2 10.9 0.4 0.9 4.23ns

Setup Slack RT A T
4.23 4.29
0006 C ve Slack
Holdanalysis
hold analysis we need to take
While calculating the
derates the launch and late derate early
along path along
the Capture path

Arrival time
wire 1 delay early derate tide early
q
derate wire 2delay
derate inverter delay early derate were 3delay
early derate
early
Arrival time 0.1 0.9 0.2 0.9 0.2 0.9 3 0.9
0.4 9 3 51 nseconds

Required time

Required time IR D Thold Twire delays latederate thtcellderate

a late derate

Required Time R T 0.1 to 3 11 2 1.1 0.4 1.1

3 07 nseconds

told Stark AT RT 3.51 3 07

o 44 nseconds tue Slack
Case
2Withonto o 2 o t
p a

ight Ight
m O3 2 0.4

Tak 2ns Late donate I Ins

09ns
Tak q Early date
0.2ns
Tsetup 0.2ns
T hold O Ins

Setup Analysis
AT were 1 talk to a inv delay wire 3
AT O I 0 2 02 3 0 4 3.9nseconds

RT Tax W Tsetup Twire delays Tell delays

RT 2 0.2 0.3 2 0.4 4 5mseconds
Setup Slack RT A T
4.5 39 O G nee

HoldAnalysis
AT were I talk qt inv delay wire 3
A T O 1 0 2 to 2 3 0.4 3.9ns

RT Thold Twindelays Tall delays

RT 0.1 to 3 2 0.4 2 8ns

Hold Slack A T RT
I In seconds
 GRPRICII
RPR Clock Re
convergence
removal Pessimism
CPPR Clock Path pessimism removal

condition arise where have to use

During Timing Analysis a youanother
Max
delay for one timing path and min delay for
timing path

Due to the common path we cannot take Maxdelay mindelay

at the sametime For example common to Data and Clockpath

Removing common clock buffer delay between launch path

capture path is CPPR and CRPR
Numerical

D a D a
delay
Tsetup 0.35ns
FF 5.2ns Ftz
TIM
BE BE
A
Iga M
woop
ihr
ak Thold 0.25ns

Ins 0.86
 Set timing derate early 09
set timing derate late 1.2

Solution
getup slack RT LA
AT 1.2ns to 8 5.2
RT 10 1.2 086 0.35 setup

Setupstalk 11.71 7.2

4.51

Hold Slack LAT RT

A T 1.2ns to 8ns 5.2ns
RT 1.2ns t 086 0.25 Thad

Hold Slack 7.2 2.31

4.89nsec

Derate Value 0.9 1.1

Using PPR and derates
Setup Stalk RT A T

RT Lo 10 86 0.9 0.35 1 1 1.211.1 0.9 PPR

AT II 2 113 008 11 t 52 1.1

Hold Slack A T RT
R'T o 8 11 0.25 1.1 1.2 1.2 0.9 ppr
AT 12 0.9 t 10.8 0.9 5 2 0.9
 Question
why do we need to go with STA if the timing is already
clean in Postroute stage

get accurate valuesof Rand

C
Answer After SPEF generation we
which our Pnr tool was not able to determine and
maybe
maybe degradation in the
due to this RCdelays there
the timing path Hence we static
go for timing Analysis

Signofftools can generate tool based Eco's forthe current existing

violations
ECO EngineeringChangeOrder

Inputs is routedb
Post
SPEF
Kii STA Reports

ECO EngineeringChangeOrder

output is Setup Eco files

td format
in Hold ECO files

inDRy'secofiley
Thiscontainsglitch bumpyWaveform
noise Ecofiles
ECOFlows routedb
new post
Jostroute dis's
SPEF
1ststage
Sta
Reporting W
Reports

Éco
Tempus flow
2nd ECO til files with
Stage
fines
Generating tool
based Elo's Restorepostroutelab Restoringthe dbwithInno
vous
ICcompiler Pnrtool

Delete filter cells

AfterPostrouteoptimizationthefiller
Source Eco cells are added inthedesignThis
files cellsneededtoberemovedfrom
fillerroute
post dbforsourcingtheEcofile
weneedthelegallocations for Legalization
standardcellswhich
wasintroduced
aftersourcingtheEcofiles

gotdisturbedaftersourcingthe
Whatevernets
ecoMaute Ecofiledue toinstancesintroductionthenets
are
routedagainin Ecoroutestage

Addfilter cells

Savictb

Spefgeneration postroutedb
new
 If the tool not able to fix the timing
generated Elo is
then we have to with manualEco's Generally I 2
go
iteration is done with tool Eco still
if degradation intiming
is observed we with manualEco's
go
ManualEco
Manual Ecomean's user have to write the til script to
fire the violations ability to report the timing

Tempus Primetime Tool

Generates Eco files

i size cell cell name Fusion Compiler

in eco update cell instance name celltype Innovous

either source the tech file restoring the

db or
you can by
a

b can do it in the Pnr stage

you
Runtime a Mo of Sienarias
STA Runtime lokpaths are
failing
20hrs aptn
Eso 30 32hrs count
filegeneration a instance

the session I 2hrs

Restoring
PNR Implementation 6 8hr meanwhile we
3days will do PV Checks
I ECO Cycle 2
full