LMC555 CMOS Timer

March 2002

LMC555
CMOS Timer
General Description Features
The LMC555 is a CMOS version of the industry standard n Less than 1 mW typical power dissipation at 5V supply
555 series general purpose timers. In addition to the stan- n 3 MHz astable frequency capability
dard package (SOIC, MSOP, and MDIP) the LMC555 is also n 1.5V supply operating voltage guaranteed
available in a chip sized package (8 Bump micro SMD) using n Output fully compatible with TTL and CMOS logic at 5V
National’s micro SMD package technology. The LMC555 supply
offers the same capability of generating accurate time delays n Tested to −10 mA, +50 mA output current levels
and frequencies as the LM555 but with much lower power
n Reduced supply current spikes during output transitions
dissipation and supply current spikes. When operated as a
one-shot, the time delay is precisely controlled by a single n Extremely low reset, trigger, and threshold currents
external resistor and capacitor. In the stable mode the oscil- n Excellent temperature stability
lation frequency and duty cycle are accurately set by two n Pin-for-pin compatible with 555 series of timers
external resistors and one capacitor. The use of National n Available in 8 pin MSOP Package and 8-Bump micro
Semiconductor’s LMCMOS™ process extends both the fre- SMD package
quency range and low supply capability.

Block and Connection Diagrams

8-Pin SOIC, MSOP,
8-Bump micro SMD
and MDIP Packages

DS008669-1

Top View DS008669-9

Top View
(Bump side down)

Pulse Width Modulator

DS008669-15

DS008669-20

LMCMOS™ is a trademark of National Semiconductor Corp.

© 2002 National Semiconductor Corporation DS008669 [Link]

LMC555
Ordering Information
Package Temperature Range Package Marking Transport Media NSC
Industrial Drawing
−40˚C to +85˚C
8-LeadSmall Outline LMC555CM LMC555CM Rails
M08A
(SO) LMC555CMX LMC555CM 2.5k Units Tape and Reel
8-Lead Mini Small LMC555CMM ZC5 1k Units Tape and Reel
MUA08A
Outline (MSOP) LMC555CMMX ZC5 3.5k Units Tape and Reel
8-Lead Molded Dip LMC555CN LMC555CN Rails
N08E
(MDIP)
8-Bump micro SMD LMC555CBP F1 250 Units Tape and Reel
BPA08EFB
LMC555CBPX F1 3k Units Tape and Reel
micro SMD Demo LMC555CBPEVAL N/A N/A N/A
Board

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 LMC555
Absolute Maximum Ratings (Notes 2, 3) Operating Ratings(Notes 2, 3)
If Military/Aerospace specified devices are required, Termperature Range −40˚C to +85˚C
please contact the National Semiconductor Sales Office/ Thermal Resistance (θJA) (Note 2)
Distributors for availability and specifications.
SO, 8-lead Small Outline 169˚C/W
Supply Voltage, V+ 15V MSOP, 8-lead Mini Small
Input Voltages, VTRIG, VRES, VCTRL, Outline 225˚C/W
VTHRESH −0.3V to VS + 0.3V MDIP, 8-lead Molded Dip 111˚C/W
Output Voltages, VO, VDIS 15V 8-Bump micro SMD 220˚C/W
Output Current IO, IDIS 100 mA Maximum Allowable Power
Storage Temperature Range −65˚C to +150˚C Dissipation @25˚C
Soldering Information MDIP-8 1126mW
MDIP Soldering (10 seconds) 260˚C SO-8 740mW
SOIC, MSOP Vapor Phase (60 MSOP-8 555mW
sec) 215˚C 8 Bump micro SMD 568mW
SOIC, MSOP Infrared (15 sec) 220˚C
Note: See AN-450 “Surface Mounting Methods and Their Effect on Product
Reliability” for other methods of soldering surface mount devices.

Electrical Characteristics (Notes 1, 2)

Test Circuit, T = 25˚C, all switches open, RESET to VS unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

(Limits)
IS Supply Current VS = 1.5V 50 150
VS = 5V 100 250 µA
VS = 12V 150 400
VCTRL Control Voltage VS = 1.5V 0.8 1.0 1.2
VS = 5V 2.9 3.3 3.8 V
VS = 12V 7.4 8.0 8.6
VDIS Discharge Saturation VS = 1.5V, IDIS = 1 mA 75 150
mV
Voltage VS = 5V, IDIS = 10 mA 150 300
VOL Output Voltage (Low) VS = 1.5V, IO = 1 mA 0.2 0.4
VS = 5V, IO = 8 mA 0.3 0.6 V
VS = 12V, IO = 50 mA 1.0 2.0
VOH Output Voltage VS = 1.5V, IO = −0.25 mA 1.0 1.25
(High) VS = 5V, IO = −2 mA 4.4 4.7 V
VS = 12V, IO = −10 mA 10.5 11.3
VTRIG Trigger Voltage VS = 1.5V 0.4 0.5 0.6
V
VS = 12V 3.7 4.0 4.3
ITRIG Trigger Current VS = 5V 10 pA
VRES Reset Voltage VS = 1.5V (Note 4) 0.4 0.7 1.0
V
VS = 12V 0.4 0.75 1.1
IRES Reset Current VS = 5V 10 pA
ITHRESH Threshold Current VS = 5V 10 pA
IDIS Discharge Leakage VS = 12V 1.0 100 nA
t Timing Accuracy SW 2, 4 Closed
VS = 1.5V 0.9 1.1 1.25
ms
VS = 5V 1.0 1.1 1.20
VS = 12V 1.0 1.1 1.25
∆t/∆VS Timing Shift with Supply VS = 5V ± 1V 0.3 %/V
∆t/∆T Timing Shift with VS = 5V 75 ppm/˚C
Temperature −40˚C ≤ T ≤ +85˚C
fA Astable Frequency SW 1, 3 Closed, VS = 12V 4.0 4.8 5.6 kHz
fMAX Maximum Frequency Max. Freq. Test Circuit, VS = 5V 3.0 MHz
tR, tF Output Rise and Max. Freq. Test Circuit 15 ns
Fall Times VS = 5V, CL = 10 pF

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Electrical Characteristics (Notes 1, 2)
Test Circuit, T = 25˚C, all switches open, RESET to VS unless otherwise noted (Continued)

Symbol Parameter Conditions Min Typ Max Units

(Limits)
tPD Trigger Propagation Delay VS = 5V, Measure Delay
100 ns
from Trigger to Output
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: See AN-450 for other methods of soldering surface mount devices, and also AN-1112 for micro SMD considerations.
Note 4: If the RESET pin is to be used at temperatures of −20˚C and below VS is required to be 2.0V or greater.
Note 5: For device pinout please refer to table 1

Test Circuit (Note 5) Maximum Frequency Test Circuit (Note 5)

DS008669-3
DS008669-2

TABLE 1. Package Pinout Names vs. Pin Function

Pin Function Package Pin numbers
8-Pin SO,MSOP, and MDIP 8-Bump micro SMD
GND 1 A3
Trigger 2 B3
Output 3 C3
Reset 4 C2
Control Voltage 5 C1
Threshold 6 B1
Discharge 7 A1
+
V 8 A2

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 LMC555
Application Info When the reset function is not use, it is recommended that it
be connected to V+ to avoid any possibility of false triggering.
MONOSTABLE OPERATION Figure 3 is a nomograph for easy determination of RC values
In this mode of operation, the timer functions as a one-shot for various time delays.
(Figure 1). The external capacitor is initially held discharged Note: In monstable operation, the trigger should be driven high before the
by internal circuitry. Upon application of a negative trigger end of timing cycle.
pulse of less than 1/3 VS to the Trigger terminal, the flip-flop
is set which both releases the short circuit across the capaci-
tor and drives the output high.

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FIGURE 3. Time Delay

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FIGURE 1. Monostable (One-Shot) ASTABLE OPERATION

If the circuit is connected as shown in Figure 4 (Trigger and
The voltage across the capacitor then increases exponen-
Threshold terminals connected together) it will trigger itself
tially for a period of tH = 1.1 RAC, which is also the time that
and free run as a multivibrator. The external capacitor
the output stays high, at the end of which time the voltage
charges through RA + RB and discharges through RB. Thus
equals 2/3 VS. The comparator then resets the flip-flop which
the duty cycle may be precisely set by the ratio of these two
in turn discharges the capacitor and drives the output to its
resistors.
low state. Figure 2 shows the waveforms generated in this
mode of operation. Since the charge and the threshold level
of the comparator are both directly proportional to supply
voltage, the timing internal is independent of supply.

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DS008669-10
FIGURE 4. Astable (Variable Duty Cycle Oscillator)
VCC = 5V Top Trace: Input 5V/Div.
TIME = 0.1 ms/Div. Middle Trace: Output 5V/Div. In this mode of operation, the capacitor charges and dis-
RA = 9.1kΩ Bottom Trace: Capacitor Voltage 2V/Div.
charges between 1/3 VS and 2/3 VS. As in the triggered
C = 0.01µF
mode, the charge and discharge times, and therefore the
FIGURE 2. Monostable Waveforms frequency are independent of the supply voltage.
Figure 5 shows the waveform generated in this mode of
Reset overrides Trigger, which can override threshold.
operation.
Therefore the trigger pulse must be shorter than the desired
tH. The minimum pulse width for the Trigger is 20ns, and it is
400ns for the Reset. During the timing cycle when the output
is high, the further application of a trigger pulse will not effect
the circuit so long as the trigger input is returned high at least
10µs before the end of the timing interval. However the
circuit can be reset during this time by the application of a
negative pulse to the reset terminal. The output will then
remain in the low state until a trigger pulse is again applied.

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Application Info (Continued)

DS008669-14

VCC = 5V Top Trace: Input 4V/Div.

DS008669-12 TIME = 20 µs/Div. Middle Trace: Output 2V/Div.
VCC = 5V Top Trace: Output 5V/Div. RA = 9.1 kΩ Bottom Trace: Capacitor 2V/Div.
TIME = 20 µs/Div. Bottom Trace: Capacitor Voltage 1V/Div. C = 0.01µF
RA = 3.9kΩ FIGURE 7. Frequency Divider Waveforms
RB = 9kΩ
C = 0.01µF
PULSE WIDTH MODULATOR
FIGURE 5. Astable Waveforms When the timer is connected in the monostable mode and
The charge time (output high) is given by triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to the Control
t1 = Ln2 (RA + RB)C Voltage Terminal. Figure 8 shows the circuit, and in Figure 9
And the discharge time (output low) by: are some waveform examples.
t2 = Ln2 (RB)C
Thus the total period is:
T = t1 + t2 = Ln2 (RA + RB)C
The frequency of oscillation is:

Figure 6 may be used for quick determination of these RC

Values. The duty cycle, as a fraction of total period that the
output is low, is:

DS008669-20

FIGURE 8. Pulse Width Modulator

DS008669-13
DS008669-15
FIGURE 6. Free Running Frequency VCC = 5V Top Trace: Modulation 1V/Div.
TIME = 0.2 ms/Div. Bottom Trace: Output Voltage 2V/Div.
FREQUENCY DIVIDER RA = 9.1 kΩ
The monostable circuit of Figure 1 can be used as a fre- C = 0.01µF
quency divider by adjusting the length of the timing cycle. FIGURE 9. Pulse Width Modulator Waveforms
Figure 7 shows the waveforms generated in a divide by three
circuit. PULSE POSITION MODULATOR
This application uses the timer connected for astable opera-
tion, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies with

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 LMC555
Application Info (Continued) 50% DUTY CYCLE OSCILLATOR
The frequency of oscillation is
the modulating signal, since the threshold voltage and hence
f = 1/(1.4 RCC)
the time delay is varied. Figure 11 shows the waveforms
generated for a triangle wave modulation signal.

DS008669-21

FIGURE 10. Pulse Position Modulator

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FIGURE 12. 50% Duty Cycle Oscillator

micro SMD Marking Orientation

Top View

DS008669-16

VCC = 5V Top Trace: Modulation Input 1V/Div.

TIME = 0.1 ms/Div. Bottom Trace: Output Voltage 2V/Div.
RA = 3.9 kΩ
RB = 3 kΩ
C = 0.01µF
DS008669-23
FIGURE 11. Pulse Position Modulator Waveforms
Bumps are numbered counter-clockwise

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Physical Dimensions inches (millimeters) unless otherwise noted

Molded Small Outline (SO) Package (M)

NS Package Number M08A

8-Lead (0.118” Wide) Molded Mini Small Outline Package

NS Package Number MUA08A

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 LMC555
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-in-line Package (N)

NS Package Number N08E

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LMC555 CMOS Timer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

NOTES: UNLESS OTHERWISE SPECIFIED

1. EPOXY COATING
2. 63Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE
NUMBERED COUNTERCLOCKWISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS
PACKAGE LENGTH AND X3 IS PACKAGE HEIGHT.
6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC.
micro SMD Package
NS Package Number BPA08EFB
X1 = 1.387 X2 = 1.412 X3 = 0.850

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