PCA9540B

2-channel I2C-bus multiplexer

Rev. 5 — 12 February 2013 Product data sheet

1. General description
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.
The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register.

A power-on reset function puts the registers in their default state and initializes the I2C-bus
state machine with no channels selected.

The pass gates of the multiplexer are constructed such that the VDD pin can be used to
limit the maximum high voltage that will be passed by the PCA9540B. This allows the use
of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
can pull the bus up to the desired voltage level for this channel. All I/O pins are 5 V
tolerant.

2. Features and benefits

 1-of-2 bidirectional translating multiplexer
 I2C-bus interface logic; compatible with SMBus standards
 Channel selection via I2C-bus
 Power up with all multiplexer channels deselected
 Low Ron switches
 Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
 No glitch on power-up
 Supports hot insertion
 Low standby current
 Operating power supply voltage range of 2.3 V to 5.5 V
 5 V tolerant inputs
 0 Hz to 400 kHz clock frequency
 ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: SO8, TSSOP8, XSON8U
NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

3. Ordering information
Table 1. Ordering information
Type number Topside Package
marking Name Description Version
PCA9540BD PA9540B SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9540BDP 9540B TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9540BGD 40B XSON8U plastic extremely thin small outline package; no leads; 8 terminals; SOT996-2
UTLP based; body 3  2  0.5 mm

3.1 Ordering options

Table 2. Ordering options
Type number Orderable Package Packing method Minimum Temperature range
part number order quantity
PCA9540BD PCA9540BD,112 SO8 Tube, bulk pack 2000 Tamb = 40 C to +85 C
PCA9540BD,118 SO8 Reel pack, SMD, 13-inch 2500 Tamb = 40 C to +85 C
PCA9540BDP PCA9540BDP,118 TSSOP8 Reel pack, SMD, 13-inch 2500 Tamb = 40 C to +85 C
PCA9540BDP/DG,118 TSSOP8 Reel pack, SMD, 13-inch 2500 Tamb = 40 C to +85 C
PCA9540BGD PCA9540BGD,125 XSON8U Reel pack, reverse 3000 Tamb = 40 C to +85 C

4. Block diagram

PCA9540B
SD0

SD1

SC0

SC1

VSS SWITCH CONTROL LOGIC

VDD POWER-ON
RESET

SCL
INPUT
FILTER I2C-BUS
SDA CONTROL

002aae715

Fig 1. Block diagram of PCA9540B

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Product data sheet Rev. 5 — 12 February 2013 2 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

5. Pinning information

5.1 Pinning

SCL 1 8 SC1
SCL 1 8 SC1
SDA 2 7 SD1
SDA 2 7 SD1
PCA9540BD PCA9540BDP
VDD 3 6 VSS VDD 3 6 VSS

SD0 4 5 SC0 SD0 4 5 SC0

002aae713 002aae714

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

SCL 1 8 SC1

SDA 2 7 SD1
PCA9540BGD
VDD 3 6 VSS

SD0 4 5 SC0

002aae753

Transparent top view

Fig 4. Pin configuration for XSON8U

5.2 Pin description

Table 3. Pin description
Symbol Pin Description
SCL 1 serial clock line
SDA 2 serial data line
VDD 3 supply voltage
SD0 4 serial data 0
SC0 5 serial clock 0
VSS 6 supply ground
SD1 7 serial data 1
SC1 8 serial clock 1

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Product data sheet Rev. 5 — 12 February 2013 3 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

6. Functional description
Refer to Figure 1 “Block diagram of PCA9540B”.

6.1 Device addressing

Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9540B is shown in Figure 5.

slave address

1 1 1 0 0 0 0 R/W

fixed
002aae716

Fig 5. Slave address

The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9540B which will be stored in the Control register. If multiple bytes are
received by the PCA9540B, it will save the last byte received. This register can be written
and read via the I2C-bus.

channel selection bits

(read/write)
7 6 5 4 3 2 1 0

X X X X X B2 B1 B0
002aae717
enable bit

Fig 6. Control register

6.2.1 Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the Control
register. This register is written after the PCA9540B has been addressed. The 2 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, it will become active after a STOP condition has been placed on the I2C-bus.
This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of connection.

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Product data sheet Rev. 5 — 12 February 2013 4 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

Table 4. Control register: Write — channel selection; Read — channel status

D7 D6 D5 D4 D3 B2 B1 B0 Command
X X X X X 0 X X no channel selected
X X X X X 1 0 0 channel 0 enabled
X X X X X 1 0 1 channel 1 enabled
X X X X X 1 1 X no channel selected
0 0 0 0 0 0 0 0 no channel selected;
power-up default state

6.3 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9540B in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9540B registers and I2C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.

6.4 Voltage translation

The pass gate transistors of the PCA9540B are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.

002aaa964
5.0

Vo(sw)
(V)

4.0
(1)

(2)
3.0
(3)

2.0

1.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage

Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this
data sheet). In order for the PCA9540B to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at

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Product data sheet Rev. 5 — 12 February 2013 5 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9540B supply voltage is
3.5 V or lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors
can then be used to bring the bus voltages to their appropriate levels (see Figure 14).

More Information can be found in application note AN262, “PCA954X family of I2C/SMBus
multiplexers and switches”.

7. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).

SDA

SCL

data line change

stable; of data
data valid allowed mba607

Fig 8. Bit transfer

7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).

SDA

SCL
S P

START condition STOP condition

mba608

Fig 9. Definition of START and STOP conditions

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Product data sheet Rev. 5 — 12 February 2013 6 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

7.3 System configuration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).

SDA
SCL

MASTER SLAVE MASTER

SLAVE MASTER I2C-BUS
TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/
MULTIPLEXER
RECEIVER RECEIVER RECEIVER

SLAVE

002aaa966

Fig 10. System configuration

7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.

data output
by transmitter
not acknowledge

data output
by receiver
acknowledge

SCL from master 1 2 8 9

S
clock pulse for
START acknowledgement
condition 002aaa987

Fig 11. Acknowledgement on the I2C-bus

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NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

7.5 Bus transactions

slave address control register

SDA S 1 1 1 0 0 0 0 0 A X X X X X B2 B1 B0 A P

START condition R/W acknowledge acknowledge

from slave from slave
STOP condition

002aae719

Fig 12. Write control register

last byte
slave address control register

SDA S 1 1 1 0 0 0 0 1 A X X X X X B2 B1 B0 NA P

START condition R/W acknowledge no acknowledge

from slave from master
STOP condition
002aae720

Fig 13. Read control register

8. Application design-in information

VDD = 2.7 V to 5.5 V

VDD = 3.3 V
V = 2.7 V to 5.5 V

SDA SDA SD0

channel 0
SCL SCL SC0

V = 2.7 V to 5.5 V
PCA9540B
I2C-bus/SMBus master
SD1
channel 1
SC1
VSS

002aae721

Fig 14. Typical application

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NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

9. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to ground (VSS = 0 V).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +7.0 V
VI input voltage 0.5 +7.0 V
II input current - 20 mA
IO output current - 25 mA
IDD supply current - 100 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature 60 +150 C
Tamb ambient temperature operating 40 +85 C
Tj(max) maximum junction [1] - 125 C
temperature

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.

10. Thermal characteristics

Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction SO8 package 158 C/W
to ambient TSSOP8 package 120 C/W

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2-channel I2C-bus multiplexer

11. Static characteristics

Table 7. Static characteristics at VDD = 2.3 V to 3.6 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
See Table 8 for VDD = 3.6 V to 5.5 V.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 2.3 - 3.6 V
IDD supply current operating mode; VDD = 3.6 V; - 20 50 A
no load; VI = VDD or VSS;
fSCL = 100 kHz
Istb standby current standby mode; VDD = 3.6 V; - 0.1 1 A
no load; VI = VDD or VSS;
fSCL = 0 kHz
VPOR power-on reset voltage no load; VI = VDD or VSS [1] - 1.6 2.1 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 6 V
IOL LOW-level output current VOL = 0.4 V 3 - - mA
VOL = 0.6 V 6 - - mA
IL leakage current VI = VDD or VSS 1 - +1 A
Ci input capacitance VI = VSS - 7 8 pF
Pass gate
Ron ON-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; 5 11 31 
IO = 15 mA
VDD = 2.3 V to 2.7 V; VO = 0.4 V; 7 16 55 
IO = 10 mA
Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A - 1.9 - V
Vi(sw) = VDD = 3.0 V to 3.6 V; 1.6 - 2.8 V
Io(sw) = 100 A
Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A - 1.5 - V
Vi(sw) = VDD = 2.3 V to 2.7 V; 1.1 - 2.0 V
Io(sw) = 100 A
IL leakage current VI = VDD or VSS 1 - +1 A
Cio input/output capacitance VI = VSS - 2.5 5 pF

[1] VDD must be lowered to 0.2 V in order to reset part.

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2-channel I2C-bus multiplexer

Table 8. Static characteristics at VDD = 3.6 V to 5.5 V

VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
See Table 7 for VDD = 2.3 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 3.6 - 5.5 V
IDD supply current operating mode; VDD = 5.5 V; - 65 100 A
no load; VI = VDD or VSS;
fSCL = 100 kHz
Istb standby current standby mode; VDD = 5.5 V; - 0.3 1 A
no load; VI = VDD or VSS
VPOR power-on reset voltage no load; VI = VDD or VSS [1] - 1.6 2.1 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 6 V
IOL LOW-level output current VOL = 0.4 V 3 - - mA
VOL = 0.6 V 6 - - mA
IIL LOW-level input current VI = VSS 1 - +1 A
IIH HIGH-level input current VI = VDD 1 - +1 A
Ci input capacitance VI = VSS - 6 8 pF
Pass gate
Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; 4 9 24 
IO = 15 mA
Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A - 3.6 - V
Vi(sw) = VDD = 4.5 V to 5.5 V; 2.6 - 4.5 V
Io(sw) = 100 A
IL leakage current VI = VDD or VSS 1 - +1 A
Cio input/output capacitance VI = VSS - 2.5 5 pF

[1] VDD must be lowered to 0.2 V in order to reset part.

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2-channel I2C-bus multiplexer

12. Dynamic characteristics

Table 9. Dynamic characteristics
Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Unit
I2C-bus
Min Max Min Max
tPD propagation delay from SDA to SDx, - 0.3[1] - 0.3[1] ns
or SCL to SCx
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and 4.7 - 1.3 - s
START condition
tHD;STA hold time (repeated) START [2] 4.0 - 0.6 - s
condition
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START 4.7 - 0.6 - s
condition
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s
tSU;DAT data set-up time 250 - 100 - ns
tr rise time of both SDA and SCL - 1000 20 + 0.1Cb[4] 300 ns
signals
tf fall time of both SDA and SCL - 300 20 + 0.1Cb[4] 300 ns
signals
Cb capacitive load for each bus line - 400 - 400 pF
tSP pulse width of spikes that must be - 50 - 50 ns
suppressed by the input filter
tVD;DAT data valid time HIGH-to-LOW [5] - 1 - 1 s
LOW-to-HIGH [5] - 0.6 - 0.6 s
tVD;ACK data valid acknowledge time - 1 - 1 s

[1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.

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NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

0.7 × VDD
SDA
0.3 × VDD

tBUF tr tf tHD;STA tSP

tLOW

0.7 × VDD
SCL 0.3 × VDD

tHD;STA tSU;STA tSU;STO

P S tHD;DAT tHIGH tSU;DAT Sr P
002aaa986

Fig 15. Definition of timing on the I2C-bus

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2-channel I2C-bus multiplexer

13. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

D E A
X

y HE v M A

8 5

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 4 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ

0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 4.8 3.8 5.8 0.4 0.6 0.3 8o
o
0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012

Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT96-1 076E03 MS-012
03-02-18

Fig 16. Package outline SOT96-1 (SO8)

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Product data sheet Rev. 5 — 12 February 2013 14 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

D E A
X

y HE v M A

8 5

A2 (A3) A
A1
pin 1 index

θ
Lp
L
1 4
detail X
e w M
bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A D(1)
UNIT A1 A2 A3 bp c E(2) e HE L Lp v w y Z(1) θ
max.
0.15 0.95 0.45 0.28 3.1 3.1 5.1 0.7 0.70 6°
mm 1.1 0.25 0.65 0.94 0.1 0.1 0.1
0.05 0.80 0.25 0.15 2.9 2.9 4.7 0.4 0.35 0°

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-04-09
SOT505-1
03-02-18

Fig 17. Package outline SOT505-1 (TSSOP8)

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Product data sheet Rev. 5 — 12 February 2013 15 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

XSON8: plastic extremely thin small outline package; no leads;

8 terminals; body 3 x 2 x 0.5 mm SOT996-2

D B A

E A A1

detail X

terminal 1
index area

e1
C
v C A B
L1 e b
w C y1 C y
1 4

L2

8 5
X

0 1 2 mm
scale

Dimensions (mm are the original dimensions)

Unit(1) A A1 b D E e e1 L L1 L2 v w y y1

max 0.05 0.35 2.1 3.1 0.5 0.15 0.6

mm nom 0.5 0.5 1.5 0.1 0.05 0.05 0.1
min 0.00 0.15 1.9 2.9 0.3 0.05 0.4
sot996-2_po

Outline References European

Issue date
version IEC JEDEC JEITA projection
07-12-21
SOT996-2
12-11-20

Fig 18. Package outline SOT996-2 (XSON8U)

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Product data sheet Rev. 5 — 12 February 2013 16 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.

14.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

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2-channel I2C-bus multiplexer

14.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350  350
< 2.5 235 220
 2.5 220 220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.

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2-channel I2C-bus multiplexer

maximum peak temperature

temperature = MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

peak
temperature

time
001aac844

MSL: Moisture Sensitivity Level

Fig 19. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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2-channel I2C-bus multiplexer

15. Soldering: PCB footprints

5.50

0.60 (8×)

1.30

4.00 6.60 7.00

1.27 (6×)

solder lands
occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr

Fig 20. PCB footprint for SOT96-1 (SO8); reflow soldering

1.20 (2×)

0.60 (6×) 0.3 (2×) enlarged solder land

1.30

4.00 6.60 7.00

1.27 (6×)

5.50
board direction

solder lands solder resist

occupied area placement accurracy ± 0.25 Dimensions in mm sot096-1_fw

Fig 21. PCB footprint for SOT96-1 (SO8); wave soldering

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Product data sheet Rev. 5 — 12 February 2013 20 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

3.600
2.950
0.725 0.125

0.125

5.750 3.600 3.200 5.500

1.150

0.600 0.450
0.650

solder lands occupied area Dimensions in mm sot505-1_fr

Fig 22. PCB footprint for SOT505-1 (TSSOP8); reflow soldering

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Product data sheet Rev. 5 — 12 February 2013 21 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

2.400 pa + oa

2.000

0.500 0.500

0.250 0.025

0.025

3.400
4.250 2.000 4.000
pa + oa

0.900

solder lands placement area Dimensions in mm

solder paste occupied area sot996-2_fr

Fig 23. PCB footprint for SOT996-2 (XSON8U); reflow soldering

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Product data sheet Rev. 5 — 12 February 2013 22 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

16. Abbreviations
Table 12. Abbreviations
Acronym Description
CDM Charged-Device Model
ESD ElectroStatic Discharge
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
I/O Input/Output
IC Integrated Circuit
LSB Least Significant Bit
POR Power-On Reset
SMBus System Management Bus

17. Revision history

Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9540B v.5 20130212 Product data sheet - PCA9540B v.4
Modifications: • Section 2 “Features and benefits”, 13th bullet item: deleted phrase “200 V MM per JESD2-A115”
• Added Section 3.1 “Ordering options”
• Table 5 “Limiting values”: added Tj(max) limits
• Added Section 10 “Thermal characteristics”
• Figure 15 “Definition of timing on the I2C-bus” modified: added 0.3  VDD and 0.7  VDD reference
lines
• Added Section 15 “Soldering: PCB footprints”
PCA9540B v.4 20090903 Product data sheet - PCA9540B v.3
PCA9540B v.3 20090528 Product data sheet - PCA9540B v.2
PCA9540B v.2 20040929 Product data sheet - PCA9540B v.1
(9397 750 13731)
PCA9540B v.1 20040413 Product data - -
(9397 750 12918)

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2-channel I2C-bus multiplexer

18. Legal information

18.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL [Link]

18.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
18.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at [Link] unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

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Product data sheet Rev. 5 — 12 February 2013 24 of 26

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2-channel I2C-bus multiplexer

Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any
may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and
authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for
the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy
in accordance with automotive testing or application requirements. NXP between the translated and English versions.
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in 18.4 Trademarks
automotive applications to automotive specifications and standards, customer
Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
are the property of their respective owners.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP B.V.
NXP Semiconductors’ specifications such use shall be solely at customer’s

19. Contact information

For more information, please visit: [Link]
For sales office addresses, please send an email to: salesaddresses@[Link]

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Product data sheet Rev. 5 — 12 February 2013 25 of 26

NXP Semiconductors PCA9540B
2-channel I2C-bus multiplexer

20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2.1 Control register definition . . . . . . . . . . . . . . . . . 4
6.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.4 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 5
7 Characteristics of the I2C-bus . . . . . . . . . . . . . 6
7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.2 START and STOP conditions . . . . . . . . . . . . . . 6
7.3 System configuration . . . . . . . . . . . . . . . . . . . . 7
7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.5 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Application design-in information . . . . . . . . . . 8
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
10 Thermal characteristics . . . . . . . . . . . . . . . . . . 9
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 10
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Soldering of SMD packages . . . . . . . . . . . . . . 17
14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 17
14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 17
14.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
14.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 20
16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
19 Contact information. . . . . . . . . . . . . . . . . . . . . 25
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2013. All rights reserved.

For more information, please visit: [Link]
For sales office addresses, please send an email to: salesaddresses@[Link]
Date of release: 12 February 2013
Document identifier: PCA9540B