A Fault-Tolerant Hybrid Cascaded H-Bridge

Multilevel Inverter
Haider Mhiesan, Student Member, IEEE, Yuqi Wei, Student Member, IEEE, Yam P. Siwakoti , Senior Member,
IEEE, and H. Alan Mantooth, Fellow, IEEE

Abstract- The cascaded H-bridge (CHB) inverter is one of the application, the system can survive for several periods, and a
most attractive multilevel topologies for renewable energy basic controller can reduce the voltage of the healthy phases as
applications. Due to the fact that CHB inverters employ a large well. Reducing the voltage level in a motor drive application
number of components, they suffer from a higher probability of does not damage the motor. However, in the case of a grid-tied
fault, which reduce the system reliability. Fault-tolerant operation
for a CHB inverter is described in this paper. New features ensure
multilevel inverter, losing one voltage level results in an
reliable and robust operation of the converter in the event of a unbalanced output voltage, which subsequently can shut down
fault. The proposed strategy uses an additional cross-coupled CHB the overall system.
(X-CHB) unit in companion with the existing CHB units to support For a BESS using CHB, the battery cells are connected in
the output voltage and ensure continuity of operation in the event parallel and series, forming battery packs, to reach the desired
of an open/short circuit fault. The operation of the proposed X- voltage, current, and energy (watt-hours). The main reasons for
CHB inverter is described in detail. Simulation and experimental failure in battery packs are overcharging, overheating, and other
verification of the proposed concept are demonstrated using a short-circuit events [13]. The series connection of battery cells
seven-level CHB. Both simulation and experimental results results in the lowering of system reliability. That is, a fault in a
confirm the fault-tolerant operation of the X-CHB for a battery
energy storage system (BESS) in case of switch faults.
single battery cell results in a failure in the entire battery pack.
In other words, the failure of a battery pack can lead to failure
I. INTRODUCTION in the entire system [14]-[15]. Each cell in a series string sees
the same current passing through. Weak cells can have elevated
Nowadays multilevel topologies are considered a promising internal resistances even in a full state of charge. This results in
technology for integrating renewable and clean energy blocking other batteries from continuing reduced ability to
resources, such as battery energy storage systems (BESS), solar supply the power [16]. In addition, during the charging mode of
photovoltaics and wind turbine generators to the electric power the batteries, the weakest cell with the lowest capacity can be
grid. The reasons behind the rapid adoption of the multilevel inadvertently overcharged, possibly leading to gas generation
converters are due to improved output power quality, and explosion. In other words, in a series string of battery cells,
scalable/modular configuration, and the possibility of the weakest cell with the lowest capacity reaches its full state of
implementing lower voltage rated components. Several charge before the rest of the battery cells, and that results in
multilevel topologies have been published in the quest for overcharging and overheating [17]-[18]. Battery cell short-
making the system cost-effective, reliable and less complex in circuits can be classified into external and internal short-circuit
control from both the hardware and software perspectives. faults. The external short-circuit results from abnormal heat and
Among them, the major multilevel topologies are: Modular high heat results in short-circuit faults. Internal short-circuits
Multilevel Converter (MMC), Flying Capacitor (FC), Cascaded are caused by either manufacturing defects or mechanical
H-Bridge (CHB), and Neutral Point Clamped (NPC) inverters failure [13], [19]-[20].
[1]-[5]. Even though these are very different types of multilevel Another possible failure in the power supply in CHB for
topologies, they share the same issue of reliability related to the BESS is due to a failed and internally short-circuited dc-link
probability of semiconductor device failures [6]-[9]. capacitor. It is worth mentioning that the proposed topology
In other words, reliability is a major concern among cannot handle this capacitor failure mode, and so shuts down
conventional multilevel topologies due to the higher number of the system.
switches and associated driving circuitry. In cases of In summary, prior fault diagnosis and mitigation methods fall
open/short-circuit faults, the multilevel output voltage becomes into one of two categories. The first is to detect and isolate a
distorted, which results in malfunction of the inverter that may faulty cell. However, isolation of one cell results in reduced
propagate downstream to the grid and cause subsequent failures functionality and degraded operation as in [21]. The structures
of the electrical grid [10]- [12]. in [22]-[23] use a strategy of bypassing the faulty cell when
The degree of switch failure is also different depending on faults occur. Then, the strategy is to bypass two more cells in
the circuit topology and application. For instance, in the case of the other phases, which results in an inverter working with
open-circuit faults in CHB, one voltage level is skipped in that fewer voltage levels (losing two voltage levels). In other words,
particular phase; however, the other two phases continue it ensures the output voltage when a fault happens is the same
generating the same output voltage. In the case of a motor drive as before the fault occurs but with less voltage levels.

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IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

This is possible by boosting the voltage in each healthy H- may affect the state of charge (SOC), which could result in
bridge cell in the case of STATCOM application. However, it controller malfunction.
is not practical in the BESS case. The methods in [24] as well Another solution involves installing a redundant back-up
as [25] also isolate the faulty switch and have the ability to system; however, that significantly increases the overall cost of
compensate for the fault to maintain the same output voltage. the system. Redundancy can be achieved when a faulty cell is
However, these methods are designed only for inverters bypassed and isolated to compensate for the missing voltage
possessing boost stages. There are several other methods level using back-up systems (an extra H-bridge or batteries).
proposed for fault-tolerant and reconfiguration when a switch This method can maintain the continuity of the inverter whilst
fault occurs [26]-[35]. However, the fault-tolerant strategies producing the same output voltage level. However, using an
presented for the dc-dc inverters [26]-[29], flying capacitor additional dc source increases the price of the system and the
inverter [30], two-stage converter [31], T-type inverter [32], control complexity [41], [42].
multi-phase inverter [33], and NPC [34]-[35] cannot be Considering the above aspects in the development of fault
implemented with the CHB inverter for BESS. tolerant and robust CHB systems, a novel hybrid CHB is
The structure presented in [36] proposes a 5-level inverter proposed by adding a novel X-CHB inverter to provide smooth
for PV systems with fault-tolerant operation capability. It and reliable operation in case of semiconductor device failure
consists of a 2-level half-bridge inverter, 3-level diode clamped or battery fault. The proposed X-CHB is a five-level inverter
inverter, and a bidirectional switch, which is a combination of with a voltage gain of up to 2. One flying capacitor is integrated
a switch with four diodes. The 5-level topology in [36] topology into the proposed structure that provides the voltage boost to
requires nine switches, two dc-supplies, four diodes, and a achieve self-voltage balancing capability in the new system.
center tapped transformer. In the case of a switch fault, or dc- Even though the application of the proposed topology has been
source fault, the 5-level topology in [36] operates as a three- demonstrated with CHB for BESS, it can also be integrated with
level, which results in the output voltage being half of what it is any type of multilevel topology to achieve fault-tolerant
in the normal operation. To maintain the output voltage of the capability.
inverter to be the same as before the fault occurs, [36] suggests This paper is structured as follows: the concept and analysis
to use two additional switches and a center tapped transformer. of the proposed hybrid cascaded H-bridge are presented in
Therefore, this will increase the system cost and complexity. Section II. The operation principles of the proposed topology
The 5-level inverter topology proposed in [37] and [38] are given in Section III. A description of modulation strategies
consists of four unidirectional switches, two bidirectional under unity and non-unity power factors is provided in Section
switches, and two dc-power supplies. In [37], the topology IV. Simulation and experimental results are evaluated in
offers reliable operation only in case of open-circuit faults. In Section V, and this paper is concluded in Section VI.
addition, there are some specific cases where the output voltage
cannot be maintained as the input voltage when there is an II. PROPOSED X-CHB INVERTER
open-circuit fault occurrence. In [38], it requires additional fast-
acting fuses to make sure the switch that gets short-circuited The proposed circuit is a combination of X-CHB (upper cell)
acts as an open-circuit failure since this topology cannot handle and an n-level CHB as shown in Fig. 1. The X-CHB produces
a short-circuit fault. In addition, the proposed topology in [38] five levels. It consists of eight switches; (S3, S6) which have
cannot handle all the switches' faults equally. For example, it bipolar voltage capability, and (S1, S2, S4, S5, S7 and S8) are
can compensate for the faulty switches (open-circuit fault) and standard semiconductor devices, such as either IGBTs or
make sure the output voltage is the same before and after the MOSFETs. It also requires an additional flying capacitor CF, to
fault occurs in some of the switches. However, when the fault boost the voltage up to 2x. In every switching cycle, the flying
occurs in other switches, this topology cannot compensate for capacitor charges to Vdc from its input dc supply through S3 and
the fault and the output voltage level is reduced. S6. The X-switches (S1 and S2) are employed to create the
The structure presented in [39] adds four switches to bypass second voltage level by connecting the dc supply with the flying
the faulty cell. Two of these switches are normally open and capacitor and also to boost the voltage up to 2x. Consequently,
two normally closed. The switches used in this article are the output voltage levels are 2ܸௗ௖ , ܸௗ௖ , 0, -ܸௗ௖ , and -2ܸௗ௖ .
electromechanical switches, which are really slow to respond In normal operating conditions, the X-CHB works as three
comparing with semiconductor devices. Also, this method level inverter producing ܸௗ௖ , 0, - ܸௗ௖ from the dc source.
results in high conduction losses since two switches per H- However, during a fault condition such as an open/short-circuit
bridge are always turned-on during normal operation, which fault or battery fault, the system loses one voltage level. During
produces more losses and heat. The method in [40] adds four that time, the X-CHB operates as a five level boost inverter
switches to bypass the faulty cell and connect its batteries to the compensating for the missing voltage level. This ensures
healthy cell. Adding batteries to another cell may damage the continuity of operation without any disturbance. Therefore, this
switches because the input voltage gets doubled, which may topology brings a high degree of reliability to the overall system
exceed the breakdown voltage of the semiconductor. Secondly, under different fault scenarios.
in the case of BESS and photovoltaic systems, a controller Overall, this paper presents a novel power converter topology
should be employed to balance the charging and discharging with improved features, such as: 1) continuity of operation in
process. Adding a battery from a faulty cell to a healthy cell case of a fault (open/short circuit switch fault), 2) full reactive
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

B+ +
Y  X-CHB
P
R+
S3
S3 S7
S7
S1 S1 S4
C1 S4 +
Vdc + Vdc VFC CF
-
- CF
S2 S5 S5
S8 S2 S8
S6
S6 
N 
S11 S13
S11 S13

H-Bridge 1

 S12 S14
S12 S14 
S21 S23
SN1 SN3
B-
Y-
R- H-Bridge 2

SN2 SN4  S22 S24

Fig. 1. Proposed n-level three phase hybrid CHB inverter. Fig. 2. A 7-level single phase hybrid CHB inverter.

TABLE I
SWITCHING STATES OF THE PROPOSED HYBRID X-CHB INVERTER UNDER FAULT
Switching Active Switching States Flying
States ࢂࢄ࢕ ࡿ૚ ࡿ૛ ࡿ૜ ࡿ૝ ࡿ૞ ࡿ૟ ࡿૠ ࡿૡ ࡿ૚૚ ࡿ૚૛ ࡿ૚૜ ࡿ૚૝ Capacitor

A 0 0 0 0 1 1 0 1 1 0 0 1 ņ
B ൅ܸௗ௖ 0 0 1 1 0 1 0 1 1 1 0 0 Ĺ
C 0 0 0 1 0 1 0 1 0 1 0 1 Ļ
D 0 0 1 1 0 1 0 1 1 0 0 1 Ĺ
E ൅ʹܸௗ௖ 0 0 0 1 0 1 0 1 1 0 0 1 Ļ
F 1 0 0 1 0 0 0 1 1 1 0 0 Ļ
G ൅͵ܸௗ௖ 1 0 0 1 0 0 0 1 1 0 0 1 Ļ
H Ͳ 0 0 0 0 1 1 0 1 0 1 0 0 ņ
I 0 0 1 1 0 0 1 0 0 1 1 0 ņ
J െܸௗ௖ 0 0 1 0 1 1 1 0 1 0 1 0 Ĺ
K 0 0 1 0 1 0 1 0 1 0 1 0 Ļ
L 0 0 1 0 1 1 1 0 0 1 1 0 Ĺ
െʹܸௗ௖ 0 0 1 0 1 0 1 0 1 0 1 0
M Ļ
N 0 1 0 0 1 0 1 0 0 1 1 0 Ļ
O െ͵ܸௗ௖ 0 1 0 0 1 0 1 0 0 1 1 0 Ļ
P 0 0 0 1 1 0 0 1 0 1 0 1 0 ņ
Note: “ņ” means no effect, “Ĺ” means charging, “Ļ” means discharging

power operation due to its capability of operation in any power The proposed topology for fault-tolerant operation is suitable
factor (lagging/leading), 3) self-balancing for the flying for applications where the continuity of operation is an
capacitor of the proposed inverter, and 4) boosting the voltage important factor for critical applications such as when the
level by factor of 2 without the need of an extra boost stage supplies are renewable energy sources.
(inductorless voltage boost).
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S3 S3 S3
S7 S7 S7

S4 S4 S4
+ + Vdc +
C
C Vdc C - F
Vdc - F + VCF=Vdc - F + VX0 + VX0
S5 -
VX0 S5 - S5 -
S8 S8 S8

S6 S6 S6

S11 S13 S11 S13 S11 S13

H-Bridge 1 H-Bridge 1 H-Bridge 1

S12 S14 S12 S14 S12 S14

S21 S23 S21 S23 S21 S23

H-Bridge 2 H-Bridge 2 H-Bridge 2

S22 S24 S22 S24 S22 S24

(a) (b) (c)

S3 S3 S3
S7 S7 S7

S4 S4 S4
Vdc Vdc + Vdc +
+ C
C
VCF=Vdc - F - F + -CF +
+ VX0
S5 VX0 S5 - S5 - VX0
-
S8 S8 S8

S6 S6 S6

S11 S13 S11 S13 S11 S13

H-Bridge 1 H-Bridge 1 H-Bridge 1

S12 S14 S12 S14 S12 S14

S21 S23 S21 S23 S21 S23

H-Bridge 2 H-Bridge H-Bridge 2

2
S22 S24 S22 S24 S22 S24

(d) (e) (f)

S3 S3
S7 S7

S4 S4
Vdc Vdc
+ +
-CF + -CF +
S5 VX0 S5 VX0
- -
S8 S8

S6 S6

S11 S13 S11 S13

H-Bridge 1 H-Bridge 1
S12 S14 S12 S14

S21 S23 S21 S23

H-Bridge 2 H-Bridge 2
S22 S24 S22 S24

(g) (h)
Fig. 3. Switching states analysis for a positive half-cycle of the hybrid CHB.
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III. OPERATION MODES FOR THE PROPOSED HYBRID CHB  Vref

3Ac 6
SYSTEM  Vtr1
2Ac 4
Vtr2
Ac 2
A. Introduction to the Proposed Topology Vtr3
0 0
A 7-level hybrid cascaded H-Bridge for fault-tolerant Vtr4
-Ac
operation is shown in Fig. 2. It consists of the X-CHB (the upper  Vtr5
-2Ac
highlighted cell) with two cascaded H-bridge cells. During  Vtr6
-3Ac
normal operation, with no fault, the inverter produces seven

voltage levels, where the X-CHB operates as an H-bridge
inverter producing ܸௗ௖ , 0, -ܸௗ௖ . In other words, the inverter 
consists of three H-bridge cells and operates as a conventional 3Vdc
2V
7-level CHB inverter. dc

Vdc
0
B. Operation of the Proposed Topology -Vdc
During a fault condition such as open/short-circuit fault or -2V

dc
battery fault, the system would typically lose one voltage level. -3Vdc
It is worth noting that the fault detection method is not the 
main concern of this paper. This work focuses on a method to ș1 ș2 ș3 ʌ ș6 ș7
ș4 ș8 ș9 2ʌ
t0 t1 t2  t3 t4 t5 t6 t7  t8 t9 t10
compensate for faults to maintain the same output voltage after
AHBHCH ADCDBEBF GD DADCBEBF HAHBHC IPJPKP ILKLJMJN OL LILKMJNJ PIPJPK
the fault happens. In other words, the proposed method to
compensate for the fault is when the fault has been identified Fig. 4. Modulation strategy of the proposed inverter under unity power-
using any fault detection method. So, while this paper focuses factor.
on developing a fault tolerant topology, the fault detection
method in [43] has been adopted to detect the switch fault. Once Interval 2
Interval 1
the faulty cell/switch is detected, the faulty H-bridge is
bypassed by turning ON its upper or lower switches.
During the fault scenario, the X-CHB operates as a five level
boost inverter producing 2ܸௗ௖ , ܸௗ௖ , 0, -ܸௗ௖ , and -2ܸௗ௖ voltage A B C B C
D D E F D D
levels to compensate for the missing voltage level to ensure the
original seven voltage levels at the output of the inverter. A C B B A C
During a fault occurrence in one of the inverter switches, the H H H H H H
X-CHB can compensate for the missing voltage of the bypassed t0 t1 t1 t2
H-bridge, where the X-CHB operates as a 7-level inverter. If Fig. 5. The modulation for interval 1. Fig. 6. The modulation for interval 2.
there is another switch fault, there are three different scenarios:
1) Another fault in the same faulty H-bridge. In this case, the Reactive Power Mode Active Power Mode
proposed topology continues operating with the same output Đ

voltage. That is, the second switch fault does not affect the Z1 Z2 Z3 Z4 Z1
inverter since the entire stage is bypassed as mentioned earlier.
2) Another fault in the same phase. In other words, there are Vac
0
two faulty switches in the same phase, but the faulty switches
are in two different H-bridge cells. The proposed hybrid fault-
tolerant topology immediately bypasses the first and second
faulty H-bridge cells. Since the X-CHB can compensate for
only one H-bridge, the inverter loses one voltage level.
Iac
3) Additional fault in one or both of the other phases. In other 0
words, there is a fault in two of three phases. In this scenario,
the proposed topology is able to compensate for the faulty
switches in the other phase. The faulty cell is isolated; the X-
CHB compensates for each voltage level missing.
The operational analysis adopted sixteen different switching
0
modes (state A to P). Table I lists all possible switching states
with its corresponding output voltage for the proposed X-CHB
inverter. The operation and analysis of the proposed hybrid ș1 ș2 ș3 ș4 ʌ ș6 ș7 ș8 ș9 2ʌ
t0 t1 t2 t3 t4 t6 t7 t8 t9 t10
cascaded H-Bridge during the positive half-cycle (states A to
HCHQHA FQEQRCRA RG GD DADCEBFB HAHBHC PKPSPI NSMSTKTI TO OL LILKMJNJ PIPJPK
H) is illustrated in Fig. 3. By way of illustration, the inverter is
assumed to have a fault in the second H-bridge (H-bridge 2),
Fig. 7. Modulation strategy of the proposed inverter under non-unity power-
and the faulty cell is bypassed by turning ON both of the lower factor.
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switches, ܵଶଶ andܵଶସ , of the faulty cell (software bypassing). ܸௗ௖ଵ ǡܵ‫ܣ݁ݐܽݐ‬
The red dotted line in Fig. 3 represents the current path, and the ܸௗ௖௫ ǡܵ‫ܤ݁ݐܽݐ‬
ܸ௑ை ൌ൞ (1)
blue indicates the capacitor charging current path. The output ܸௗ௖௫ ǡܵ‫ܥ݁ݐܽݐ‬
voltage of the X-CHB and the inverter are defined as ܸ௑ , and Ͳǡܵ‫ܪ݁ݐܽݐ‬
ܸ௑ை , respectively.
2) Interval 2 (‫ݐ‬ଵ –‘‫ݐ‬ଶ ƒ†‫ݐ‬ଷ –‘‫ݐ‬ସ )
The flying capacitor (CF) is clamped to the dc power supply
During these operation zones, the output voltage is switched
through switches ܵଷ and ܵ଺ as shown in Figs. 3(b), and (d),
from ܸௗ௖ to 2ܸௗ௖ . Redundant states (D, E, and F) are used to
where the flying capacitor voltage (ܸ஼ி ) is equal to the input
generate 2 ܸௗ௖ . The switching sequence (ADCDBEBF) for
voltage ܸௗ௖ . To compensate for the voltage level during the
interval (–ଵ to – ଶ ), and switching sequence (DADCEBFB) for
fault, the voltage across CF gets discharged, and the output
interval (– ଷ to – ସ ) maintain the voltage between ܸௗ௖ and 2ܸௗ௖ .
voltage of the X-CHB ܸ௑ is equal to 2ܸௗ௖ and as shown in Fig.
Selecting these redundant states provides self-balancing for the
3 (g). By discharging ‫ܥ‬ி during the positive cycle in series with
flying capacitor.
the input voltage (when ܵଵ , ܵସ and ଼ܵ are ON), the output
The inverter output voltages during this interval are:
voltage of the X-CHB is 2ܸௗ௖ (ܸ௑ = 2ܸௗ௖ ) as shown in Fig. 3(g).
Similarly, during the negative cycle, X-CHB can generate -2ܸௗ௖ ܸௗ௖ଵ ǡܵ‫ܣ݁ݐܽݐ‬
by discharging the flying capacitor and connecting it in series ‫ ܸ ۓ‬ǡܵ‫ܤ݁ݐܽݐ‬
with input voltage throughܵଶ , ܵହ and ܵ଻ . ۖ ௗ௖௫
ܸௗ௖௫ ǡܵ‫ܥ݁ݐܽݐ‬
Thus, the proposed X-CHB has the ability to boost the ܸ௑ை ൌ (2)
‫ ۔‬ௗ௖ଵ ൅ ܸௗ௖௫ ǡܵ‫ܦ݁ݐܽݐ‬
ܸ
voltage up to 2x, and increase the voltage levels by using only ۖ ܸௗ௖ଵ ൅ ܸ௑ ǡܵ‫ܧ݁ݐܽݐ‬
eight additional switches and one capacitor in the X-CHB ‫ܸ ە‬ௗ௖௫ ൅ ܸ௑ ǡܵ‫ܨ݁ݐܽݐ‬
without the need of an inductor. These features make the X- Fig. 6 shows the modulation of interval 2 during (–ଵ to – ଶ ).
CHB applicable to any type of multilevel inverter to achieve The self-voltage balancing during (–ଵ to – ଶ ) is implemented
fault tolerant operation. using the redundant states (D, E, and F), which generate 2ܸௗ௖ .
Both states E and F can generate 2ܸௗ௖ with the flying capacitor
IV. MODULATION STRATEGY being discharged. In other words, the flying capacitor is always
discharged during states E and F. Therefore, when using these
A. Unity Power-Factor Operation states during interval 2, and the flying capacitor voltage is lower
The modulation strategy of the converter under unity power- than the reference voltage, the flying capacitor is charged by
factor conditions is shown in Fig. 4. Phase disposition level- using state B, which provides a charging mode for the flying
shifted PWM is used because it provides lower total harmonic capacitor. However, when the flying capacitor voltage is greater
distortion (THD) and simplicity of implementation. Six than the reference voltage, state A or C is selected to provide
triangular carrier signals and one sinusoidal reference signal are a discharge mode for the capacitor. Consequently, using these
used to generate the 7-voltage levels of the proposed hybrid redundant states results in self-balancing.
CHB. The carrier signals are compared with the reference 3) Interval 3 (‫ݐ‬ଶ to ‫ݐ‬ଷ )
signal to generate the proper PWM signals resulting in 7-level The output voltage during this period of time is changing
inverter. In order to analyze the modulation strategy, one output from 2ܸௗ௖ to 3ܸௗ௖ . To generate 3ܸௗ௖ , state F is used, which
voltage cycle can be divided into six time intervals as shown in generates the voltage by using the proposed novel inverter.
Fig. 4. The output voltages during interval 3 are:

1) Interval 1 (‫ݐ‬଴ to ‫ݐ‬ଵ and ‫ݐ‬ସ to ‫ݐ‬ହ ) ܸௗ௖ଵ ൅ ܸௗ௖௫ ǡܵ‫ܦ݁ݐܽݐ‬

ܸ௑ை ൌ ൜
ܸௗ௖ଵ ൅ ܸௗ௖௫ ൅ ܸ௑ ǡܵ‫ܩ݁ݐܽݐ‬
(3)
During this interval, the output voltage is switched between
0 and ܸௗ௖ . States A, B, and C are used to generate ܸௗ௖ , while H
is used to generate 0. Using these different redundant states (A, It is obvious that during this interval that just state D is used
B and C) to generate ܸௗ௖ , enables the controller to regulate the to generate 2ܸௗ௖ . Neither E nor F is used. That is, states E and
voltage across the flying capacitor. When the flying capacitor F can generate 2ܸௗ௖ , but the flying capacitor is always being
voltage (ܸ௑ ) is lower than the input voltage (which is also used discharged; however, state D provides a charging mode for the
as a reference voltage to regulate the flying capacitor voltage flying capacitor. Since there is just one state to generate 3ܸௗ௖ ,
(ܸ஼ி ), state B is selected since this state provides a charging state G, and the flying capacitor is always being discharged, the
mode for the flying capacitor. However, when the flying selected state with state G should provide a charging mode.
capacitor voltage (ܸ஼ி ) is greater than the reference voltage, Consequently, self-balancing for the flying capacitor depends-
state A or C are chosen.
As a result, the switching sequence (AHBHCH) for interval -on the state that generates the 2ܸௗ௖ to charge the capacitor and
(– ଴ to –ଵ ) and switching sequence (HAHBHC) for interval (– ସ make it ready for the next level (3ܸௗ௖ ) to be discharged.
to – ହ ), helps to balance ܸ௑ .
4) Interval 4 (‫ݐ‬ହ –‘‫ݐ†ƒ ଺ݐ‬ଽ –‘‫ݐ‬ଵ଴ )
The modulation of interval 1 is shown in Fig. 5. The inverter The output voltage during this interval is 0 and - ܸௗ௖ .
output voltage during interval 1 can be express as: Redundant states H and I are used to generate -ܸௗ௖ , and P for
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S3 S3 S3
S3
S7 S7 S7 S7

S4 S4 S4 S4
+ Vdc + Vdc +
Vdc C Vdc +
C C
- F
C
- F
- F - F + +
+ VX0 + VX0 S5 VX0 S5 VX0
S5 - S5 - - -
S8 S8 S8 S8

S6 S6 S6 S6

S11 S13 S11 S13 S11 S13 S11 S13

H-Bridge 1 H-Bridge 1 H-Bridge 1 H-Bridge 1

S12 S14 S12 S14 S12 S14 S12 S14

S21 S23 S21 S23 S21 S23 S21 S23

H-Bridge 2 H-Bridge 2 H-Bridge 2 H-Bridge 2

S22 S24 S22 S24 S22 S24 S22 S24

(a) (b) (c) (d)

Fig. 8. Switching states analysis of the proposed 7LX-BANPC inverter in non-unity power-factor operation. (a) State Q, (b) State R, (c) State S, and (d) State T

the 0 state. The balancing of this interval is similar to interval Unity Power Factor Operation Non-unity Power Factor Operation
1. The switching state sequences for (– ହ to – ଺ ) is (IPJPKP), and
for (– ଽ to –ଵ଴ ) is (PIPJPK). For ij = 0 For ij < Sin-1(1/4) For ij > Sin-1(1/4)
The output voltages of the inverter during this interval are:
+ 3Vdc G + 3Vdc
െܸௗ௖ଵ ǡܵ‫ܫ݁ݐܽݐ‬ + iac - iac
െܸ ǡܵ‫ܬ݁ݐܽݐ‬
ܸ௑ை ൌ ൞ ௗ௖௫ (4) + 2Vdc
െܸௗ௖௫ ǡܵ‫ܭ݁ݐܽݐ‬ D E F R E F
+ 2Vdc
Ͳǡܵ‫ܲ݁ݐܽݐ‬ + iac - iac

5) Interval 5 (‫ݐ‘– ଼ݐ†ƒ ଻ݐ‘– ଺ݐ‬ଽ ) + Vdc + Vdc

The switching states sequences (ILKLJMJN) and + iac A B C A C Q
- iac
(LILKMJNJ) during (– ଺ to – ଻ ) and (– ଼ to – ଽ ), respectively, are
used to generate -ܸௗ௖ and -2ܸௗ௖ , and also ensure self-balancing
for the flying capacitor voltage.
The phase inverter output voltage (ܸ௑ை ) can be expressed as: 0 H&P 0

െܸௗ௖ଵ ǡܵ‫ܫ݁ݐܽݐ‬
‫ ۓ‬െܸ ǡܵ‫ܬ݁ݐܽݐ‬
ۖ ௗ௖௫ - Vdc - Vdc
െܸௗ௖௫ ǡܵ‫ܭ݁ݐܽݐ‬ - iac I J K I K S
ܸ௑ை ൌ (5) +iac
‫ ۔‬െܸௗ௖ଵ െ ܸௗ௖௫ ǡܵ‫ܮ݁ݐܽݐ‬
ۖെܸௗ௖ଵ െ ܸ௑ ǡܵ‫ܯ݁ݐܽݐ‬
‫ ە‬െܸௗ௖௫ െ ܸ௑ ǡܵ‫ܰ݁ݐܽݐ‬
- 2Vdc L M N
- 2Vdc
T M N
- iac + iac
6) Interval 6 (‫) ଼ݐ‘– ଻ݐ‬
The switching states L and O are selected to produce -ʹܸௗ௖
- 3Vdc - 3Vdc
and -3ܸௗ௖ . During this interval, self-balancing for the flying O + iac
capacitor is also implemented using the same strategy as in - iac
interval 3. Commutation States
Switching States
The phase voltage during this interval can be expressed as:
Fig. 9. Switching states during unity and non-unity power factors.
െܸ െ ܸௗ௖௫ ǡܵ‫ܮ݁ݐܽݐ‬
ܸ௑ை ൌ ൜ ௗ௖ଵ (6)
െܸௗ௖ଵ െ ܸௗ௖௫ െ ܸ௑ ǡܵ‫ܱ݁ݐܽݐ‬
through Z4) can be defined to express the modulation scheme
B. Non-Unity Power-Factor Operation during a complete grid cycle depending on the output current
An example of non-unity power-factor under a reactive direction and the voltage polarity.
power condition, where the output voltage and current have The reactive power region, where the output voltage and
different polarities is shown Fig. 7. Four operation zones (Z1 current have opposite polarity, is represented in Z1 and Z3.
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

TABLE II

COMPARISON OF FAULT-TOLERANT TECHNIQUES (seven level – single phase)

Scheme [40] [39] [22] [44] [42] [45] [46] Proposed
Number of Power Switches 16 12 12 24 16 18 14 16
Number of Relays 20 12 3 6 3 2 6 0
Control Complexity Complex Complex Easy Moderate Complex Easy Moderate Easy
Hardware Cost High High Low Medium High Medium High Low
Applicable to Different Topologies No No No No Yes Yes Yes Yes
Applicable to BESS Yes Yes No Yes Yes Yes Yes Yes

During Z1, the voltage polarity is positive while current is this method expensive, and the control is more complex. In the
negative. However, the output voltage is negative and current is case of BESS, when the batteries from a faulty cell are added to
positive in Z3. The active power region is defined as Z2 and Z4, a healthy H-bridge cell, the charge balancing is more complex,
where both the output voltage and current have the same which requires complex control algorithms to maintain the
polarity. It is clear that under the active power operation, the balancing of the batteries during the charging and discharging
switching states have the same sequence as the unity power- modes. Moreover, the hardware implementation suffers from
factor as shown in Fig. 4. challenges due to the large number of relays. The structure in
Even if switches ܵଷ andܵ଺ are unidirectional, that does not [44] requires 12 more switches, and 6 additional relays to
affect the inverter’s ability to operate under reactive power isolate the fault and reconfigure the circuit to maintain the same
mode. When the output voltage and current have opposite output voltage as under normal operation.
polarity, the switching states B, D, J, and L transfer naturally to Unlike the fault-tolerant structures in [39], [40], and [44], the
be Q, R, S, and T as summarized in Fig. 8. scheme in [45] and [22] do not require a large number of
The output voltages of the inverter during the reactive power additional relays and switches. The proposed structure in [45]
mode are: requires six extra switches, two relays, and one dc link
ܸௗ௖ଵ ǡܵ‫ܳ݁ݐܽݐ‬ capacitor, which makes it easier to control than [39], [40], and
ܸ ൅ ܸௗ௖ଵ ǡܵ‫ܴ݁ݐܽݐ‬ [44]. Nevertheless, the proposed hybrid CHB inverter offers
ܸ௑ை ൌ ൞ ௗ௖௫ (7)
െܸௗ௖ଵ ǡܵ‫ܵ݁ݐܽݐ‬ even fewer switches and no need for additional relays. In [22],
െܸௗ௖ଵ െ ܸௗ௖ଵ ǡܵ‫ܶ݁ݐܽݐ‬ the structure suggests to isolate the faulty cell in a phase and
two healthy cells in the other phases. That is, when a fault
The switching states are not part of the main switching states occurs in a phase, the faulty cell is bypassed, and two more cells
of the inverter that were described in the unity power-factor from the other phases are also bypassed, which results in an
section. The switches naturally commutate due to the fact that inverter generating an output voltage with fewer levels than
the polarity and direction of the output voltage and current are normal operation. In other words, the inverter output voltage
different. The operation state of the inverter under both unity becomes 5-level instead of 7-level. This topology is suitable for
and non-unity power-factor is summarized in Fig. 9. STATCOM applications, but not for BESS. The method in [22]
employed one relay per cell, which makes it easy to control.
V. COMPARATIVE SUMMARY However, the proposed topology can be implemented in both
STATCOM and BESS applications with a simple control
A comparative summary of some of the key features of the scheme.
proposed topology with other fault-tolerant structures for a The fault-tolerant scheme in [42] suggests to insulate an extra
CHB inverter is presented in Table II. The number of H-bridge cell with a dc source such that its voltage is equal to
components and parameters included in Table II are for single- the other H-bridge cell voltages. The redundant H-bridge cell
phase 7-level fault-tolerant topologies. The number of has no functionality until the fault occurs. When a
semiconductor devices in each topology is listed, where the semiconductor switch fault occurs, the faulty H-bridge is
basic number is 12. For example, the total number of the power isolated, and the redundant back-up battery is connected to the
switches for the 7-level single phase for the proposed hybrid inverter to maintain the output voltage to be as same as normal
CHB inverter is 16 as in Table II, which includes eight switches operation. One of the biggest issues with this method is the cost
for H-bridge 1 and 2, and 8 switches for the hybrid CHB of implementation since the price of the batteries is too
inverter as shown in Fig. 2. expensive for medium and high voltage applications.
In the fault-tolerant structure presented in [39] and [40], the According to [47], the batteries cost around 55% of the total
fault is bypassed using four extra relays for each H-bridge cell. cost for a power electronics drive system, while the other power
In addition, the batteries for the faulty cell are disconnected electronics components cost 24%. In addition, the SOC
from the faulty cell and connected to a healthy H-bridge cell to balancing requires a complex control algorithm to balance the
ensure continuity of operation while losing one voltage level. batteries after the fault occurs. The SOC of the standby batteries
In other words, the extra relays isolate the faulty cell from the before the fault is around 100%, since they have not been
inverter and connect its batteries to a healthy H-bridge cell. The functioning. Suppose the fault occurs when the SOC of the
high number of relays, four per H-bridge cell, makes the cost of
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

Phase-phase voltage before filter (V) Phase-phase voltage before filter (V)

400 400

0 00
-400 -400
Line voltage after filter (V) Line voltage after filter (V)

400 400

0 00
-400 -400
Load current (line) (A) Load current (line) (A)
5 5

0 0

-5 -5
Flying capacitor voltage (V) Flying capacitor voltage (V)
135 135
Ɏ=45
130 130

125 125
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1  0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Fig. 10. Operation of the inverter under unity power factor. Fig. 11. Operation of the inverter under lagging power factor.
Phase-phase voltage before filter (V)
400
0 7-Level CHB 7-Level Proposed Hybrid CHB
Normal Mode Faulted
Compensation Mode
Mode
-400 Phase-phase voltage (V)
Line voltage after filter (V) 400

400
0
0
-400
-400
Line voltage after filter (V)
Load current (line) (A) 400
5
0
0
-400
-5
Load current (line) (A)
Flying capacitor voltage (V)
135 5

Ɏ=-45
130 0

125 -5
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1  0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

Fig. 12. Operation of the inverter under leading power factor. Fig. 13. Normal, faulted, and compensation modes (resistive load).
7-Level CHB 7-Level Proposed Hybrid CHB 7-Level CHB 7-Level Proposed Hybrid CHB
Normal Mode Faulted Compensation Mode Normal Mode Faulted Compensation Mode
Mode Mode
Phase-phase voltage (V) Phase-phase voltage (V)
400 400

0 0

-400 -400
Line voltage after filter (V) Line voltage after filter (V)
400 400

0 0

-400 -400
Load current (line) (A) Load current (line) (A)
5 5

0 0

-5 -5
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1  0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

Fig. 14. Normal, faulted, and compensation modes (inductive load). Fig. 15. Normal, faulted, and compensation modes (capacitive load).

Control
Board

H-Bridge
1& 2
ac out

X-
CHB

C1 CF

dc + dc
dc --
Fig. 16. Picture showing the prototype of the proposed hybrid X-CHB inverter.
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

7 level voltage v7L-ac [200 V/div] 7 level voltage v7L-ac [200 V/div]

Load current iac [5 A/div] Load current iac [5 A/div]

Load voltage vac [200 V/div] Load voltage vac [200 V/div]

Fig. 17. Operation of the inverter under unity power factor. Fig. 18. Operation of the inverter under lagging power factor.

7-Level CHB Faulted 7-Level

Normal Mode Mode Compensation Mode

7 level voltage v7L-ac [200 V/div]

Load current iac [5 A/div]

Load voltage vac [200 V/div]

Fig. 19. Operation of the inverter under leading power factor. Fig. 20. Normal, faulted, and compensation modes (resistive load).

7-Level CHB Faulted 7-Level 7-Level CHB Faulted 7-Level

Normal Mode Mode Compensation Mode Normal Mode Mode Compensation Mode

7 level voltage v7L-ac [200 V/div] 7 level voltage v7L-ac [200 V/div]

Load current iac [5 A/div] Load current iac [5 A/div]

Load voltage vac [200 V/div] Load voltage vac [200 V/div]

Fig. 21. Normal, faulted, and compensation modes (inductive load). Fig. 22. Normal, faulted, and compensation modes (capacitive load).
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

healthy batteries is 50%. In order to maintain all the batteries 7-Level CHB Faulted 7-Level
balanced, the control algorithm must be designed carefully. Normal Mode Mode Compensation Mode

Another method for fault-tolerant operation for CHB

inverters using an auxiliary circuit is proposed in [46].
Although the structure in [46] does not require any extra
semiconductor switches, fault-tolerant operation is
accomplished by adding an additional auxiliary circuit. The
7 level voltage v7L-ac Flying capacitor voltage
auxiliary circuit consists of six relays and two additional power [500 V/div] [100 V/div]
supplies, which increases the cost and complexity of the system.
In addition, the proposed topology does not require extra relays,
Load current
which results in higher reliability and less complexity compared [2 A/div]
with other topologies. Unlike the fault-tolerant topologies in
[39], [40], [42] and [44], the proposed topology does not suffer
from control complexity or SOC balance issues.
Switch current (S21) [2 A/div]
VI. SIMULATION AND EXPERIMENTAL RESULTS

To verify the concept of the proposed hybrid CHB inverter,

a detailed MATLAB/Simulink® model for the circuit of Fig. 2 Fig. 23. Normal, faulted, and compensation modes; the output voltage
was analyzed for the 7-level inverter. The parameter and (unfiltered) (ch1), flying capacitor voltage (ܸ஼ி ) (ch2), line current (ch3), and
component values of the simulation and experiment are given faulty switch current (ܵଶଵ ) (ch4).
in Table II. Fig. 10 shows the waveforms for the output voltage
TABLE III
(unfiltered and filtered), line current, and voltage across the
flying capacitor for the proposed hybrid CHB inverter under SIMULATION AND EXPERIENTIAL PARAMETERS
unity power-factor. Description Value
The inverter’s operation in lagging and leading power factor
has been successfully tested. Fig. 11 and Fig. 12 show the Number of cells 3
operation in lagging and leading power factor, respectively. Power rated 1 kVA
There is not any specific consideration or technique that the
proposed inverter requires to operate under any power-factor. Input voltage (ܸௗ௖ ) 400 V
Fig. 13 and Fig. 15 are verifications of the operations as
Line frequency 60 Hz
illustrated in Fig. 9.
An open-circuit fault scenario has been created in ܵଶଵ in Fig. Flying capacitor 470 μF
2. As shown in Fig. 13, the three different modes are: normal
Filter inductor, 0.16 mH
operation mode (where the inverter functions as a normal
CHB), faulted mode (a fault is induced and one voltage level is Filter Capacitor 50 μF
lost), and compensation mode (where the proposed hybrid CHB
operation starts). During the faulted mode, the output voltage Carrier frequency 7 kHz
loses one voltage level. The fault is detected and isolated using Switches (S1- S24) CMF20120
the method proposed in [43]. The X-CHB compensates for the
lost output voltage and restores the output voltage to normal
levels without affecting the system connected downstream. The sinusoidal voltage. An open-circuit fault has been created in ܵଶଵ
proposed inverter is also evaluated under lagging and leading in Fig. 2. After the fault occurs in ܵଶଵ , the method in [43] for
power factor to show its capability of operating under reactive fault detection and isolation is used. Fig. 20 shows the output
power conditions. Figs. 14 and 15 show the normal operation, voltage (unfiltered and filtered), and line current under normal,
faulted mode, and compensation mode during lagging and faulted and compensation modes for unity power-factor. Figs.
leading power factors, respectively. 21 and 22 shows the output voltage (unfiltered and filtered), and
A scaled down 7-level hybrid CHB low-power prototype has line current under normal, faulted and compensation modes for
been built and tested in the laboratory as shown in Fig. 16 to both lagging and leading power factors, respectively. Fig. 23
validate the concept and performance of the new circuit. All the shows the output voltage (unfiltered), flying capacitor voltage
switches are (CMF20120) from Cree/Wolfspeed. The output (ܸ஼ி ), line current, and faulty switch current (ܵଶଵ ) under normal,
voltage (unfiltered and filtered), and line current under normal faulted, and compensation modes for unity power-factor. It
operation and unity power factor is shown in Fig. 17. To verify shows a smooth transition from a faulted mode to a
the inverter ability to operate under reactive power modes, the compensation mode. Consequently, the output voltage of the
inverter has been tested under lagging and leading power inverter is the same before and after fault occurred. The
factors as shown in Figs. 18 and 19. The inverter’s ability to proposed fault-tolerant method provides high reliability for
generate a 7-level output voltage is observed with pure expensive and critical applications such as BESS to avoid
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

expensive shut down. Grid-tied multilevel inverters are [8] H. Wang et al., “Transitioning to physics-of-failure as a reliability driver
in power electronics,” IEEE J. Emerg. Sel. Topics Power Electron. , vol.
sensitive to unbalanced voltage because of the synchronization
2, no. 1, pp. 97-114, March 2014.
between the grid and inverter requiring both of their voltages to [9] P. Tu, S. Yang and P. Wang, “Reliability- and cost-based redundancy
be equal. Synchronization could be lost when there is a switch design for modular multilevel converter,” IEEE Trans. Ind. Electron., vol.
or dc power supply fault (battery fault), which consequently 66, no. 3, pp. 2333-2342, March 2019.
[10] S. Yang, A. Bryant, P. Mawby, D. Xiang, L. Ran and P. Tavner, “An
shuts down the systems. industry-based survey of reliability in power electronic converters,” IEEE
Trans. Ind. Appl., vol. 47, no. 3, pp. 1441-1451, May-June 2011.
VII. CONCLUSIONS [11] A. Hanif, Y. Yu, D. DeVoto and F. Khan, “A comprehensive review
toward the state-of-the-art in failure and lifetime predictions of power
electronic devices,” IEEE Trans. Power Electron., vol. 34, no. 5, pp.
This paper presents a novel hybrid CHB for fault-tolerant
4729-4746, May 2019.
operation to ensure seamless operation of the system under an [12] T. Peng et al., “A uniform modeling method based on open-circuit faults
open/short circuit switching fault or dc supply fault, due to analysis for npc-three-level converter,” IEEE Trans. on Circuits and
battery fault, using a novel X-CHB circuit. In addition to fault Systems II: Express Briefs, vol. 66, no. 3, pp. 457-461, March 2019.
[13] R. Xiong, R. Yang, Z. Chen, W. Shen and F. Sun, “Online Fault Diagnosis
tolerant ability, the proposed inverter has the ability to boost the of External Short Circuit for Lithium-Ion Battery Pack,” IEEE Trans. Ind.
voltage by a factor of two, which compensates for the missing Electron., vol. 67, no. 2, pp. 1081-1091, Feb. 2020.
voltage level in the case of open/short circuit faults. Moreover, [14] M. Chen, B. Zhang, Y. Li, G. Qi and J. Liu, “Design of a multi-level battery
the proposed topology achieves full reactive power operation management system for a Cascade H-bridge energy storage system,”
IEEE PES Asia-Pacific Power and Energy Engineering Conference
due to its capability of operation in any power-factor (APPEEC), Hong Kong, 2014, pp. 1-5.
(lagging/leading). Furthermore, the presented modulation [15] E. Chatzinikolaou and D. J. Rogers, “A Comparison of Grid-Connected
strategy enables self-balancing of the flying capacitor of the Battery Energy Storage System Designs,” IEEE Trans. Power Electron.,
proposed the X-CHB. Simulation and experimental results vol. 32, no. 9, pp. 6913-6923, Sept. 2017.
[16] J. Zhang, S. Ci, H. Sharif and M. Alahmad, “Modeling Discharge Behavior
validate the performance of the proposed topology. The of Multicell Battery,” IEEE IEEE Trans. Energy Convers., vol. 25, no. 4,
proposed hybrid fault-tolerant topology is suitable for industrial pp. 1133-1141, Dec. 2010.
applications that require reliable operation such as BESS and [17] Y. Zhu, W. Zhang, J. Cheng and Y. Li, “A novel design of reconfigurable
uninterrupted power systems. multicell for large-scale battery packs,” International Conference on
Power System Technology (POWERCON), Guangzhou, 2018, pp. 1445-
More investigation is needed in order to design new 1452.
topologies which allow continuity of operation in the event of [18] H. Kim and K. G. Shin, “On Dynamic Reconfiguration of a Large-Scale
dc-link capacitor failure, which cannot be addressed by the Battery System,” 15th IEEE Real Time Embedded Technol. Appl. Symp.,
proposed topology. San Francisco, CA, 2009, pp. 87-96.
[19] H. Xiaobin, X. Shuoman, L. Nianzhi and H. Guojian, “Evaluation of bulge
failure status for power battery packs at high temperatures based on ERT,”
ACKNOWLEDGEMENT IEEE International Instrumentation and Measurement Technology
Conference Proceedings, Taipei, 2016, pp. 1-6.
This material is based upon work supported by the National [20] B. Xia, Y. Shang, T. Nguyen and C. Mi, “A correlation based detection
method for internal short circuit in battery packs,” 2017 IEEE Applied
Science Foundation under Grant No. 1439700. Any opinions, Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017,
findings, and conclusions or recommendations expressed in this pp. 2363-2368.
material are those of the author(s) and do not necessarily reflect [21] J. Zhang, Z. Liu, T. Wang, M. E. H. Benbouzid and Y. Wang, “An arm
the views of the National Science Foundation. isolation and reconfiguration fault tolerant control method based on data-
driven methodology for cascaded seven-level inverter,” 2018 IEEE 7th
Data Driven Control and Learning Systems Conference (DDCLS), pp.
REFERENCES 939-943, Enshi, 2018.
[1] S. Kouro et al., “Recent advances and industrial applications of multilevel [22] W. Song, A. Q. Huang, “Fault-tolerant design and control strategy for
converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553-2580, cascaded H-bridge multilevel converter-based STATCOM”, IEEE Trans.
Aug. 2010. Ind. Electron.., vol. 57, no. 8, pp. 2700-2708, Aug. 2010
[2] S. Rivera et al., “Multilevel direct power control—a generalized approach [23] A. Yazdani, H. Sepahvand, M. L. Crow and M. Ferdowsi, “Fault detection
for grid-tied multilevel converter applications,” IEEE Trans. Power and mitigation in multilevel converter STATCOMs,” IEEE Trans. Ind.
Electron., vol. 29, no. 10, pp. 5592-5604, Oct. 2014. Electron., vol. 58, no. 4, pp. 1307-1315, April 2011.
[3] J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, “Multilevel inverters: [24] S. Rahman, M. Meraj, A. Iqbal and L. Ben-Brahim, “Novel voltage
a survey of topologies, controls, and applications,” IEEE Trans. Ind. balancing algorithm for single-phase cascaded multilevel inverter for
Electron., vol. 49, no. 4, pp. 724-738, Aug. 2002. post-module failure operation in solar photovoltaic applications,” in IET
[4] H. Abu-Rub, J. Holtz, J. Rodriguez and G. Baoming, “Medium-voltage Renewable Power Generation, vol. 13, no. 3, pp. 427-437, 25 2 2019.
multilevel converters—state of the art, challenges, and requirements in [25] M. Jalhotra, L. K. Sahu, S. P. Gautam and S. Gupta, “Reliability and
industrial applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. energy sharing analysis of a fault-tolerant multilevel inverter topology,”
2581-2596, Aug. 2010. IET Power Electron., vol. 12, no. 4, pp. 759-768, 10 4 2019.
[5] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo and M. A. [26] E. Jamshidpour, P. Poure and S. Saadate, “Photovoltaic systems reliability
M. Prats, “The age of multilevel converters arrives,” IEEE Ind. Electron. improvement by real-time FPGA-based switch failure diagnosis and fault-
Magazine, vol. 2, no. 2, pp. 28-39, June 2008. tolerant dc–dc converter,” IEEE Trans. Ind. Electron., vol. 62, no. 11, pp.
[6] B. Mirafzal, “Survey of fault-tolerance techniques for three-phase voltage 7247-7255, Nov. 2015.
source inverters,” IEEE Trans. Ind. Electron., vol. 61, no. 10, pp. 5192- [27] S. Siouane, S. Jovanoviü, P. Poure and E. Jamshidpour, “An efficient fault
5202, Oct. 2014. tolerant cascaded step-up step-down converter for solar pv modules,”
[7] P. Lezana, J. Pou, T. A. Meynard, J. Rodriguez, S. Ceballos and F. 2018 IEEE International Conference on Environment and Electrical
Richardeau, “survey on fault operation on multilevel inverters,” IEEE Engineering and 2018 IEEE Industrial and Commercial Power Systems
Trans. Ind. Electron., vol. 57, no. 7, pp. 2207-2218, July 2010. Europe (EEEIC / I&CPS Europe), Palermo, 2018, pp. 1-5.
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE
[28] M. M. Haji-Esmaeili, M. Naseri, H. Khoun-Jahan and M. Abapour, Conference on Electrical Machines & Power Electronics (ACEMP),
“Fault-tolerant and reliable structure for a cascaded quasi-Z-source dc–dc 2015, pp. 304-310.
converter,” IEEE Trans. Power Electron., vol. 32, no. 8, pp. 6455-6467,
Aug. 2017.
[29] K. Ambusaidi, V. Pickert and B. Zahawi, “New circuit topology for fault
tolerant h-bridge dc–dc converter,” IEEE Trans. Power Electron., vol. 25,
no. 6, pp. 1509-1516, June 2010.
[30] J. Amini and M. Moallem, “A fault-diagnosis and fault-tolerant control Haider Mhiesan received his [Link]. degree in
scheme for flying capacitor multilevel inverters,” IEEE Trans. Ind. Electrical Engineering from Kufa University, Iraq, in
Electron., vol. 64, no. 3, pp. 1818-1826, March 2017. 2007. He received his M.S. degrees in electrical
[31] M. Farhadi, M. T. Fard, M. Abapour and M. T. Hagh, “dc–ac converter- engineering from the University of Arkansas in 2016.
fed induction motor drive with fault-tolerant capability under open- and He is a graduate assistant at the University of
short-circuit switch failures,” IEEE Trans. Power Electron., vol. 33, no. Arkansas for the Research Center on GRid-connected
2, pp. 1609-1621, Feb. 2018. Advanced Power Electronic Systems (GRAPES). His
[32] R. V. Nemade, J. K. Pandit and M. V. Aware, “Reconfiguration of T-type current research interests include multilevel inverters,
inverter for direct torque controlled induction motor drives under open- transformerless grid-tied inverters, grid connected
switch faults,” IEEE Trans. Ind. Appl., vol. 53, no. 3, pp. 2936-2947, photovoltaic inverters, reconfigurable multilevel inverters and protection
May-June 2017. systems. He serves as reviewer for IEEE Transactions on Power Electronics,
[33] B. P. Reddy, M. Rao A, M. Sahoo and S. Keerthipati, “A fault-tolerant International Transactions on Electrical Energy Systems, Energies, Applied
multilevel inverter for improving the performance of a pole–phase Science and IEEE Journal of Emerging and Selected Topics in Power
modulated nine-phase induction motor drive,” IEEE Trans. Ind. Electron., Electronics.
vol. 65, no. 2, pp. 1107-1116, Feb. 2018.
[34] W. Chen, E. Hotchkiss and A. Bazzi, “Reconfiguration of NPC multilevel Yuqi Wei (S’18) was born in Henan, China, in 1995.
inverters to mitigate short circuit faults using back-to-back switches,” He received his B.S. degree in Electrical Engineering
CPSS Trans. Power Electron. and Appl., vol. 3, no. 1, pp. 46-55, March from Yanshan University, Hebei, China, in 2016, and
2018. his M.S. degree in Electrical Engineering from
[35] M. Aly, E. M. Ahmed and M. Shoyama, “A new single-phase five-level University of Wisconsin-Milwaukee (UWM),
inverter topology for single and multiple switches fault tolerance,” IEEE Wisconsin, U.S.A., in 2018. He received another M.S.
Trans. Power Electron., vol. 33, no. 11, pp. 9198-9208, Nov. 2018. degree in Electrical Engineering from Chongqing
[36] R. A. Madhukar, K. Sivakumar, “A Fault-tolerant single-phase five-level University, Chongqing, China, in 2019. He is currently
inverter for grid-independent PV systems”, IEEE Trans. Ind. Electron., working toward the Ph.D. degree at the University of
vol. 62, no. 12, pp. 7569-7577, Dec. 2015. Arkansas, Arkansas, U.S.A. His current research interests include topology,
[37] S. K. Maddugari, V. B. Borghate, S. Sabyasachi and R. R. Karasani, “A modelling and control of DC/DC power converters and power factor correction
fault tolerant cascaded multilevel inverter topology for open circuit faults AC/DC converters. He has published more than 20 peer-reviewed journal and
in switches,” IEEE Transportation Electrification Conference (ITEC- conference papers. Mr. Wei serves as reviewer for IEEE Transactions on
India), Pune, 2017, pp. 1-5. Industrial Electronics, IEEE Transactions on Industry Applications and IET
[38] S. K. Maddugari, V. B. Borghate, S. Sabyasachi and R. R. Karasani, “A Power Electronics.
Linear-Generator-Based Wave Power Plant Model Using Reliable
Multilevel Inverter,” IEEE Trans. Ind. Appl., vol. 55, no. 3, pp. 2964- Yam P. Siwakoti (S’10–M’14–SM’18) received the
2972, May-June 2019. [Link]. degree in electrical engineering from the
[39] M. M. Haji-Esmaeili, M. Naseri, H. Khoun-Jahan and M. Abapour, National Institute of Technology, Hamirpur, India, in
“Fault-tolerant structure for cascaded H-bridge multilevel inverter and 2005, the M.E. degree in electrical power engineering
reliability evaluation,” IET Power Electron., vol. 10, no. 1, pp. 59-70, 1 from the Norwegian University of Science and
20 2017. Technology, Trondheim, Norway, and Kathmandu
[40] H. K. Jahan, F. Panahandeh, M. Abapour and S. Tohidi, “Reconfigurable University, Dhulikhel, Nepal, in 2010, and the Ph.D.
multilevel inverter with fault-tolerant ability,” in IEEE Trans. Power degree in Electronic Engineering from Macquarie
Electron., vol. 33, no. 9, pp. 7880-7893, Sept. 2018. University, Sydney, Australia, in 2014.
[41] M. Aleenejad, H. Iman-Eini and S. Farhangi, “Modified space vector He was a postdoctoral fellow at the Department of Energy Technology,
modulation for fault-tolerant operation of multilevel cascaded H-bridge Aalborg University, Denmark (2014-2016). He was a visiting scientist at the
inverters,” IET Power Electron., vol. 6, no. 4, pp. 742-751, April 2013. Fraunhofer Institute for Solar Energy Systems, Freiburg, Germany
[42] P. Moamaei, H. Mahmoudi and R. Ahmadi, “Fault-tolerant operation of (2017/2018). He is also a recipient of the prestigious Green Talent Award from
cascaded H-Bridge inverters using one redundant cell,” 2015 IEEE Power the Federal Ministry of Education and Research, Germany in 2016.
and Energy Conference at Illinois (PECI), Champaign, IL, pp. 1-5, 2015. Currently he is a Senior Lecturer in the Faculty of Engineering and
[43] H. Mhiesan et al., “A method for open-circuit faults detecting, identifying, Information Technology, University of Technology Sydney, Australia. He
and isolating in cascaded h-bridge multilevel inverters,” in IEEE serves as an Associate Editor of three major journals of IEEE (IEEE
International Symposium on Power Electronics for Distributed TRANSACTIONS ON POWER ELECTRONICS, IEEE TRANSACTIONS ON INDUSTRIAL
Generation Systems (PEDG), pp. 1-5, Charlotte, NC, 2018. ELECTRONICS and IEEE Journal of Emerging and Selected Topics in Power
[44] H. Mhiesan, R. McCann, C. Farnell and A. Mantooth, "Novel Circuit and Electronics) and the IET Power Electronics. He is also a peer review college
Method for Fault Reconfiguration in Cascaded H-Bridge Multilevel member of Engineering and Physical Science Research Council (EPSRC), UK.
Inverters," 2019 IEEE Applied Power Electronics Conference and
Exposition (APEC), Anaheim, CA, USA, 2019, pp. 1800-1804. H. Alan Mantooth (S'83 - M'90 - SM'97 – F’09)
[45] H. Salimian and H. Iman-Eini, "Fault-Tolerant Operation of Three-Phase received the B.S. and M.S. degrees in electrical
Cascaded H-Bridge Converters Using an Auxiliary Module," IEEE engineering from the University of Arkansas in 1985
Transactions on Industrial Electronics, vol. 64, no. 2, pp. 1018-1027, Feb. and 1986, respectively, and the Ph.D. degree from the
2017. Georgia Institute of Technology in 1990. He then
[46] B. Hemanth Kumar, Makarand M. Lokhande, Raghavendra Reddy joined Analogy, a startup company in Oregon, where
Karasani and Vijay B. Borghate, “Fault Tolerant operation of CHB he focused on semiconductor device modeling and the
Multilevel based on SVM technique using an auxiliary unit,” Journal of research and development of modeling tools and
Power Electronics (JPE), vol. 18, no.1, pp. 56-69, Jan 2018 techniques. In 1998, he joined the faculty of the
[47] B. Gadalla, E. Schaltz and F. Blaabjerg, "A survey on the reliability of Department of Electrical Engineering at the University of Arkansas,
power electronics in electro-mobility applications," 2015 Intl Aegean Fayetteville, where he currently holds the rank of Distinguished Professor. His
research interests now include analog and mixed-signal IC design & CAD,
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE
semiconductor device modeling, power electronics, and power electronic
packaging. Dr. Mantooth helped establish the National Center for Reliable
Electric Power Transmission (NCREPT) at the UA in 2005. Professor
Mantooth serves as the Executive Director for NCREPT as well as two of its
centers of excellence: the NSF Industry/University Cooperative Research
Center on GRid-connected Advanced Power Electronic Systems (GRAPES)
and the Cybersecurity Center on Secure, Evolvable Energy Delivery Systems
(SEEDS) funded by the U.S. Department of Energy. In 2015, he also helped to
establish the UA’s first NSF Engineering Research Center entitled Power
Optimization for Electro-Thermal Systems (POETS) that focuses on high
power density systems for transportation applications. Dr. Mantooth holds the
21st Century Research Leadership Chair in Engineering. He serves as
Immediate Past-President for the IEEE Power Electronics Society in 2019-20.
Dr. Mantooth is a Fellow of IEEE, a member of Tau Beta Pi and Eta Kappa Nu,
and registered professional engineer in Arkansas.