UNIT 2
Bus Cycles and System
Architecture
1. Data bus pins (D0 to D31) :-
Bidirectional i.e can send and receive data.
BE# used to enable signal to access data bits.
2. Address bus pins (A2 to A31) :-
Unidirectional i.e. only send address
30 address pins & 4 byte enable pins.
3. Byte enable pins :-
These signals is to select the access of byte, word, double word
of data. These signal generated internally by A0 and A1
Bus status pins:-
1. Address data strobe:- It is active low signal. ADS signal used for latching address to external
latches.
2. W/R# :- If W/R=0 data is to be read from memory or I/O
=1 data is to be written on memory or I/O device.
3. M/IO# :- if M/IO = 1 memory access
if M/IO = 0 I/O device
During I/O operation address bus contains 16 bit I/O address A2-A15
4. D/C# :- This signal indicates whether current bus cycle in progress is data cycle
or control cycle
if D/C = 1 Data cycle
if D/C = 0 Control cycle
5. LOCK :- logic 0 on this pin will lock up the masters and the shared resourses in
80386DX system.
BUS control pins:-
1. READY# : The ready signals indicates to the CPU that the previous bus cycle has
been terminated and the bus is ready for the next cycle. The signal is used to insert
WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU.
2. NA# : The next address input pin, if activated, allows address pipelining, during
80386 bus cycles.
Interupt interface pins :-
1. INTR : This interrupt pin is a maskable interrupt, that can be masked using the IF
of the flag register.
2. NMI : A valid request signal at the non-maskable interrupt request input pin
internally generates a non-maskable interrupt of type2.
3. RESET : A high at this input pin suspends the current operation and restart the
execution from the starting location.
4. N / C : No connection pins are expected to be left open while connecting the 80386
in the circuit
DMA interface pins :-
1. HOLD : The bus hold input pin enables the other bus masters to gain control of the
system bus if it is asserted.
2. HLDA : The bus hold acknowledge output indicates that a valid bus hold request
has been received and the bus has been relinquished by the CPU.
Co-processor interface pins :-
1. BUSY# :The busy input signal indicates to the CPU that the coprocessor
is busy with the allocated task.
2. ERROR#:The error input pin indicates to the CPU that the coprocessor
has encountered an error while executing its instruction.
3. PEREQ: The processor extension request output signal indicates to the
CPU to fetch a data word for the coprocessor.
EFLAG of 80386DX
The flags may be considered in three groups: the status flags, the control
flags, and the systems flags.
Status Flags:-
1. CF: carry flag: this bit is set by arithmetic instr that generates a carry or borrow.
2. PF: Parity flag: set by instr if the LSB of 8 bit destination operand consists of an even
number of 1’s.
3. AF: Auxiliary carry flag: this bit is set by instr if there is a carry or borrow after nibble
addition or subtraction.
4. ZF: Zero flag: this bit is set to 1, if result of an operation is 0. Ex:- in cmp instr if result
is 0 then ZF=1
5. SF: Sign flag: the signed numbers can be represented with a combination of sign and
magnitude. The MSB of a number indicates sign of number. The MSB of a result is
copied into SF. If SF=1 the result of execution of an instr is negative number.
6. OF: Overflow flag: this flag is set to indicate that the signed result is out of range.
Control Flag
1. DF (Direction Flag, bit 10): controls the direction of string instruction. •
Setting DF causes string instructions to autodecrement; that is, to process
strings from high addresses to low addresses. (if DF=1 then ESI and EDI are
dec by 1) • Clearing DF causes string instructions to autoincrement, or to
process strings from low addresses to high addresses. (if DF=1 then ESI and
EDI are dec by)
2. TF:Trap flag: if TF is set (TF=1), it enables trapping through the chip
debugging features. The 386 goes into single step mode where it can execute
one instr at a time.
3. IF: Interrupt flag: this bit controls the operation of INTR (Interrupt request)
input pin of mp. If IF=1, the INTR pin is enabled and if IF=0 then INTR pin
is disabled. The state of this flag is controlled by STI and CLI instr.
System Flags
These flags indicate the current status of the mp. They are used by OS not
by user programs.
1. IOPL: Input/Output priviledge level: its 2 bit. Used in protected
mode of 386. it holds the priviledge level from 0 to 3 at which the code
is running in order to execute any I/O related instr.
2. NT: Nested task flag: Used in protected mode. This bit is set when
one task invokes another task. For eg: prog A is calling prog B.
3. RF: Resume flag: this bit allows selective masking (avoid) of some
exceptions when a code is debugged.
4. VM virtual 8086 mode: this flag indicates the operating mode of the
386. the flag is set when 386 switches from the protected mode to
virtual 8086 mode
Control Register
Control registers CR0, CR2, and CR3.
EM (Emulation, bit 2) :-EM indicates whether coprocessor functions are to be emulated.
ET (Extension Type, bit 4) :-ET indicates the type of coprocessor present in the system (80287 or 80387 ) .
MP (Math Present, bit 1) :-MP controls the function of the WAIT instruction, which is used to coordinate a coprocessor .
PE (Protection Enable, bit 0) :-Setting PE causes the processor to begin executing in protected mode. Resetting PE
returns to real-address mode .
PG (Paging, bit 31) :-PG indicates whether the processor uses page tables to translate linear addresses into physical
addresses .
TS (Task Switched, bit 3) :-
Debug Register :-
1. Debug Address Registers (DR0-DR3)
➢ Each of these registers contains the linear address associated with one of four
breakpoint conditions.
➢ Each breakpoint condition is further defined by bits in DR7.
➢ The debug address registers are effective whether or not paging is enabled. The
addresses in these registers are linear addresses.
➢ If paging is enabled, the linear addresses are translated into physical addresses by
the processor's paging mechanism.
➢ If paging is not enabled, these linear addresses are the same as physical addresses.
2. Debug Control Register (DR7)
R/W RW bits in DR7
00 Break on instruction execution only
01 Break on data writes only
10 Undefined
11 Break on data reads or writes but not instruction fetches
LEN LEN bits in DR7
00 1 byte length
01 1 word (2 byte) length
10 reserved
11 1 double word (4 byte length)
2. Debug Control Register (DR6) :-
When the processor detects an enabled debug exception, it sets the low-
order bits of this register (B0 thru B3) before entering the debug exception
handler.
BT :- Associated with trap bit of TSS (Task state segment : it is the area of
memory that holds the tasks registers state and other information.)
BS :- Associated with trap bit of EFLAG
BD :- It sets if the next instruction will read or write one of the eight
debug registers.
Translation Lookaside Buffer (TLB)
The 80386 provides a mechanism for testing the Translation Lookaside Buffer
(TLB), the cache used for translating linear addresses to physical addresses.
Although failure of the TLB hardware is extremely unlikely, users may wish to
include TLB confidence tests among other power-up confidence tests for the
80386.
Structure of the TLB
➢ The TLB is a four-way set-associative
memory.
➢ There are four sets of eight entries each.
➢ Each entry consists of a tag and data.
➢ Tags are 24-bits wide. They contain the
high-order 20 bits of the linear address, the
valid bit, and three attribute bits.
➢ The data portion of each entry contains the
high-order 20 bits of the physical address.
