A Novel Liberty based Approach for Early Power Estimation for Brand New Technology Nodes

Abstract

Power consumption in the SoC has become an important specification in both low power
consumption SoCs where applications require SoCs to be run on battery and also in high
power consumption SoCs where the power dissipation raising the junction temperature is a
major concern. Product teams are required to estimate fairly accurate power consumption of
the design pretty early on during the feasibility stage for a variety of product related decisions.
The competitiveness of these decisions is directly driven by the accuracy of the early power
estimation methodology especially since the estimation is done much prior to the actual design
start.
This paper discusses one such approach to accurately estimate the power consumption of any
design, much before the design actually goes on the floor.

Problem Definition

Early estimation has been a subject of much research and because of the uncertainty involved
in the early estimation process, the estimation techniques invariably lead to inaccurate
estimation. The stakes involved are very high since any wrong estimation can either result in
the design getting scrapped or the customer walking over to the competition for presumably
lower power design. Hence utmost care is required in ensuring that estimation done at an early
stage is a good indicator of the eventual design performance. This becomes even more
important for the first design in any process node since there is not much cushion available in
the form of silicon results in that particular node.

Some of the conventional power estimation approaches used for a brand new technology node
are based on

 Using a ‘per-gate-per-Mhz’ average factor based on an older technology silicon results

 Scaling the ‘per-gate-per-Mhz’ of older technology to the newer technology node, using the gate
density scaling between the two technology nodes
 Estimating the power of the design using the equation

Power = Scaled-per-gate-per-Mhz x Number of gates x Frequency

Such conventional methods used for calculating the per-gate-per-Mhz factor can lead to
inaccuracies since these take into account only the process scaling. However the power
dissipation of any design is also largely dependent on the implementation of the design in
terms of

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  Transition times implemented (affects the short circuit power)
 Load seen by the gates (affects the switching power)

The need therefore is to have an approach that is non-theoretical, practical and more
importantly takes into account the implementation topology of the design and that too at an
early time when the design is far away from even the start of the implementation.

Proposed Approach

The proposed approach estimates ‘per-gate-per-Mhz’ taking into account both the major
parameters that can affect the power dissipation

 Process scaling
 Design Implementation topology

The most important aspect of the proposed methodology is that it takes into account the
design implementation topology even before the design implementation has actually been
started. It, therefore, best addresses the early power estimation needs of the new process
node. The methodology uses the liberty files characterized for the new process technology
node as a key input and based on these liberty files, it estimates the process scaling from the
old technology node to the newer technology node and also estimates the affect of the design
topology supported by the liberty files. The parameter ‘per-gate-per-Mhz’ is thus estimated
considering both the process and the design implementation.

It is to be noted that the liberty characterization of a standard cell for any process node
contains the information on

 The short circuit power consumption (rise and fall) for different combinations of slews
and loads corresponding to every pin of the cell and
 The maximum and minimum load that the process best supports

Steps in the Proposed Approach

1. Taking into account the futuristic design implementation topology

2. Process scaling

1. Taking into account the futuristic design implementation topology

In the actual design implementation flow, the implementation is restricted to

remain within the bounds as specified by the characterization. This means that if
the bounding parameters as specified in the cell characterization are taken into
account for estimating the short circuit power and the switching power, the

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 actual future design implementation can be mimicked well early on. This is so
because the design timing constraints limits for slew, for any technology, are
relative to the liberty characterized values. Also the typical placement and
routing topology which governs average load seen by a logic gate is relative to
the minimum and maximum load values characterized for the process node. This
is accomplished through the steps outlined below

1a. Identification of Relevant Slew/Load Combinations

Bounding values of slew and load are identified. Some sample entries are shown
below

 Fast slew, Min load (Fs, MinL)

 Fast slew , Max load (Fs, MaxL)
 Mid slew, Min load (Ms, MinL)
 Mid slew, Max load (Ms, MaxL)
 Slow slew, Min load (Ss, MinL)
 Slow slew, Max load (Ss, MaxL)

1b. Computation of Rise/Fall Short Circuit Power

For the combinations of slew and load, as identified in step1a, the average
internal power for rise and fall transitions is computed. This corresponds to the
average short circuit power.

1c. Computation of Switching Power

For the combinations of load, as identified in step1a, the switching power is

computed using the standard formula

Switching power = 0.5*C*V*V*f*S. Where

“C” is the capacitive load on the output of standard cell

“V” is the voltage,

“f” is the frequency of operation of the cell (taken as 1 Mhz)

“S” is the output switching activity of the cell.

1d. Computation of the Total Liberty Based Dynamic Power

Finally, the total dynamic power is computed using the short circuit and
switching power computed in step1b and step1c

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 Total Dynamic power (Fs , MinL) =Internal Power(Fs , MinL) + Switching power(MinL)

Total Dynamic power (Fs , MaxL) =Internal Power(Fs , MaxL)+Switching power(MaxL)

Total Dynamic power (Ms , MinL) =Internal Power(Ms , MinL) + Switching power(MinL)

Total Dynamic power (Ms , MaxL) =Internal Power(Ms , MaxL)+Switching power(MaxL)

Total Dynamic power (Ss , MinL) =Internal Power(Ss , MinL) + Switching power(Fs,MinL)

Total Dynamic power (Ss , MaxL) =Internal Power(Ss , MaxL)+Switching power(Fs,MaxL)

The dynamic power as obtained in step 1d is averaged to give the factor ‘liberty-
based-per-gate-per-Mhz’

2. Process Scaling

Process scaling involves using the silicon based average ‘per-gate-per-Mhz’

factor from the older matured process and then scaling it into the new
technology node. This includes the following steps

2a. Using a Reference Silicon Based Factor for a Technology

The silicon based ‘per-gate-per-Mhz’ number from a matured technology is used

as a reference. The liberty based average dynamic power for the matured
process is calculated using the steps 1a through 1d as mentioned earlier and is
compared to the silicon based ‘per-gate-per-Mhz’ to compute the ‘liberty-to-
silicon-scaling-factor’. This scaling factor indicates the factor by which the liberty
based average dynamic power varies from silicon. The variation is due to the
difference in average load of a gate across the design and also the average
switching of a gate in a typical application across the design.

2b. Calculating the ‘per-gate-per-Mhz’ Factor for New Process Node

The liberty-to-silicon-scaling-factor computed for a matured process in step 2a is

used in conjunction with the liberty based dynamic power (as computed in step
1a through 1d) to estimate the ‘per-gate-per-Mhz’ factor for the new process
node.

Figure 1 shows the flow chart of the proposed approach as described so far.

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 Figure 1 – Proposed Approach Flow Chart

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Example of Usage of the Proposed Approach

Let us assume that

Silicon based per-gate-per-Mhz for matured process = Psi-mat

Liberty based per-gate-per-Mhz (1a through 1d) for matured process = Plib-mat

Then, ‘liberty-to-silicon-scaling-factor’ for matured process = (Plib-mat)/Psi-mat

Liberty based per-gate-per-Mhz (1a through 1d) for new process = Plib-new

Early estimated per-gate-per-Mhz for new process = ((Plib-new) * (Psi-mat))/ (Plib-mat)

Summary

Any early estimation approach that is based on only process scaling for estimating the
power consumption of a design has inaccuracies associated with it since the power
consumption of a design is greatly dependent on the eventual design implementation.
Hence, there is a need to use an approach that accounts for both the process scaling and
the design implementation when moving from one technology node to another. This paper
discusses one such approach that takes into account the “future” design implementation
topology well in advance in modeling power estimation at an early stage. The estimation
obtained using the proposed approach correlated to be within 15% of the eventual design
based power estimation results.

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