Latches and Flip Flops

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Flip flop is an important basic memory element for digital circuit. Flip-flop is designed by
assembling different logic gates. Single logic gate does not have any information storing
capacity but by combining different such gates one can make such a digital circuit which
can store digital information. Flip flop is such circuit. There are different types of flip
flop with different characteristics for different application. Flip-flop is the basic building
blocks of most sequential circuits. Flip-flop (FF), is also known as a bistable multivibrator,
because it has two stable states. It can remain in either of the states indefinitely. Its state
can be changed by applying the proper triggering signal. Flip flop is one-bit memory

element. There are two outputs in a flip-flop generally marked as Q and . Either of Q

and can be used as output but normal practice is to take Q as output port and
as inverted output port.
It is to be noted here that a flip flop has always one out complement of other output. The
state of a flip-flop is normally determined by the condition of output Q. If Q = 1 the flip-
flop is said to be in HIGH state or logic 1 state or SET state. When, Q = 0 the state of flip
flop is said to be in LOW state or logic 0 state or RESET state or CLEAR state.

The figure below shows a block diagram of a flip flop. It shows a flip-flop may have one or
more inputs but only two outputs. The combination of inputs which alter the outputs or
state of flip flop is referred as excitation. The excitation is used to switch the flip flop from
one state to other. But the typical feature of flip flop is that once the state of flip flop is
changed by applying, excitation, it remains unaltered even the excitation is removed from
input ports. Hence, momentary application of excitation is enough to change the state a
flip-flop. This is how flip flop behaves as memory element. When, Q = 1 it stores a 1 and
when, Q = 0, it stores a 0. Flip-flops are the basic components of shift registers and
counters. Flip flop is a sequential circuit hence it can be either synchronous or
asynchronous. When inputs are controlled by clock pulse it is normally referred as flip flop.
Here the inputs are applied but not acted until clock pulse appears and enable the inputs.
When the same circuit is made asynchronous that is its inputs is not controlled by clock
pulse, it is called latch. It is SET or RESET instantaneously on receiving the input signal.
Latch can act independently of clock signal.

S R Flip Flop S R Latch

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Most simple type of flip flop is S R Flip Flop. It has two inputs S and R and two outputs Q

and . The state of this latch is determined by condition of Q. If Q is 1 the latch is said
 to be SET and if Q is 0 the latch is said to be RESET. This S R Latch or Flip flop can be
designed either by two cross-coupled NAND gates or two-cross coupled NOR gates. When
we design this latch by using NOR gates, it will be an active high S-R latch. That means it
is SET when S = 1. When we design this latch by using NAND gates, it will be an active low
S-R latch. That means it is SET when S = 0. S R Flip Flop is also called SET RESET Flip
Flop.
Figure below shows the logic circuit of S R latch.

In the above logic circuit if S = 1 and R = 0, Q becomes 1. Let us explain how.

 NOR gate always gives output 0 when at least one of the inputs is 1.

 So when S is applied as 1 the output of gate G2 i.e. is 0 irrespective of the condition

of second input Q to the gate.

 Now is input of gate G1 so both the inputs of G1 become 0 as R is already 0. So,

output of G1 is now or 1.

 So whatever may be the previous condition of Q, it always becomes Q = 1 and = 0

when, S = 1 and R = 0. This is called SET condition of the latch.
In the above logic circuit if S = 0 and R = 1, Q becomes 0. Let us explain how.
 As we already said, a NOR gate always gives output 0 when at least one of the inputs is
1.
 So when R is applied as 1, the output of gate G1 i.e. Q is 0 irrespective of the condition
of second input to the gate.
 So, whatever may be the previous condition of Q, it always becomes 0 this 0 is then fed
back to input of gate G2. As here S is already 0, both inputs of G2 are 0. Hence output
 of G2 i.e. will be 1. So, Q = 0 and = 1 when, S = 0 and R = 1. This is called
RESET condition of the latch.
In the above logic circuit if S = 0 and also R = 0, Q remains same as it was. Let us
explain how.
 First suppose Q is previously 1.
 Now the inputs of G2 are 0 and 1 as S=0 and Q=1. So output of G2 i.e. is
or 0.

 Now both inputs of G1 are 0 as R=0 and =0. So output of G1 i.e. Q is or 1.

 Now suppose Q is previously 0.

 Now both inputs of G2 are 0 and 1 as S = 0 and Q = 0. So output of G2 i.e.

is or 1.

 Now the inputs of G1 are 0 and 1 as R=0 and = 1. So output of G1 i.e. Q is

or 0.
 So it is proved that Q remains same as it is when S = 0 and also R = 0 in S R latch
or flip flop.
In the above logic circuit if S = 1 and also R = 1, the condition of Q is totally
unpredictable. Let us explain how.
 First suppose Q is previously 1.
 Now both inputs of G2 are 1 as S = 1 and Q = 1. So output of G2 i.e. is or
0.

 Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q

is or 0. That means Q is changed.

 Now Q is 0. So inputs of G2 are 1 and 0 as S = 1 and Q = 0. So output of G2 i.e.

is or 0. That means is unchanged.

 Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q

is or 0. That means Q is unchanged.

So, when both S and R are 1, it becomes unpredictable whether the value of output Q will
be changed or unchanged. This condition of S R latch normally avoided. As the latch is SET
when S = 1(HIGH), the latch is called Active High S R Latch. There is other type of latch
which is SET when, S = 0 (LOW), and this latch is known as Active Low S R Latch.

S R Flip Flop S R Latch

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Most simple type of flip flop is S R Flip Flop. It has two inputs S and R and two outputs Q

and . The state of this latch is determined by condition of Q. If Q is 1 the latch is said
to be SET and if Q is 0 the latch is said to be RESET. This S R Latch or Flip flop can be
designed either by two cross-coupled NAND gates or two-cross coupled NOR gates. When
we design this latch by using NOR gates, it will be an active high S-R latch. That means it
is SET when S = 1. When we design this latch by using NAND gates, it will be an active low
S-R latch. That means it is SET when S = 0. S R Flip Flop is also called SET RESET Flip
Flop.
Figure below shows the logic circuit of S R latch.
 In the above logic circuit if S = 1 and R = 0, Q becomes 1. Let us explain how.
 NOR gate always gives output 0 when at least one of the inputs is 1.

 So when S is applied as 1 the output of gate G2 i.e. is 0 irrespective of the condition

of second input Q to the gate.

 Now is input of gate G1 so both the inputs of G1 become 0 as R is already 0. So,

output of G1 is now or 1.

 So whatever may be the previous condition of Q, it always becomes Q = 1 and = 0

when, S = 1 and R = 0. This is called SET condition of the latch.
In the above logic circuit if S = 0 and R = 1, Q becomes 0. Let us explain how.
 As we already said, a NOR gate always gives output 0 when at least one of the inputs is
1.
 So when R is applied as 1, the output of gate G1 i.e. Q is 0 irrespective of the condition
of second input to the gate.
 So, whatever may be the previous condition of Q, it always becomes 0 this 0 is then fed
back to input of gate G2. As here S is already 0, both inputs of G2 are 0. Hence output

of G2 i.e. will be 1. So, Q = 0 and = 1 when, S = 0 and R = 1. This is called

RESET condition of the latch.
In the above logic circuit if S = 0 and also R = 0, Q remains same as it was. Let us
explain how.
 First suppose Q is previously 1.
 Now the inputs of G2 are 0 and 1 as S=0 and Q=1. So output of G2 i.e. is
or 0.

 Now both inputs of G1 are 0 as R=0 and =0. So output of G1 i.e. Q is or 1.

 Now suppose Q is previously 0.

 Now both inputs of G2 are 0 and 1 as S = 0 and Q = 0. So output of G2 i.e.

is or 1.

 Now the inputs of G1 are 0 and 1 as R=0 and = 1. So output of G1 i.e. Q is

or 0.
 So it is proved that Q remains same as it is when S = 0 and also R = 0 in S R latch
or flip flop.
In the above logic circuit if S = 1 and also R = 1, the condition of Q is totally
unpredictable. Let us explain how.
 First suppose Q is previously 1.
 Now both inputs of G2 are 1 as S = 1 and Q = 1. So output of G2 i.e. is or
0.

 Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q

is or 0. That means Q is changed.

 Now Q is 0. So inputs of G2 are 1 and 0 as S = 1 and Q = 0. So output of G2 i.e.

is or 0. That means is unchanged.

 Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q

is or 0. That means Q is unchanged.

So, when both S and R are 1, it becomes unpredictable whether the value of output Q will
be changed or unchanged. This condition of S R latch normally avoided. As the latch is SET
when S = 1(HIGH), the latch is called Active High S R Latch. There is other type of latch
which is SET when, S = 0 (LOW), and this latch is known as Active Low S R Latch.

Active Low S R Latch and Flip Flop

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There is one type of latch which is SET when S = 0(LOW), and this latch is known
as Active Low S R [Link] latch is normally designed by using NAND gates. The
logical circuit is shown below.
 In the above logic circuit if S = 0 and R = 1, Q becomes 1. Let us explain how.
 NAND gate always gives output 1 when at least one of the inputs is 0.
 So, when S is applied as 0 the output of gate G1 i.e. Q is 1 irrespective of the condition

of second input to the gate.

 Now, Q is input of gate G2 so both the inputs of G2 become 1 as R is already 1. So
output of G2 is now or 0.

 So whatever may be the previous condition of Q, it always becomes Q = 1 and = 0

when S = 0 and R = 1. This is called SET condition of the latch.
In the above logic circuit if S = 1 and R = 0, Q becomes 0. Let us explain how.
 As we already said, a NAND gate always gives output 1 when at least one of the inputs
is 0.

 So when R is applied as 0, the output of gate G2 i.e. is 1 irrespective of the

condition of second input Q to the gate.

 So whatever may be the previous condition of , it always becomes 1 this 1 is then

fed back to input of gate G1. As here S is already 1, both inputs of G1 are 1. Hence

output of G1 i.e. Q will be 0. So Q = 0 and = 1 when, S = 1 and R = 0. This is called

RESET condition of the latch.
In the above logic circuit if S = 1 and also R = 1, Q remains same as it was. Let us
explain how.
 First suppose Q is previously 1.
 Now both inputs of G2 are 1 as R = 1 and Q = 1. So output of G2 i.e. is or 0.

 Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q is

or 1.
 Now suppose Q is previously 0.

 Now the inputs of G2 are 1 and 0 as R = 1 and Q = 0. So output of G2 i.e. is

or 1.

 Now both inputs of G1 are 1 as S = 1 and = 1. So output of G1 i.e. Q is or 0.

 So it is proved that Q remains same as it is when, S = 1 and also R = 1.
In the above logic circuit if S = 0 and also R = 0, the condition of Q is totally
unpredictable. Let us explain how.
 First suppose Q is previously 0.
 Now both inputs of G2 are 0 as R = 0 and Q = 0. So output of G2 i.e. is or 1.

 Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is

or 1. That means Q is changed.

 Now Q is 1. So inputs of G2 are 0 and 1 as R = 0 and Q = 1. So output of G2 i.e.

is or 1. That means is unchanged.

 Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is
or 1. That means Q is unchanged.
So, when both S and R are 0, it becomes unpredictable whether the value of output Q will
be changed or unchanged. This condition of S R latch normally avoided.

Gated S R Latches or Clocked S R Flip Flops

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In latch we so far discussed can change its state instantaneously on the application of
required inputs conditions. They are asynchronous latches. On the other hand, a gated S-R
latch can only change its output state when there is an enabling signal along with required
inputs. That means the inputs can only act upon when the latch is enabled otherwise there
will be no change in output state even required inputs are applied. In other words, the
latch is active when ENABLE signal is HIGH and it is inactive when ENABLE signal is LOW.
This HIGH LOW enable signal is applied to the gated latch in the form of clocked pulses.
So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R [Link] this
latch responds to the applied inputs only when the level of the clock pulse is high, this type
of flip-flop is also called level triggered flip-flop. The logical circuit of a Gated S-R Latch
or Clocked S-R Flip-Flop is shown below.
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D Flip Flop or D Latch

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In Active High S-R Flip Flop when S and R both are 0, there will be no change in the output
of the latch and when both S and R are 1 the output of the latch is totally unpredictable. In
Active Low S-R Flip Flop when S and R both are 1, there will be no change in the output of
the latch and when both S and R are 0 the output of the latch is totally unpredictable. So if
both inputs of the flip-flop are same there will be either No Change or Invalid output
condition. So if we avoid these conditions of inputs there will be either SET or RESET
conditions. There are many applications, where only SET and REST conditions of the latch
are required. In those applications, we can use inputs (S&R) which are always the
complement of each other. This can be designed by a single input (S) to the latch and the
R input achieved by inverting this S. This single input is called Data input and it is labelled
with D.
This is why this type of single input Flip flop is called D-Flip Flop or D Latch. Basic logical
representation of D-flip flop is shown below.

D latch can be gated and then the logical circuit can be as follows
Gated D - Latch: There are many applications where separate S and R inputs not
required. In these cases by creating D flip-flop we can omit the conditions where S = R =
0 and S = R = 1. In D flip-flop if D = 1 then S = 1 and R = 0 hence the latch is set on the
other hand if D = 0 then S = 0, and R = 1 hence the latch is reset. We can make this latch
as gated latch and then it is called gated D-latch. Like gated S-R latch gated D flip-flop
also have ENABLE input. The difference from gated S-R latch is that it has only two inputs
D and ENABLE. The above said set and reset conditions of the latch is only seen in the
latch when the ENABLE or EN input is high. That means when D = 1 and EN = 1 the gated
latch D flip-flop is ENABLE and SET when D = 0 and EN = 1 the latch is ENABLE and RESET
but when EN = 0 the latch is DISABLE no question of SET REST. That means at EN = 0,
any change in input D does not affect the output (No Change Condition). Again SET means
output Q = 1 and RESET means Q = 0 so Q = D or output follows input when EN is High
and this is the reason for which it is , an LOW D input makes Q Low, i.e. resets the flip-flop
and a High D input makes Q High, i.e. sets the flip-flop. In other words, we can say that
the output Q follows the D input when EN is High. So, this latch is said to be transparent.
The logic diagram, the logic symbol and the truth table of a gated D-latch are shown in
Figure bellow.
J K Flip Flop
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JK flip-flop is a sequential bi-state single-bit memory device named after its inventor
by Jack Kil. In general it has one clock input pin (CLK), two data input pins (J and K) and
two output pins (Q and Q̅…) as shown by Figure 1. JK flip-flop can either be triggered upon
the leading-edge of the clock or on its trailing edge and hence can either be positive- or
negative- edge triggered, respectively.

In
order to have an insight over the working of JK flip-flop, it has to be realized interms of
basic gates similar to that in Figure 2 which expresses a positive-edge triggered JK flip-
flop using AND gates and NOR gates. Here it is seen that the output Q is logically anded
with input K and the clock pulse (using AND gate 1, A1) while the output Q̅ is anded with
the input J and the clock pulse (using AND gate 2, A2).
Further the output of A1 is fed as one of the inputs (X1) to the NOR gate 1, N1 whose other
input (Y1) is connected to output Q̅. Similarly NOR gate 2, N2 has its two inputs (X2 and Y2)
as output of A2 and output Q (respectively).

Initially let J = K = 0, Q = 0 and Q̅ = 1. Now consider the appearance of positive-edge of

the first clock pulse at the CLK pin of the flip-flop. This results in X1 = 0 and X2 = 0. Then
the output of N1 will become 0 as X1 = 0 and Q̅ = 1; while the output of N2 will become 1
as X2= 0 and Q = 0. Thus one gets Q = 0 and Q̅ = 1. However if one considers the initial
states to be J = K = 0, Q = 1 and Q̅ = 0, then X1 = X2 = 0 which results in Q = 1 and Q̅ =
0. This indicates that the state of flip-flop outputs Q and Q̅ remains unchanged for the case
of J = K = 0.
Now assume that J = 0, K = 1, Q = 0 and Q̅ = 1. Analyzing on the same grounds, one gets
X1 = X2 = 0 which further results in Q = 0 (and hence Q̅ = 1). For the same case if Q and
Q̅ were 1 and 0, respectively, then X1 = 1 and X2 = 0 which would result in Q = 0 (and
hence Q̅ = 1). This implies that if J = 0 and K = 1, then the flip-flop resets (Q = 0 and Q̅ =
1).
Next if J = 1, K = 0, Q = 1 and Q̅ = 0, then X1 = X2 = 0 which results in Q = 1 (and thus Q̅
= 0). For the same case if Q = 0 and Q̅ = 1, then X1 = 0, X2 = 1 which leads to Q̅ = 0 and
hence Q is forced to value 1. This means that for the case of J = 1 and K = 0, flip-flop
output will always be set i.e. Q = 1 and Q̅ = 0.
Similarly for J = 1, K = 1, Q = 1 and Q̅ = 0 one gets X1 = 1, X2 = 0 and Q = 0 (and hence
Q̅ = 1); and if Q changes to 0 and Q̅ to 1, then X1 = 0, X2 = 1 which forces Q̅ to 0 and
hence Q to 1. This indicates that for J = K = 1, flip-flop outputs toggle meaning which Q
changes from 0 to 1 or from 1 to 0, and these changes are reflected at the output pin Q̅
accordingly.
However it is to be noted that the state of the flip-flops remain unaltered if there is no
rising-edge of the clock at its input. All these details can be summarized as in Table I. The
wave forms pertaining to the same are presented by Figure 3. Moreover it is to be noted
that the working of negative edge triggered flip-flop is similar to that of positive-edge
triggered one except that the changes occur at the trailing edge of the clock pulse instead
of its leading edge.
 From the
truth table above one can arrive at the equation for the output of the J K flip-flop as (Table

II)
 In addition
to the basic input-output pins shown in Figure 1, J K flip-flop can also have special inputs
like clear (CLR) and preset (PR) (Figure 4). These can be used to bring the flip-flop to a
definite state from its current state. For example, the output can be made equal to 0 using
CLR pin while it can set to 1 using PR pin. However these pins can be either active high
(Figure 4a) or active low (Figure 4b) operated. The waveforms pertaining to positive-edge
triggered JK flip-flop with active high preset and clear pins are shown in Figure 5. Moreover
it is to be noted that these pins can be either synchronous or asynchronous in nature
meaning which the clear and set operations occur either depending on the clock (shown by
green lines) or no (shown by red lines), respectively. Further if the preset and clear pins
are active low, then the changes observed in the diagram occur at the instant when clear
and preset go low instead of high.

Master Slave Flip Flop

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Master Slave flip flop are the cascaded combination of two flip-flops among which the
first is designated as master flip-flop while the next is called slave flip-flop (Figure 1). Here
the master flip-flop is triggered by the external clock pulse train while the slave is
activated at its inversion i.e. if the master is positive edge-triggered, then the slave is
negative-edge triggered and vice-versa. This means that the data enters into the flip-
flop at leading/trailing edge of the clock pulse while it is obtained at the output pins during
trailing/leading edge of the clock pulse. Hence a master-slave flip-flop completes its
operation only after the appearance of one full clock pulse for which they are also known
as pulse-triggered flip-flops.

The internal structure of a master-slave JK flip-flop interms of NAND gates and an inverter
(to complement the clock signal) is shown in Figure 2. Here it is seen that the NAND
gate 1 (N1) has three inputs viz., external clock pulse (Clock), input J and output Q̅; while
the NAND gate 2 (N2) has external clock pulse (Clock), input K and output Q as its inputs.
Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross
connected gates N3 and N4. These four gates together (N1, N2, N3 and N4) form the
master-part of the flip-flop while a similar arrangement of the other four gates N 5, N6,
N7 and N8form the slave-part of it.
From figure it is also evident that the slave is driven by the outputs of the master (M1 and
M2), which is in accordance with its name master-slave flip-flop. Further the master is
active during the positive edge of the clock due to which M 1 and M2 change their states;
depending on the values of J and K. However at this instant the outputs of the overall
system (master-slave JK flip-flop) remains unchanged as the slave will be inactive due to
positive-edge of the clock pulse. Similar to this, the slave decides on its outputs Q and Q̅
depending on its inputs M1 and M2, during the negative edge of the clock during which the
master will be inactive.
The truth table corresponding to the working of the flip-flop shown in Figure 2 is given by
Table I. Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in
red boxes) appear during the positive-edge of the clock (red arrow). However at this
instant the slave-outputs remain latched or unchanged. The same data is transferred to
the output pins of the master-slave flip-flop (data enclosed in blue boxes) by the slave
during the negative edge of the clock pulse (blue arrow). The same principle is further
emphasized in the timing diagram of master-slave flip-flop shown by Figure 3. Here the
green arrows are used to indicate that the slave-output is nothing but the master-output
delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave flip-flop is
analogous to that of the master slave JK flip-flop explained here.
Read Only Memory | ROM
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 Read Only Memory (ROM) is a kind of memory which forms an integral part of many
electronic components including those of computers. The major trait of this memory is the
fact that, here, the number of reads are unrestricted while the number of writes are fixed.
This means that in a ROM, the user can store the data only once (usually done during
fabrication) or sometimes only a couple of times. However this stored data can be read
from it how many every times needed. Next, the information so stored in ROMs will not be
erased even if the power shuts down. As a result, they are referred to as permanent, non-
volatile memory devices.

Internally, ROM comprises of a row-column grid which will be connected by

the diodes depending on the programming bit received. This indicates that ROM is a hard-
wired memory device. As a consequence, one need not refresh its memory contents on a
timely-basis in order to keep-up the data stored, unlike RAM (Random Access Memory)
which demands for frequent refresh cycles. The single-write, multiple-read nature of ROM
makes it most suitable to store boot-up programs and the firmware applications which
require no/very less updates. Calculators, laser printers, washing machines and gaming
consoles are a few among the numerous appliances wherein ROM finds its place. Various
kinds of ROMs in existence are
1. Masked Read Only Memory (MROM)
These were the first set of ROMs developed which are hard-wired and read-only in
nature. MROM is programmed by the manufacturer during fabrication after which the
contents of the memory can never be changed. This is because, MROMs are fabricated
using masks (integrated circuits which have definite opaque and transparent areas)
which either allow or block the passage of light (like that of UV) during photolithography.
These devices are compact than any other kind of semiconductor memories for a given
bit and are preferred when the need is for mass production.

2. Programmable Read Only Memory (PROM)

PROMs in the market are blank ROMs and contain no pre-recorded instructions like
those of MROMs. These allow the user to program it only once, using PROM
programmers, after which their contents can never be changed. This is because, a
typical PROM with all 1's in it will be programmed to have 0's by blowing-off the fuses
using high voltage pulses, wherever required. As this is an irreversible process, PROMs
are one-time programmables.

3. Erasable and Programmable Read Only Memory (EPROM)

These devices comprise of an array of transistors characterized by floating-gates, which
are programmed one-by-one with the help of high-voltage pulses. However, such a
programmed EPROM can be erased by exposing them to strong ultra-violet (UV) light
for certain duration, after which they can be programmed once again. Nevertheless,
multiple-erase operations cause wearing out of the device due to which they lack the
unlimited reprogramming ability. These kind of memory devices are generally used to
store firmware programs which demand frequent upgrades.

4. Electrically Erasable and Programmable Read Only Memory (EEPROM)

EEPROMs can be programmed more than once, as they are capable of being erased
electrically. This means that they need not be removed from the system inorder to carry
on the process of erasing and programming. However writing into an EEPROM is a slow
process when compared to reading from it. Moreover they offer the flexibility of erasing
byte-by-byte or selected areas only, instead of entire chip as in the case of EPROMs.
Depending on this ability they can be classified as

1. Electrically Alterable Read Only Memory (EAROM)

This kind of EEPROM allows bit-wise modification. However writing process is
extremely slow and requires higher voltage than that for reading. Thus these are used
to store set-up information of the system or for similar applications which require rare
and/or partial rewriting.
2. Flash Read Only Memory (FROM)
These can be erased and reprogrammed much faster than EEPROMs and allow the
user to access multiple locations of the memory at the same time.

Application of Flip Flops

Registers
Registers are the devices which are meant to store the data. As known, each flip-flop can
store a single-bit of information. This means that by cascading n flip-flops, one can store n
bits of information. Such an arrangement is called an n-bit register. For example by
cascading three D flip-flops as shown in Figure 1, one can store three bits of information
(B3, B2 and B1), thus forming a 3-bit buffer register.

The data stored in the registers can be moved stage-wise within the registers and/or
in/out of the register by applying clock pulses. Such a register is called shift register.

There are various kinds of shift registers depending on the mode of data-shift viz., serial-in
serial-out register, serial-in parallel-out register, parallel-in serial-out register, parallel-in
parallel-out register. Further depending on the direction of data movement they can be
either left-shift and/or right-shift in nature, as shown by Figure 2.

Counters
Counters are the digital circuits which are used to count the number of events. These are
nothing but a series of flip-flops (JK or D or T) arranged in a definite manner. A single flip-
flop has two states 0 and 1, which means that it can count upto two. Thus one flip-flop
forms a 2-bit (or Modulo 2, MOD 2) counter. Similarly to count till 8, one needs to connect
3 (= 23) flip-flops in series as shown in Figure 3.
These counters can either be synchronous/asynchronous and/or positive/negative edge-
triggered depending on the connections provided at their clock inputs. Moreover by slightly
modifying the connections between the flip-flops, various other kinds of counters can be
designed viz., up-counter, down-counter, up/down counter, ring counter, johnson counter,
etc.

Event Detectors
Event detectors are the circuits which aid in determining the occurrence of a particular
event. These devices are required to change their state when an event occurs and should
further be held in the same state till that event gets cleared. Flip-flops are well-known to
preserve their state until the appearance of a suitable condition at their inputs, which
means they can act as event detectors. For example one can use a D flip-flop to detect the
event of switching 'on' of the light, as shown in Figure 4a. The working of such a circuit is
explained in terms of wave forms shown by Figure 4b.
Data Synchronizers
All the outputs of a particular combinational circuit are expected to change their states at
the same instant. However sometimes due to the varying gate delays, the outputs of the
combinational circuit might change their states at different instants of time (green lines in
Figure 5a). This would further cause unexpected behavior resulting in wrong outputs. This
can be avoided by using synchronous D flip-flops at the outputs acting as data
synchronizers (Figure 5b).

In this case, the outputs will be latched by the flip-flops until the clock signal appears.
Thus the outputs can change their states only when the positive edge of the clock triggers
the flip-flops which in turn causes the state-change in all the outputs at that particular
instant of time.

Frequency Divider
Consider a positive edge triggered JK flip-flop whose inputs are tied-together and driven
high, as shown in Figure 6. In this state, the output of JK flip-flop will toggle for each
positive-edge of the clock signal (red lines in the figure). From the waveform it is evident
that if the input clock period is Tin, then the time period of output waveform Tout is twice
of it. Thus one gets fout = fin/2 which implies that input frequency is divided by 2. In other
words, after passing through a single flip-flop, the input frequency will be halved. On the
same grounds one can conclude that after passing through the n flip-flops, the input
frequency will be divided by 2n which results in fout = fin/2n.
 Apart from these applications, a few flip-flops have definite uses like

1. D flip-flop can be used to create delay-lines which are used in digital signal processing
systems. This application arises readily due to the fact that the output at the
synchronous D flip-flop is nothing but the input delayed by one-clock cycle. Thus by
cascading n such flip-flops, output can be delayed by n clock cycles which in turn
produces the required amount of delay.
2. Generally the mechanical switches used to enter the values into the digital system are
prone to bouncing problem where the switch-contacts vibrate while closing/opening the
switch. This leads to the variation in the output voltage causing the logical inputs to
alternate between 0 and 1. This results in unexpected system behavior which can be
avoided by connecting a RS flip-flop between the switch and the digital circuit to act as a
switch debouncer.

Shift Registers
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Registers are the devices used to store the data bits. The bits stored in such registers can
be made to move within the registers and/or in/out of the registers by applying clock
pulses. Such registers are called shift registers. An n-bit shift register can be formed by
cascading n flip-flops where each flip-flop stores a single bit of information (Figure 1). Here
the clear line is used to reset each flip-flop which in turn clears the entire register.

Shift registers can be categorized based on the type of data movement.

 Category 1: Depending on the Direction of Data Shift

 Category 2: Depending on the Mode of Data In or Out
 Category 1: Depending on the Direction of Data Shift

Unidirectional Shift Register

In this type, the data bits within the register can move only in one direction i.e. either
towards left or towards right, accordingly they are called Left-Shift Register or Right-Shift
Register (Figure 2).

Bidirectional or Reversible Shift Register

Bidirectional shift registers (Figure 3) are the shift registers which are capable of shifting
the data in either direction i.e. both towards left (indicated by green arrows) as well as
towards right (indicated by red arrows). This is accomplished by modifying the circuit of
unidirectional shift registers by providing certain additional circuitry including a control
(black color) line which aids in selecting the direction of data-shift.

Category 2: Depending on the Mode of Data In or Out

Serial In Serial Out (SISO) Shift Register

In case of serial in serial out shift registers (Figure 4a), both data loading as well as data
retrieval processes are performed serially, in bit-by-bit fashion. Here for every clock pulse
three functions are performed viz.,

1. One bit of data enters into the register,

2. Data within the register shifts either right or left by one bit,
3. One data bit will come out of the shift register.
However it is to be noted that valid data bit comes out of the n-bit SISO register only after
the application of n clock pulses. Further one requires providing additional n clock pulses in
order to retrieve the entire n-bit input word.

Serial In Parallel Out (SIPO) Shift Register

In serial in parallel out shift registers (Figure 4b), data is loaded into the register bit-by-bit
while it is retrieved in parallel fashion. In this case, at every clock pulse

1. One bit of data enters into the register,

2. Data within the register shifts either right or left by one bit.
Meanwhile the output bits can be read-out in parallel, one bit from each of the individual
register component. Further it is to be noted that valid n-bit data word comes out of the n-
bit SIPO register just after the application of n clock pulses.

Parallel In Serial Out (PISO) Shift Register

In case of parallel in serial out shift registers (Figure 4c), the data loading happens in
parallel fashion while the data retrieval is serial in nature. Here the entire input word
enters into the shift-register at a single clock cycle. From then on, for each clock cycle
1. Data within the register shifts either right or left by one bit
2. One bit exits the register.
This means that the data bits of the input word are obtained at the PISO output bit-by-bit.
This indicates that in order to obtain the entire n-bit input word, one would have to wait
for additional n clock cycles.

Parallel In Parallel Out (PIPO) Shift Register

In parallel in parallel out shift registers (Figure 3d) both data loading as well as data
retrieval processes are parallel in nature. This means that the entire data word can be
entered into the registers at a single clock tick. Similarly this entire data word can be
obtained at the output pins of the individual register components by just providing one
more clock pulse. However it is to be noted that these kinds of shift registers are also
capable of shifting the data bits either towards right or towards left.

Further if the data-out pin of the shift-registers is back connected to the data-in pin, then
the bits of the input word circulate within the registers without being lost. Shift
registers are used when there is a need to accomplish a particular task with reduced
number of control pins. For example in order to control 16 LEDs, one would require 16
individual lines of a micro controller. However due to the limited number of available
general purpose input output (GPIO) pins, this will not be feasible. In such a case, a series
combination of two shift registers would prove to be helpful as it can accomplish the task
with just 4 I/O pins.
Further, shift registers are extensively used to convert serial data stream into parallel form
and vice-versa.

Buffer Register and Controlled Buffer Register

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Buffer registers are a type of registers used to store a binary word. These can be
constructed using a series of flip-flops as each flip-flop can store a single bit. This means
that in order to store an n-bit binary word one should design an array of n flip-flops. Figure
1 shows a 4 bit synchronous buffer register formed by cascading four positive edge
triggered D flip-flops. Here the entire input data word B1B2B3B4 is loaded onto the register
at a single clock tick. This means that at every leading edge of the clock the values of flip-
flop outputs follow their input bits i.e. Q 1 = B1, Q2 = B2, Q3 = B3 and Q4 = B4 as shown by

Figure 2.

Buffer registers offer

no means of control over the inputs which in turn leads to uncontrolled outputs. In order to
overcome this drawback one can resort to controlled buffer registers as shown by Figure 3.
In this design, tri-state switches are used to control the operation of loading and/or

retrieval of the data to/from the buffer register. Here one has to pull the or

control line (blue line) low in order to store the data into the register, while control
line (red line) should be made low to read the data.

Data Transfer in Shift Registers

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Shift registers are the devices which are used to store and/or shift the bits of the input
data word. Here the data bits can be made to enter (or exit) the register in serial/parallel
mode in synchronization with the clock pulse. Moreover the data bits within the shift
register can be made to change their position by moving towards right or left for each
clock pulse.
Consider a 3-bit register formed by connecting three synchronous positive edge
triggered D flip-flops as shown in Figure 1. Here it is seen that the CLR pins of all the flip-
flops are tied-up together and are connected to the clear input. Further the output of FF1
(Q1) is connected as an input to flip-flop 2 (D2 of FF2) and the output of FF2, Q2 is
connected as an input to flip-flop 3 (D3 of FF3). Moreover the data word which is to be
stored is supplied to the register via the input pin of flip-flop 1 (D1 of FF1) while the data is
collected from the output pin of third flip-flop (Q3 of FF3).

Generally the contents of every flip-flop (and hence the entire register) is made zero by
driving their clear pins high before feeding the data. Next the first bit of the input word
(B1of Data in) is made to appear at D1.
This bit will be stored in FF1 and thereby appears at its output Q 1 on the appearance of
first leading edge of the clock. Further at the second clock tick, B1 is stored in FF2 and is
obtained at Q2 while the data at Q1 will the second bit of the input word, B2. Similarly at
the rising edge of the third clock pulse, the third bit of the input data word, B 3 appears at
Q1 while Q 2= B2 and Q2 = B1.
This is called right-shift data transmission as one can note the movement of data from left
to right within the register. The operation of such a register is further emphasized by
Figure 2 in terms of wave forms and by Table I which indicates the movement of data bits
(green arrows), considering the data-in sequence as 100100.
 In the type of shift
register explained above it is seen that the data bit stored in the last flip-flop is lost as and
when the new data bit is stored into the register. This can be avoided by back-connecting
the output pin of FF3 to the D1 pin of FF1. This causes the output bit of the FF3 (Q3) to be
stored into FF1 which results in the circulation of the data bits within the register. However
even in this case the movement of data bits within the intermediate flip-flops remains the
same.
Similar to the right-shift register, there are left-shift registers in which the data moves
from right to left within the register. Further in some cases, the data loading and retrieval
processes of the shift registers are controlled using additional circuitry. Never the less the
basic functionality remains the same. Moreover one has to note that the mode of data
movement explained remains the same irrespective of the size of the shift register.

Serial In Serial Out (SISO) Shift Register

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Serial In Serial Out (SISO) shift registers are a kind of shift registers where both data
loading as well as data retrieval to/from the shift register occurs in serial-mode. Figure 1
shows a n-bit synchronous SISO shift register sensitive to positive edge of the clock
pulse. Here the data word which is to be stored is fed bit-by-bit at the input of the
first flip-flop. Further it is seen that the inputs of all other flip-flops (except the first flip-
flop FF1) are driven by the outputs of the preceding ones say for example, the input of
FF2 is driven by the output of FF1. At last the data stored within the register is obtained at
the output pin of the nth flip-flop in serial-fashion.
Initially all the flip-flops in the register are cleared by applying high on their clear pins.
Next the input data word is fed serially to FF1.
This causes the bit appearing at the D1 pin (B1) to be stored into FF1 as soon as the first
leading edge of the clock appears. Further at the second clock tick, B 1 gets stored into
FF2while a new bit enters into FF1 (B2).
This kind of shift in data bits continues for every rising edge of the clock pulse. This
indicates that for every single clock pulse the data within the register moves towards right
by a single bit. Thus the design shown in Figure 1 is regarded as a right-shift SISO shift
register. Following the data transmission as explained, one can note that the first bit of
an input word appears at the output of nth flip-flop for the nth clock tick. On applying
further clock cycles, one gets the next successive bits of the input data word as the serial
output (Table I). The waveforms pertaining to the same are shown by Figure 2.
Similar to the right-shift SISO shift-register shown, there can exist a left-shift SISO shift-
register also (Figure 3). However the working principle remains the same except the fact
that the data movement will be from right to left.

Serial in Parallel Out (SIPO) Shift Register

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In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register
serially while it is retrieved from it in parallel-fashion. Figure 1 shows an n-bit
synchronous SIPO shift register sensitive to positive edge of the clock pulse. Here the
data word which is to be stored (Data in) is fed serially at the input of the first flip-
flop (D1 of FF1). It is also seen that the inputs of all other flip-flops (except the first flip-
flop FF1) are driven by the outputs of the preceding ones say for example, the input of
FF2 is driven by the output of FF1. In this kind of shift register, the data stored within the
register is obtained as a parallel-output data word (Data out) at the individual output pins
of the flip-flops (Q1 to Qn).

In general, the register contents are cleared by applying high on the clear pins of all the
flip-flops at the initial stage. After this, the first bit, B1 of the input data word is fed at the
D1 pin of FF1.
This bit (B1) will enter into FF1, get stored and thereby appears at its output Q 1 on the
appearance of first leading edge of the clock. Further at the second clock tick, the bit
B1right-shifts and gets stored into FF2 while appearing at its output pin Q2 while a new bit,
B2enters into FF1. Similarly at each clock tick the data within the register moves towards
right by a single bit while a new bit of the input word enters into the register. Meanwhile
one can extract the bits stored within the register in parallel-fashion at the individual flip-
flop outputs.
Analyzing on the same grounds, one can note that the n-bit input data word is obtained as
an n-bit output data word from the shift register at the rising edge of the n th clock pulse.
This working of the shift-register can be summarized as in Table I and the corresponding
wave forms are given by Figure 2.
In the right-shift SIPO shift-register, data bits shift from left to right for each clock tick.
However if the data bits are made to shift from right to left in the same design, one gets a
left-shift SIPO shift-register as shown by Figure 3. Nevertheless the basic working principle
remains the same except the fact that now Bn down to B1 is stored in Qn down to Q1 i.e.
Q1= B1, Q2 = B2 … Qn = Bn at the nth clock tick.