CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 1
HIGH-LEVEL SYNTHESIS
High-level synthesis: the automatic addition of
structural information to a design described by
an algorithm.
BEHAVIORAL D. STRUCTURAL D.
Systems
Algorithms Processors
Register transfers ALUs, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer Transistors
functions
Transistor layout
Cell layout
Module layout
Floor plans
Physical partitions
PHYSICAL D.
High-level synthesis visualized on Gajskis Y-
chart
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 2
HARDWARE MODELS
FOR HIGH-LEVEL
SYNTHESIS
All HLS systems need to restrict the target hard-
ware. The search space is too large, otherwise.
All synthesis systems have their own peculiari-
ties; but most systems generate synchronous
hardware and build it with the following parts:
* functional units: they can perform one or
more computations, e.g. addition, multiplica-
tion, comparison, ALU.
i1 i2
o f (i 1, i 2)
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 3
HARDWARE MODELS
(Continued)
* registers: they store inputs, intermediate re-
sults and outputs; sometimes several regis-
ters are taken together to form a register file.
* multiplexers: from several inputs, one is
passed to the output.
i0 i1 i2 i3
c1
c0
o + i k , k + 2c 1 ) c 0
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 4
HARDWARE MODELS
(Continued)
* busses: a connection shared between several
hardware elements, such that only one ele-
ment can write data at a specific time.
* three-state (tri-state) drivers control the ex-
clusive writing on the bus.
i
enable
o
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HIGH-LEVEL SYNTHESIS Page 5
HARDWARE MODELS
(Continued)
Parameters defining the hardware model for the
synthesis problem:
* clocking strategy: e.g. one- or two-phase
clocks.
* interconnect: e.g. allowing or disallowing
buses.
* clocking of functional units: allowing or dis-
allowing of:
+ multicycle operations;
+ chaninig;
+ pipelined units.
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HIGH-LEVEL SYNTHESIS Page 6
HARDWARE CONCEPTS:
DATA PATH + CONTROL
Hardware is normally partitioned into two parts:
* the data path: a network of functional units,
registers, multiplexers and buses. The actual
computation takes place in the data path.
* control: the part of the hardware that takes
care of having the data present at the right
place at a specific time, of presenting the right
instructions to a programmable unit, etc.
Often high-level synthesis concentrates on data-
path synthesis. The control part is then realized
as a finite state machine or in microcode.
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 7
INPUT FORMAT
The algorithm, that is the input for a high-level
synthesis system, is often provided in textual
form either:
* in a conventional programming language,
such as Pascal, or
* in a hardware description language, which is
more suitable to express the parallelism pres-
ent in hardware.
The description has to be parsed and trans-
formed into an internal representation; here
conventional compiler techniques can be used.
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 8
INTERNAL
REPRESENTATION
Most systems use some form of a data-flow
graph. A DFG may or may not contain informa-
tion on control flow.
A data-flow graph is built from:
* vertices (nodes): representing computation,
and
* edges: representing precedence relations.
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 9
DATA FLOW
x := a * b; y := c + d;
z := x + y;
a b c d
x y
z
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HIGH-LEVEL SYNTHESIS Page 10
TOKEN FLOW IN A DFG
* A node in a DFG fires when tokens are pres-
ent at its inputs.
* The input tokens are consumed and an output
token is produced.
a b c d a b c d
x y x y
z z
a b c d a b c d
x y x y
z z
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HIGH-LEVEL SYNTHESIS Page 11
CONDITIONAL DATA
FLOW
By means of two special nodes:
* selector
T F
selector
* distributor
distributor
T F
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HIGH-LEVEL SYNTHESIS Page 12
EXPLICIT ITERATIVE
DATA FLOW
Selector and distributor nodes can be used to de-
scribe iteration.
a b
T sel. F
T distr. F
while a > b
a do
a := a b;
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HIGH-LEVEL SYNTHESIS Page 13
Loops require careful placement of initial tokens
on edges.
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HIGH-LEVEL SYNTHESIS Page 14
IMPLICIT ITERATIVE
DATA FLOW
* Iteration implied by stream of input tokens
arriving at regular points in time.
* Initial tokens act as buffers.
a b a b a b
a[0] a[1] b[1] a[1]
a[0]
c[1]
c c c
* Delay elements instead of initial tokens.
a b
T0
c
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HIGH-LEVEL SYNTHESIS Page 15
ITERATIVE DFG
EXAMPLE
+
c8 o1
m1 d1 m2
T0
c2 c4 c6 c7
+ +
m3 d2 m4
T0
i1 c1 c3 c5
+
A second-order filter section.
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HIGH-LEVEL SYNTHESIS Page 16
HIGH-LEVEL
TRANSFORMATIONS
Restructuring data and control flow graphs prior
to the actual mapping onto hardware.
Examples:
* Replacing division by 2 by shift.
* Loop unrolling.
* Replacing chain of adders by a tree.
x1 x2 x3 x4 x5 x6 x7 x8
y
+ + + + + + + +
x1 x2 x3 x4 x5 x6 x7 x8
+ + + +
+ +
+
y
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HIGH-LEVEL SYNTHESIS Page 17
TERMINOLOGY
Subtasks in high-level synthesis:
* Scheduling: determine for each operation the
time at which it should be performed such
that no precedence constraint is violated.
For an edge (v i, v j): t j w t i ) i
* Allocation: specify the hardware resources
that will be necessary.
* Assignment: provide a mapping from each
operation to a specific functional unit and
from each variable to a register.
Remarks:
* The subproblems are strongly interrelated;
they are, however, often solved separately.
* Scheduling (except for a few versions) is NP-
complete heuristics have to be used.
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 18
EXAMPLE
The second-order filter section made acyclic:
+
c8 o1
o 2(d 1)
m1 m2
c2 c4
i 2(d 1)
c6 c7
+ +
m3 o 3(d 2) m4
i1 c1 c3 i 3(d 2) c5
+
The schedule and operation assignment with an
allocation of one adder and one multiplier:
c3 c4 c5 c6
+ c1 c2 c7 c8
0 5 10
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HIGH-LEVEL SYNTHESIS Page 19
EXAMPLE (Continued)
The resulting data path after register assign-
ment:
d1
i1 r1 r2 r3 r4
ROM d2
o1
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HIGH-LEVEL SYNTHESIS Page 20
OPTIMIZATION CRITERIA
Not surprisingly, the objective function to be op-
timized is similar to the one for the design of
VLSI circuits in general. It is a combination of:
* speed: how long does it take to perform the
intended computation,
* area: the addition of the areas of all function-
al units and registers, sometimes taking the
area of interconnection into account.
Often optimization is constrained:
* Optimize area when the minimum speed is
given time-constrained synthesis.
* Optimize speed when maximum area is given
area-constrained synthesis.
* Optimize speed when a maximum for each
resource type is given resource-con-
strained synthesis.
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HIGH-LEVEL SYNTHESIS Page 21
SCHEDULING METHODS
* As soon as possible (ASAP):
+ an operation can be scheduled when all its
predecessors have been scheduled.
+ very simple, as data-flow graph need only
to be traversed from inputs(s) to output(s).
* As late as possible (ALAP):
+ similar to ASAP, but scheduling is now
performed from output(s) to input(s).
* List scheduling:
+ similar to ASAP; however, now an extra
criterion is used for choosing between all
operations that have all their predecessors
scheduled.
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HIGH-LEVEL SYNTHESIS Page 22
SCHEDULING METHODS
(Continued)
* Critical-path list scheduling:
+ sorting criterion is the length of the longest
path from operation to output.
+ gives good results in practice!
* Freedom-based scheduling:
+ compute both ASAP and ALAP schedules
(longest-path computations from inputs to
operation and from operation to outputs).
+ the difference in scheduling position gives
the freedom or mobility of an operation
(operations in the critical path have mobil-
ity zero).
+ take advantage of mobility to find a good
position within scheduling range.
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HIGH-LEVEL SYNTHESIS Page 23
FORCE-DIRECTED
SCHEDULING
* extension of freedom-based methods.
* computes so-called distribution graph to
model the global effects on hardware re-
sources.
a1 +
a1
a2 + a2
+ a3 a3
^
* a partial schedule t, is a schedule where some
transfers have a fixed time positions and oth-
ers have a scheduling range.
* the resource utilization for resource r of a
^
partial schedule t at time t is given by the dis-
^ ^
tribution function q r(t, t).
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 24
FORCE-DIRECTED
SCHEDULING (Ctd.)
* When fixing an operations time, one makes
^
a transition from partial schedule t to partial
^
schedule s.
^ ^
* For every operation a force F r(t, s), is com-
puted for every possible position within an
operations range.
* Basic force function:
^ ^
F r(t, s) + ^ ^ ^ ^ ^ ^
q r(t, t)(q r(s, t) * q r(t, t))
trange(op)
* The lowest force determines which operation
is scheduled and at which position.
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HIGH-LEVEL SYNTHESIS Page 25
THE ASSIGNMENT
PROBLEM
Subtasks in assignment:
* operation-to-FU assignment
* value grouping
* value-to-register assignment
* transfer-to-wire assignment
* wire to FU-port assignment
In general: task-to-agent assignment
Assumption: assignment follows scheduling.
* Then the claim of a task on an agent is an
interval minimum resource utilization can
be found by left-edge algorithm.
* In case of iterative algorithm, interval graph
becomes circular-arc graph optimization
is NP-complete.
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HIGH-LEVEL SYNTHESIS Page 26
ASSIGNMENT BY CLIQUE
PARTITIONING
* Tasks are compatible when they can be
executed on the same agent simultaneously
compatiblity graph.
* A clique is a maximal complete subgraph.
* Clique partitioning divides the vertices of a
graph into complete subgraphs.
v1
v1
v4 v5 v4 C 3 v5
v0 v0
C1 C4
v2 v7 C0 v7
v2
v3 v6 v3 v6
C2
(a) (b)
A graph and its cliques
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HIGH-LEVEL SYNTHESIS Page 27
TSENG AND SIEWOREKS
CLIQUE-PARTITIONING
ALGORITHM
k:= 0;
k k k
Gc (Vc ; Ec ) := Gc (Vc ; Ec );
while Eck 6= ; do
begin
\ nd vi; vj with largest set of common neighbors";
N := \set of common neighbors of vi and vj ";
s := i [ j ;
Vc
k+1 := V k [ fvsg n fvi ; vj g;
c
Ec
k +1 := ;;
for each (vm ; vn ) 2 Eck do
if vm 6= vi ^ vm 6= vj ^ vn 6= vi ^ vn 6= vj
then Eck+1 := Eck+1 [ f(vm ; vn )g;
for each vn 2 N do
Ec
k+1 := E k+1 [ f(vn ; vs)g;
c
k := k + 1
end
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 28
CLIQUE-PARTITIONING
EXAMPLE
v1 v0,1
v4 v5 v5
v0 v4
v2 v2
v7 v7
v3 v6 v3 v6
(a) (b)
v0,1,2
v0,1,2
v4 v5,6
v4 v5
v7
v7
v3
v3 v6
(c) (d)
v0,1,2,3 v0,1,2,3
v4 v5,6 v4 v5,6,7
v7
(e) (f)
CAD TOOLS FOR VLSI
HIGH-LEVEL SYNTHESIS Page 29
HIGH-LEVEL
TRANSFORMATIONS
Restructuring data and control flow graphs prior
to the actual mapping onto hardware.
Examples:
* Replacing division by 2 by shift.
* Loop unrolling.
* Replacing chain of adders by a tree.
x1 x2 x3 x4 x5 x6 x7 x8
y
+ + + + + + + +
x1 x2 x3 x4 x5 x6 x7 x8
+ + + +
+ +
+
y
