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3.1 ESIOT- Interfaces

The document discusses the interfacing of embedded systems and IoT, focusing on input/output (I/O) devices, communication links, and various I/O interfaces. It explains the roles of CPU and peripheral devices, data conversion, synchronization, and device selection, along with different types of I/O commands and access methods. Additionally, it covers serial communication protocols, particularly UART and I2C, detailing their functionalities, advantages, and operational principles.
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0% found this document useful (0 votes)
7 views71 pages

3.1 ESIOT- Interfaces

The document discusses the interfacing of embedded systems and IoT, focusing on input/output (I/O) devices, communication links, and various I/O interfaces. It explains the roles of CPU and peripheral devices, data conversion, synchronization, and device selection, along with different types of I/O commands and access methods. Additionally, it covers serial communication protocols, particularly UART and I2C, detailing their functionalities, advantages, and operational principles.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Interfacing

Embedded Systems and IoT


Embedding A Computer: I/O devices
I/O Devices
• Digital interface to I/O devices
• Some devices have non-digital components,
• e.g., electronics for rotating disk and analog read/write in hard drive
• Devices usually use registers to talk to CPU
• Status: info, e.g. if the data is ready to read, 1: ready, 0: finished
• Data: holds data outputted to or inputted from the device
Interface
• Interface is a shared boundary between two separate components of
the computer system which can be used to attach two or more
components to the system for communication purposes.
• There are two types of interface:
• CPU interface
• I/O interface
Input-Output Interface
• Peripherals connected to a computer need special communication links for
interfacing with CPU to control or manage the input output transfers.
Why?
• The purpose of the communication link is to resolve the differences
that exist between the CPU and each peripheral device.

CPU Peripheral devices


Electronic device Electromechanical and Conversion of signal values
electromagnetic devices

Data transfer rate - Fast Data transfer rate - Slower Synchronization mechanism
Word Data codes and formats Conversion
Main function of input-output interface
• Data conversion:
• Data conversion refers to conversion between digital and analog signals and
conversion between serial and parallel data formats.
• Synchronization:
• Synchronization refers to matching of operating speed of CPU and other
peripherals.
• Device selection:
• Device selection refers to the selection of I/O device by CPU in a queue
manner.
I/O bus
• Consists of data lines, address lines and control lines
• To communicate with a peripheral device
• Processor places a device address on address lines
• Each Interface decodes (for peripheral) the address and control received,
• Provides signals for the peripheral controller
• Initiate data transfer
• also synchronizes the data flow and supervises the data transfer
I/O command
• Control lines transfers I/O command
• Control command-
• To activate the peripheral and to inform it what to do.
• Status command- used
• To test various status conditions in the interface and the peripheral.
• Data Output command
• The interface to respond by transferring data from the bus into one of its registers.
• Data Input command
• The interface receives the data from the peripheral and places it in its buffer register.
Accessing I/O Ports
• How to access an I/O port from software?
• Special instructions
• Special registers
• Special memory locations
Option 1: I/O Instructions
• Special instruction in the ISA for input/output
• Example: Z80 ISA
• out (243), A
• Output value stored in register A to port 243
• in A,254
• Read the value in port 254 and store it in register A
• Ports are special operands
Option 2: Special Registers
• Special register in the ISA for input/output
• Example: SNAP ISA
• add $15,$1,$2
• Register 15 is mapped for output operations
• add $1,$15,$2
• Register 15 is also mapped for input operations
• I/O operation determined by writing specific values to
$15.
Memory Mapped I/O
• Memory mapped I/O: Reads
and writes to specific memory
locations correspond to I/O
operations
Privilege Levels
• Which software should manages the IO?
• Processors often support multiple privilege levels
• Supervisor / “Privileged” in Cortex-M4
• Access to all resources
• User / “Unprivileged” in Cortex-M4
• Limited access to certain instructions and memory/peripheral
• Which mode should a processor starts running in?
Handling Outputs
• On-chip registers connected to I/O pins
• Implementing output instructions:
• Write register for output values
• Change in state appears on the pins
• . . . after a small delay
Handling Input
• Need communication disciplines
• How does software know if the value is valid?
• Use a valid bit
• 9-bit input, with 8-bits of data
• Toggle 9th bit to indicate new data
• Use encoded data
• One-hot encoding
• 01 = false, 10 = true, 00 = no data
• How does software know when a new input is ready?
Handling Input
• Option 1: Polling
• Use software to check
• Keep reading the value in a loop

• Option 2: Interrupts
• A peripheral device notifies a processor that there is a new input
• Run Interrupt Service Routine (ISR)
• Return to the original (interrupted) program
Multiple IO Devices
• Which device raised an interrupt?
• Which interrupt service routine to run?
• Common approaches
• Polling
• Interrupt Vector Table (IVT) + Multiple IRQ signals
• Interrupt + Polling
• Daisy chain
Prioritization (ARM)
• Exceptions are prioritized to order the response simultaneous
requests (smaller number = higher priority)
• Priorities of some exceptions are fixed
• Reset: -3, highest priority
• Non-maskable interrupts (NMI): -2
• Hard Fault: -1

• Priorities of other (peripheral) exceptions are adjustable


• Value is stored in the interrupt priority register (IPR0-7)
Pin vs Port vs Interface
• A pin is one wire on the microcontroller used for input or output.
• A port is a collection of pins.
• An interface is defined as the collection of the I/O port, external
electronics, physical devices, and the driver, which combine to allow
the computer to communicate with the external world.
• I/O interface categories
• Parallel - binary data are available simultaneously on a group of lines
• Serial - binary data are available one bit at a time on a single line
• Analog - data are encoded as an electrical voltage, current, or power
• Time - data are encoded as a period, frequency, pulse width, or phase shift
General Purpose Input Output (GPIO)
• Collection of pins, and
allows the driver to read
data from input pins and
write data to output pins
• Can use this to interface
with external devices
• Example
• Input: switch
• Output: LEDs
I/O Interfaces
• Parallel I/O and Serial I/O
• Parallel I/O: multiple input/output simultaneously
• Data Bus, Address Bus, Intel 8255, printer
• Serial I/O: transferring data between CPU and peripherals
one bit at a time, sequentially
• Ethernet, USB, Inter-integrated Circuit, Serial Peripheral Interface
I/O Interfaces Parallel

• Parallel v.s. Serial


• Parallel
• Wider bandwidth
• More wires indicate more overhead
• Simple I/O operation
• Serial
• 1-bit transfer per time unit
• Less wires indicate less overhead
Serial
• Complex I/O protocol
I/O Interfaces
• Serial over Parallel
• Parallel interfaces have less reliability
• Interference and noise corrupt data
• Capacitance and mutual inductance affects bandwidth
• Serial
• Less mutual interference between wires
• Higher clock frequency increases transmission rate
Serial Communications
• Synchronous Serial Interface: all bytes in a frame transmit with equal
time interval spacing or phase difference
• SCI
• I2C
• CAN
• USB
• Asynchronous Serial Interface: all bytes in a data frame may transmit
with variable time-interval spacing or phase difference
• UART
Serial Interfaces Protocol
• “Simple” Serial Interfaces
• RS-232C (UART)
• Provides for point–to–point communications, primarily
• Among the simplest serial communication methods
• Generally no address decoding, .... though “multi-drop” systems exist
• Max speed ~ 1 M bits per sec
• I2C (Inter–Integrated Circuit) Bus
• Serial, 2-wire (plus ground) bus
• Note that it is a true bus (as opposed to point–to–point communications)
• Popular in embedded systems
• SPI (Serial Peripheral Interface ) Bus
• Also referred to as SSI (Synchronous Serial Interface)
• Serial, 4-wire bus
• Operates in full duplex mode
Serial Interfaces Protocol
• “Complex” Serial Interfaces
• USB
• Universal Serial Bus
• PC to peripheral connection
• Complex protocols (hardware and software)
• Ethernet
• Local Area Networking
• computer-to-computer linkage
• Developed by Xerox PARC, IEEE 802.3
• Relies on protocols to implement sharing of the medium
• original versions were bus-like, now most common is point-to-point
Serial Interfaces Protocol
• Wireless Serial Interfaces
• Bluetooth
• Wireless (radio) communication between electronic devices
• Protocols are based on ethernet-like model
• RF portion quite complex
• WiFi (IEEE 802.11)
• Wireless LAN
• Computer-to-computer connections
• Same protocols as ethernet, plus more
• RF portion (as in the case of Bluetooth) quite complex
Serial Communication
• The basic premise of serial communications is that one or two wires
are used to transmit digital data. – Of course, ground reference is also
needed (extra wire)
• Can be one way or two way, usually two way, hence two
communications wires.
• Often other wires are used for other aspects of the communications
(ground, “clear-to-send”, “data terminal ready”, etc).
Serial Communication Basics
• Send one bit of the message at a
time
• Message fields
• Start bit (one bit)
• Data (LSB first or MSB, and size – 7,
8, 9 bits)
• Optional parity bit
• All devices on network or link must
use same communications
parameters
• The speed of communication must
be the same as well (300, 600, 1200,
2400, 9600, 14400, 19200, etc.)
UART (Universal Asynchronous Receiver/
Transmitter)
• Universal – configurable to fit protocol requirements
• Asynchronous – no clock line needed to de-serialize bits
• Receiver/Transmitter
UART
UART Functions
• Outbound data
• Convert from parallel to serial
• Add start and stop delineators (bits)
• Add parity bit
• Inbound data
• Convert from serial to parallel
• Remove start and stop delineators (bits)
• Check and remove parity bit
System Diagram
UART Character Transmission
• Uses a single wire for transmission
• Each block represents a bit that can be a mark (logic ‘1’, high) or space
(logic ‘0’, low)
• Each bit has a fixed time duration determined by the transmission
rate. E.g. a 1200 bps (bits per second) UART will have a 1/1200 s or
about 833.3 microsec bit width
UART Character Transmission
• The start bit marks the beginning of a new word
• When detected, the receiver synchronizes with the new data stream
• Next follows the data bits (7 or 8)
• The least significant bit is sent first
• The stop bit marks the end of transmission
• Receiver checks to make sure it is ‘1’
• Separates one word from the start bit of the next word
• In the configuration shown, it takes 10 bits to send 7 bits of data
UART Transmission Example
• Send the ASCII letter ‘W’ (1010111)
UART Options
• UARTs usually have programmable options:
• Data: 7 or 8 bits
• Parity: even, odd, none, mark, space
• Stop bits: 1, 1.5, 2
• Baud rate: 300, 1200, 2400, 4800, 9600, 19.2K, 38.4k, 57.6k, 115.2k…
UART Throughput
• Data Throughput Example
• Assume 19200 baud, 8 data bits, no parity, 1 stop bit
• 19200 baud = 19.2 kbps
• 1 start bit + 8 data bits + 1 stop bit = 10 bits
• It takes 10 bits to send 8 bits (1 byte) of data
• 19.2 kbps • 8/10 = 15.36 kbps
• How many KB (kilobytes) per second is this?
• 1 byte = 8 bits
• 1 KB = 1,024 bytes
• So, 1 KB = 1,024 bytes • 8 bits/byte = 8,192 bits
• Finally, 15,360 bps • 1 KB / 8,192 bits = 1.875 KB/s
Serial Communication to/from PC
• Serial communication
• The Arduino IDE has a feature, called “Serial Monitor”, which is a separate
pop-up window that acts as a terminal to communicate with the Arduino
UNO by receiving and sending serial data
• Arduino’s serial library supports serial communication
• [Link]() - start serial port and set baud rate
• [Link]() - transmit the data to PC
• [Link]() - receive the data from PC
The I2C Bus
• I2C (Inter Integrated Circuit) Bus
• Serial, 2-wire bus
• Different than point–to–point communications
• Developed by Philips (now NXP) Semiconductor in early1980’s
• Intel SMBus (System Management Bus) is a subset of I2C
• Software controlled addressing
• No address decoding hardware
• Available as a built-in peripheral on many μControllers and μProcessors
The I2C Bus
• 2 Wire, Serial Bus
• SDA – Serial Data
• SCL – Serial Clock
• Many masters, many slaves possible
• always at least one master (μcontroller or DSP)
• Each device has a unique 7-bit I2C address
• 4 most significant bits are typically fixed and assigned to specific categories of
devices
• e.g. 4’b1010 is assigned to serial EEPROMs
• 3 less significant bits are programmable, often through hardware address pins
• Bit 8 of address signals read or write.
I2C Bus Terminology
• Master
• The component that initiates a transfer (Start command), generates the clock signal
(SCL), and terminates the transfer (Stop command)
• Slave
• The device addressed by the master
• A slave can be either receiver or transmitter
• Transmitter
• Device that sends data to the bus
• can be master-transmitter or slave-transmitter
• Receiver
• Device that receives data from the bus
• can be master-receiver or slave-receiver
I2C Bus Terminology
• Master always drives the clock line which sets the timing for all
transactions
• Master can be either transmitter or receiver, depending on data
direction
I2C Bus Terminology
• Multi-master
• The ability for more than one master to co-exist on the bus at the same time
without collision or data loss.
• Obviously, though multiple masters may be present, only one can be master
in any one transaction
• Arbitration
• Fixed-priority
• The prearranged procedure that authorizes only one master at a time to take
control of the bus
• Synchronization
• The prearranged procedure that synchronizes the clock signals provided by
two or more masters.
Multi-master

master 1 master 2
data line
SDL

clock line
SCL

slave 1 slave 2
Multi-master

master 1
data line
SDL

clock line
SCL

slave 1 slave 1
The I2C Bus
• I2C Bus Transfer Conditions and States
• F (FREE) - Idle
• The bus is free or idle; the data line SDA and the SCL clock are both in the high state
• S (START) or R (RESTART)
• Data transfer begins with a Start condition. The level of the SDA data line changes from
high to low, while the SCL clock line remains high. When this occurs, the bus becomes
'busy‘
• C (CHANGE)
• While the SCL clock line is low, the data bit to be transferred can be applied to the SDA
data line by a transmitter. During this time, SDA may change its state, as long as the SCL
line remains low.
The I2C Bus
• I2C Bus Transfer Conditions and States
• D (DATA)
• A high or low bit of information on the SDA data line is valid during the high level of the
SCL clock line
• This level must be kept stable during the entire time that the clock remains high to avoid
misinterpretation as a Start or Stop condition
• P (STOP)
• Data transfer is terminated by a Stop condition
• This occurs when the level on the SDA data line passes from the low state to the high
state, while the SCL clock line remains high
• When the data transfer has been terminated, the bus is free once again
I2C Bus Transactions
• I2C address of the targeted device is sent in the first byte after Start
condition
• LSB of initial byte indicates direction of transfer (R/W)
• Each transmission sequence begins with Start condition and ends
with Stop or Restart condition
• After every 8 data bits in one direction, an "acknowledge“ bit is
transmitted in the other direction
• The transmitter and receiver switch roles for one bit and the erstwhile
receiver transmits a single 0 bit (ACK) back
I2C Bus Transactions
• If the transmitter sees a 1 bit (NACK) instead, it learns that:
• (If master transmitting to slave) The slave is unable to accept the data. No
such slave, command not understood, or unable to accept any more data
• (If slave transmitting to master) The master wishes the transfer to stop after
this data byte
I2C Bus Transactions
• Data transfer is initiated with the START bit (S) when SDA is pulled low
while SCL stays high
• Then, SDA sets the transferred bit while SCL is low (blue) and the data
is sampled (received) when SCL rises (green)
• When the transfer is complete, a STOP bit (P) is sent by releasing the
data line to allow it to be pulled up while SCL is constantly high
• In order to avoid false marker detection, the level on SDA is changed
on the falling edge and is captured on the rising edge of SCL
I2C Bus Transactions
The I2C bus: State diagram
The I2C Bus
I2C interface in microcontroller
Communication analysis
• First, understand delay for single message.
• Delay for multiple messages depends on:
• network protocol;
• devices on network.
Message delay
• Assume:
• single message;
• no contention.
• Delay:
• tm = tx + tn + tr
• = transmitter overhead + network transmission time + receiver overhead
Example: 2
IC message delay
• Network transmission time dominates.
• Assume 100 kbits/sec, one 8-bit byte.
• Number of bits in packet:
• npacket = start + address + data + stop
• = 1 + 8 + 8 + 1 = 18 bits
• Time required to transmit: 1.8 x 10-4 sec.
SPI – Serial Peripheral Interface
• Developed by Motorola
• Also known as Serial Synchronous Interface (SSI)
• 3- or 4-wire serial interface
• Optional 4-wire (SS=slave select) is not bussed
• Single master with multiple slave devices
• Daisy-chain
• Full-duplex data transfer
• No arbitration
SPI – Serial Peripheral Interface
• Used to communicate across small distances
• Transfers data in 4 to 16 bit characters
• Higher throughput than I2C and can do “stream transfers”
• But
• Has no hardware flow control
• No slave acknowledgment (master could be talking to thin air and not even
know it)
Devices with SPI Interface

BME 688 Environmental Precision Thermocouple Amplifier


sensor
RFID Reader Writer Module
Devices with SPI Interface
SPI
SPI Protocol
• Wires:
• Master Out Slave In (MOSI)
• To Carries data out of Master to Slave
• Master In Slave Out (MISO)
• To Carries data from Slave to Master
• System Clock (SCLK)
• Master produced clock to synchronize data transfer
• SS_BAR
• Unique line to select a slave
SPI Protocol
• Two possibilities for connecting multiple slaves
Star (slaves in parallel) Slaves in Series
SPI: Shift register model
• Shift registers shift in and out data
• Master shifts out data to Slave, and shifts in data from Slave
SPI Communication
SPI clocking: there is no “standard way”
• Four programmable clocking “modes”
• Two phases
• Two polarities
• Master and selected slave must be in the same mode
• During transfers with slaves A and B, Master must
• Configure clock to Slave A’s clock mode
• Select Slave A
• Do transfer
• Deselect Slave A
• Configure clock to Slave B’s clock mode
• Select Slave B
• Do transfer
• Deselect Slave B
• Master reconfigures clock mode on-the-fly!
SPI Pros and Cons
• Pros:
• Fast and easy
• Fast for point-to-point connections
• Easily allows streaming/Constant data inflow
• No addressing/Simple to implement
• Everyone supports it

• Cons:
• SS makes multiple slaves very complicated
• No acknowledgement ability
• No inherent arbitration
• No flow control

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