Datasheet

RA6M5 Group R01DS0366EJ0140

Rev.1.40
Renesas Microcontrollers Mar 14, 2025
High-performance 200 MHz Arm Cortex-M33 core, up to 2 MB code flash memory with Dual-bank, background and SWAP
operation, 8 KB Data flash memory, and 512 KB SRAM with Parity/ECC. High-integration with Ethernet MAC controller,
USB 2.0 High-Speed, CAN FD, SDHI, Quad and Octa SPI, and advanced analog. Integrated Secure Crypto Engine with
cryptography accelerators, key management support, tamper detection and power analysis resistance in concert with Arm
TrustZone for integrated secure element functionality.

Features
■ Arm® Cortex®-M33 Core ● Realtime Clock (RTC) with calendar and VBATT support
● Event Link Controller (ELC)
● Armv8-M architecture with the main extension ● Data Transfer Controller (DTC)
● Maximum operating frequency: 200 MHz ● DMA Controller (DMAC) × 8
● Arm Memory Protection Unit (Arm MPU) ● Power-on reset
– Protected Memory System Architecture (PMSAv8) ● Low Voltage Detection (LVD) with voltage settings
– Secure MPU (MPU_S): 8 regions ● Watchdog Timer (WDT)
– Non-secure MPU (MPU_NS): 8 regions ● Independent Watchdog Timer (IWDT)
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance ■ Human Machine Interface (HMI)
– Driven by LOCO or system clock
● Capacitive Touch Sensing Unit (CTSU)
● CoreSight™ ETM-M33
■ Multiple Clock Sources
■ Memory
● Main clock oscillator (MOSC) (8 to 24 MHz)
● Up to 2-MB code flash memory ● Sub-clock oscillator (SOSC) (32.768 kHz)
● 8-KB data flash memory (100,000 program/erase (P/E) cycles) ● High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
● 512-KB SRAM ● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
■ Connectivity ● IWDT-dedicated on-chip oscillator (15 kHz)
● Serial Communications Interface (SCI) × 10 ● Clock trim function for HOCO/MOCO/LOCO
– Asynchronous interfaces ● PLL/PLL2
– 8-bit clock synchronous interface ● Clock out support
– Smart card interface
– Simple IIC ■ General-Purpose I/O Ports
– Simple SPI ● 5-V tolerance, open drain, input pull-up, switchable driving ability
– Manchester coding (SCI3, SCI4)
● I2C bus interface (IIC) × 3 ■ Operating Voltage
● Serial Peripheral Interface (SPI) × 2
● Quad Serial Peripheral Interface (QSPI) ● VCC: 2.7 to 3.6 V
● Octa Serial Peripheral Interface (OSPI)
● USB 2.0 Full-Speed Module (USBFS) ■ Operating Temperature and Packages
● USB 2.0 High-Speed Module (USBHS) ● Ta = -40℃ to +105℃
● CAN with Flexible Data-rate (CANFD) × 2 – 176-pin LQFP (24 mm × 24 mm, 0.5 mm pitch)
● Ethernet MAC/DMA Controller (ETHERC/EDMAC) – 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
● SD/MMC Host Interface (SDHI) – 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
● Serial Sound Interface Enhanced (SSIE) – 144-pin BGA (7 mm × 7 mm, 0.5 mm pitch)
● Consumer Electronics Control (CEC) – 100-pin BGA (7 mm × 7 mm, 0.5 mm pitch)
● Ta = -40℃ to +85℃
■ Analog – 176-pin BGA (13 mm × 13 mm, 0.8 mm pitch)
● 12-bit A/D Converter (ADC12) × 2
– 5 Msps at interleaving
● 12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)

■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 6
● Low Power Asynchronous General Purpose Timer (AGT) × 6

■ Security and Encryption

● Secure Crypto Engine 9
– Symmetric algorithms: AES
– Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
● Arm® TrustZone®
– Up to three or six regions for the code flash, depending on the
bank mode
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecycle management
● Pin function
– Up to three tamper pins
– Secure pin multiplexing

■ System and Power Management

● Low power modes
● Battery backup function (VBATT)

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1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 200 MHz with the following
features:
● Up to 2 MB code flash memory
● 512 KB SRAM
● Quad Serial Peripheral Interface (QSPI), Octa Serial Peripheral Interface (OSPI)
● Ethernet MAC Controller (ETHERC), USBFS, USBHS, SD/MMC Host Interface
● Capacitive Touch Sensing Unit (CTSU)
● Analog peripherals
● Security and safety features

1.1 Function Outline

Table 1.1 Arm core
Feature Functional description

Arm Cortex-M33 core ● Maximum operating frequency: up to 200 MHz

● Arm Cortex-M33 core:
– Armv8-M architecture with security extension
– Revision: r0p4-00rel0
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
● CoreSight™ ETM-M33

Table 1.2 Memory

Feature Functional description

Code flash memory Maximum 2 MB of code flash memory.

Data flash memory 8 KB of data flash memory.
Option-setting memory The option-setting memory determines the state of the MCU after a reset.
SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).

Table 1.3 System (1 of 2)

Feature Functional description

Operating modes Two operating modes:

● Single-chip mode
● SCI/USB boot mode
Resets The MCU provides 14 resets.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.

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Table 1.3 System (2 of 2)

Feature Functional description

Clocks ● Main clock oscillator (MOSC)

● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator
● PLL/PLL2
● Clock out support
Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to
Measurement Circuit (CAC) be measured (measurement target clock) within the time generated by the clock selected
as the measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range. When measurement
is complete or the number of pulses within the time generated by the measurement reference
clock is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)
modules. The ICU also controls non-maskable interrupts.
Low power modes Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered area
includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.
Register write protection The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
Memory Protection Unit (MPU) The MCU has one Memory Protection Unit (MPU).

Table 1.4 Event link

Feature Functional description

Event Link Controller (ELC) The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between
the modules without CPU intervention.

Table 1.5 Direct memory access

Feature Functional description

Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
DMA Controller (DMAC) The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer
data without intervention from the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.

Table 1.6 External bus interface

Feature Functional description

External bus ● CS area (ECBIU): Connected to the external devices (external memory interface)
● QSPI area (EQBIU): Connected to the QSPI (external device interface)
● OSPI area (EOBIU): Connected to the OSPI (external device interface)

Table 1.7 Timers (1 of 2)

Feature Functional description

General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer
with GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter,
down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG) The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state

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Table 1.7 Timers (2 of 2)

Feature Functional description

Low Power Asynchronous General The Low Power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
Purpose Timer (AGT) for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
Realtime Clock (RTC) The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode,
that are used by switching register settings. For calendar count mode, the RTC has a 100-year
calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count
mode, the RTC counts seconds and retains the information as a serial value. Binary count mode
can be used for calendars other than the Gregorian (Western) calendar.
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.

Table 1.8 Communication interfaces (1 of 2)

Feature Functional description

Serial Communications Interface (SCI) The Serial Communications Interface (SCI) × 10 channels have asynchronous and synchronous
serial interfaces:
● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
● 8-bit clock synchronous interface
● Simple IIC (master-only)
● Simple SPI
● Smart card interface
● Manchester interface
● Extended Serial interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0, 3 to 9) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.

I2C bus interface (IIC) The I2C bus interface (IIC) has 3 channels. The IIC module conforms with and provides a subset
of the NXP I2C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) has 2 channels. The SPI provides high-speed full-duplex
synchronous serial communications with multiple processors and peripheral devices.
CAN with Flexible Data-rate (CAN-FD) The CAN with Flexible Data-rate (CAN-FD) can handle classical CAN frames and CAN-FD
frames complied with ISO 11898-1 standard.
The module supports 16 transmit buffers per channel and 16 receive buffer per channel.
USB 2.0 Full-Speed module (USBFS) The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports
all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has buffer
memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned any
endpoint number based on the peripheral devices used for communication or based on your
system.
USB 2.0 High-speed Module (USBHS) The USB 2.0 High-Speed Module (USBHS) that operates as a host or a device controller
compliant with the Universal Serial Bus (USB) Specification revision 2.0. The host controller
supports USB 2.0 high-speed, fullspeed, and low-speed transfers, and the device controller
supports USB 2.0 high-speed and full-speed transfers.
The USBHS has an internal USB transceiver and supports all of the transfer types defined in the
USB 2.0 specification.
The USBHS has FIFO buffer for data transfers, providing a maximum of 10 pipes.

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Table 1.8 Communication interfaces (2 of 2)

Feature Functional description

Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM
(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has
an SPI-compatible interface.
Octa Serial Peripheral Interface (OSPI) The Octa Serial Peripheral Interface (OSPI) module is a memory controller for connecting
OctaFlash and OctaRAM.
Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting I2S/Monaural/TDM audio data over a serial bus. The SSIE
supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master
receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO
buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception
and transmission.
SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and
4-bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports
1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451)
device access. This interface also provides backward compatibility and supports high-speed
SDR transfer modes.
Ethernet MAC (ETHERC) One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3 Media
Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the MAC
layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows transmission
and reception of frames compliant with the Ethernet and IEEE802.3 standards. The ETHERC is
connected to the Ethernet DMA Controller (EDMAC) so data can be transferred without using the
CPU.
Consumer Electronics Control module The CEC transmission/reception module can generate and receive CEC signals complied with
(CEC) the High-Definition Multimedia Interface (HDMI) Ver.1.4b.
And the module can automaticall detect communication states.

Table 1.9 Analog

Feature Functional description

12-bit A/D Converter (ADC12) Two units of 12-bit successive approximation A/D converter (ADC12) are provided. Analog input
channels are selectable up to 13 in unit 0 and up to 16 in unit 1. Each 3 analog input of unit
0 and unit 1 is assigned to the same port (AN000/AN100, AN001/AN101, and AN002/AN102),
and up to 26 ports are available as analog input. The temperature sensor output and an internal
reference voltage are selectable for conversion in each unit 0 and unit 1.
12-bit D/A Converter (DAC12) A 12-bit D/A converter (DAC12) is provided.
Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.

Table 1.10 Human machine interfaces

Feature Functional description

Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch
sensor. Changes in the electrostatic capacitance are determined by software that enables the
CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the
touch sensor is usually enclosed with an electrical conductor so that a finger does not come into
direct contact with the electrode.

Table 1.11 Data processing (1 of 2)

Feature Functional description

Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The
calculator bit order of CRC calculation results can be switched for LSB-first or MSB-first communication.
Additionally, various CRC-generation polynomials are available.

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Table 1.11 Data processing (2 of 2)

Feature Functional description

Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.

Table 1.12 I/O ports

Feature Functional description

Programmable I/O ports ● I/O ports for the 176-pin LQFP

– I/O pins: 132
– Input pins: 1
– Pull-up resistors: 133
– N-ch open-drain outputs: 132
– 5-V tolerance: 17
● I/O ports for the 176-pin BGA
– I/O pins: 132
– Input pins: 1
– Pull-up resistors: 133
– N-ch open-drain outputs: 132
– 5-V tolerance: 17
● I/O ports for the 144-pin LQFP
– I/O pins: 109
– Input pins: 1
– Pull-up resistors: 110
– N-ch open-drain outputs: 109
– 5-V tolerance: 21
● I/O ports for the 144-pin BGA
– I/O pins: 109
– Input pins: 1
– Pull-up resistors: 110
– N-ch open-drain outputs: 109
– 5-V tolerance: 21
● I/O ports for the 100-pin LQFP
– I/O pins: 75
– Input pins: 1
– Pull-up resistors: 76
– N-ch open-drain outputs: 75
– 5-V tolerance: 14
● I/O ports for the 100-pin BGA
– I/O pins: 66
– Input pins: 1
– Pull-up resistors: 67
– N-ch open-drain outputs: 66
– 5-V tolerance: 9

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1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.

Memory Bus Arm Cortex-M33 System

2 MB code flash External DSP FPU POR/LVD Clocks

CSC MOSC/SOSC
8 KB data flash
IDAU
Reset
(H/M/L) OCO
512 KB SRAM
MPU
MPU
1 KB Standby Mode control PLL/PLL2
SRAM
NVIC
Power control CAC

DMA System timer

ICU Battery backup
DTC
Test and DBG interface
Register write
DMAC × 8 protection

Timers Communication interfaces Human machine interfaces

SCI × 10 QSPI OSPI CTSU

GPT32 x 4
GPT16 x 6
IIC × 3 SDHI ETHERC

AGT × 6 SPI × 2 CAN-FD × 2 USBHS

RTC
SSIE USBFS CEC
WDT/IWDT

Event link Data processing Analog

ELC CRC ADC12 × 2 TSN

Security DOC DAC12 × 2

SCE9

Note: Not available on all parts.

Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.13 shows a
list of products.

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R7FA6M5AH3CFC #AA 0
Production identification code
Terminal material (Pb-free)
A: Sn (Tin) only
C: Others
Packing
A: Tray
B: Tray (Full carton)
U: Tray (Full tray)
H: Tape and reel
Package type
BG: FBGA 176 pins
BM: FBGA 144 pins
AG: FBGA 100 pins
FC: LQFP 176 pins
FB: LQFP 144 pins
FP: LQFP 100 pins
Quality Grade
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
F: 1 MB
G: 1.5 MB
H: 2 MB
Feature set
A: Supporting only Classical CAN
(Not supporting Flexible Data rate)
B: Supporting Classical CAN with Flexible Data rate
Group name

Series name

RA family

Flash memory

Renesas microcontroller

Note: Check the order screen for each product on the Renesas website for valid symbols after the #.

Figure 1.2 Part numbering scheme

Table 1.13 Product list (1 of 2)

Data Operating
Product part number Package code Code flash flash SRAM temperature

R7FA6M5AH2CBG PLBG0176GF-A 2 MB 8 KB 512 KB -40 to +85°C

R7FA6M5AH3CFC PLQP0176KB-C -40 to +105°C
R7FA6M5AH2CBM PLBG0144KB-A -40 to +85°C
R7FA6M5AH3CBM PLBG0144KB-A -40 to +105°C
R7FA6M5AH3CFB PLQP0144KA-B
R7FA6M5AH3CFP PLQP0100KB-B
R7FA6M5AG2CBG PLBG0176GF-A 1.5 MB -40 to +85°C
R7FA6M5AG3CFC PLQP0176KB-C -40 to +105°C
R7FA6M5AG2CBM PLBG0144KB-A -40 to +85°C
R7FA6M5AG3CBM PLBG0144KB-A -40 to +105°C
R7FA6M5AG3CFB PLQP0144KA-B
R7FA6M5AG3CFP PLQP0100KB-B

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Table 1.13 Product list (2 of 2)

Data Operating
Product part number Package code Code flash flash SRAM temperature

R7FA6M5BH2CBG PLBG0176GF-A 2 MB 8 KB 512 KB -40 to +85°C

R7FA6M5BH3CFC PLQP0176KB-C -40 to +105°C
R7FA6M5BH2CBM PLBG0144KB-A -40 to +85°C
R7FA6M5BH3CBM PLBG0144KB-A -40 to +105°C
R7FA6M5BH3CFB PLQP0144KA-B
R7FA6M5BH3CAG PLBG0100KB-A
R7FA6M5BH3CFP PLQP0100KB-B
R7FA6M5BG2CBG PLBG0176GF-A 1.5 MB -40 to +85°C
R7FA6M5BG3CFC PLQP0176KB-C -40 to +105°C
R7FA6M5BG2CBM PLBG0144KB-A -40 to +85°C
R7FA6M5BG3CBM PLBG0144KB-A -40 to +105°C
R7FA6M5BG3CFB PLQP0144KA-B
R7FA6M5BG3CAG PLBG0100KB-A
R7FA6M5BG3CFP PLQP0100KB-B
R7FA6M5BF2CBG PLBG0176GF-A 1 MB -40 to +85°C
R7FA6M5BF3CFC PLQP0176KB-C -40 to +105°C
R7FA6M5BF2CBM PLBG0144KB-A -40 to +85°C
R7FA6M5BF3CBM PLBG0144KB-A -40 to +105°C
R7FA6M5BF3CFB PLQP0144KA-B
R7FA6M5BF3CAG PLBG0100KB-A
R7FA6M5BF3CFP PLQP0100KB-B

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1.4 Function Comparison

Table 1.14 Function Comparison (1 of 2)
R7FA6M5XX2CBG R7FA6M5XXXCBM
Parts number R7FA6M5XX3CFC R7FA6M5XX3CFB R7FA6M5BX3CAG R7FA6M5XX3CFP

Pin count 176 144 100

Package BGA/LQFP BGA/LQFP BGA LQFP
Code flash memory 2 MB, 1.5 MB, 1 MB
Data flash memory 8 KB
SRAM 512 KB
Parity 448 KB
ECC 64 KB
Standby SRAM 1 KB
DMA DTC Yes
DMAC 8
BUS External bus 16-bit bus 8-bit bus
System CPU clock 200 MHz (max.)
CPU clock
MOSC, SOSC, HOCO, MOCO, LOCO, PLL
sources
CAC Yes
WDT/IWDT Yes
Backup
128 B
register
Communication SCI 10 9 10
IIC 3 2 3
SPI 2
CAN or
2
CANFD
USBFS Yes
USBHS Yes No Yes No
QSPI Yes
OSPI Yes
SSIE Yes
SDHI/MMC Yes
ETHERC Yes*3 Yes No Yes*3
CEC Yes
Timers GPT32*1 4

GPT16*1 6

AGT*1 6

RTC Yes
Analog ADC12 Unit 0: 13, Unit 1: 16 Unit 0: 12, Unit 1: 13 Unit 0: 11, Unit 1: 9
Shared channel pin: 3 Shared channel pin: 3 Shared channel pin: 3
*2 *2 *2

DAC12 2
TSN Yes
HMI CTSU 15 20 6 12

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Table 1.14 Function Comparison (2 of 2)

R7FA6M5XX2CBG R7FA6M5XXXCBM
Parts number R7FA6M5XX3CFC R7FA6M5XX3CFB R7FA6M5BX3CAG R7FA6M5XX3CFP

Data processing CRC Yes

DOC Yes
Event control ELC Yes
Security SCE9, TrustZone, and Lifecycle management
I/O ports I/O pins 132 109 66 75
Input pins 1 1 1 1
Pull-up 67
133 110 76
resistors
N-ch open- 66
132 109 75
drain outputs
5-V tolerance 17 21 9 14
Note: The product name differs depending on the memory size and whether CAN or CANFD is supported. See section 1.3. Part
Numbering.
Note 1. Available pins depend on the Package type. For details, see section 1.7. Pin Lists.
Note 2. Some input channels of the ADC units are sharing the same port pin.
Note 3. Available for RMII only.

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1.5 Pin Functions

Table 1.15 Pin functions (1 of 7)
Function Signal I/O Description

Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. The capacitor should be
placed close to the pin.
VCL/VCL0 I/O Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VBATT Input Battery Backup power pin
VSS Input Ground pin. Connect it to the system power supply (0 V).
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT Output
CLKOUT Output Clock output pin
Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC CACREF Input Measurement reference clock input pin
On-chip emulator TMS Input On-chip emulator or boundary scan pins
TDI Input
TCK Input
TDO Output
TCLK Output Output clock for synchronization with the trace data
TDATA0 to TDATA3 Output Trace data output
SWO Output Serial wire trace output pin
SWDIO I/O Serial wire debug data input/output pin
SWCLK Input Serial wire clock pin
Interrupt NMI Input Non-maskable interrupt request pin
IRQn Input Maskable interrupt request pins
IRQn-DS Input Maskable interrupt request pins that can also be used in Deep
Software Standby mode

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Table 1.15 Pin functions (2 of 7)

Function Signal I/O Description

External bus interface RD Output Strobe signal indicating that reading from the external bus interface
space is in progress, active-low
WR Output Strobe signal indicating that writing to the external bus interface
space is in progress, in 1-write strobe mode, active-low
WRn Output Strobe signals indicating that either group of data bus pins (D07 to
D00 or D15 to D08) is valid in writing to the external bus interface
space, in byte strobe mode, active-low
BCn Output Strobe signals indicating that either group of data bus pins (D07 to
D00 or D15 to D08) is valid in access to the external bus interface
space, in 1-write strobe mode, active-low
ALE Output Address latch signal when address/data multiplexed bus is selected
WAIT Input Input pin for wait request signals in access to the external space,
active-low
CSn Output Select signals for CS areas, active-low
A00 to A23 Output Address bus
D00 to D15 I/O Data bus
A00/D00 to A15/D15 I/O Address/data multiplexed bus
GPT GTETRGA, GTETRGB, Input External trigger input pins
GTETRGC, GTETRGD
GTIOCnA, GTIOCnB I/O Input capture, output compare, or PWM output pins
GTIU Input Hall sensor input pin U
GTIV Input Hall sensor input pin V
GTIW Input Hall sensor input pin W
GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase)
GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase)
AGT AGTEEn Input External event input enable signals
AGTIOn I/O External event input and pulse output pins
AGTOn Output Pulse output pins
AGTOAn Output Output compare match A output pins
AGTOBn Output Output compare match B output pins
RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock
RTCICn Input Time capture event input pins

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Table 1.15 Pin functions (3 of 7)

Function Signal I/O Description

SCI SCKn I/O Input/output pins for the clock (clock synchronous mode)
RXDn Input Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn Output Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn I/O Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), active-
low.
CTSn Input Input for the start of transmission.
SCLn I/O Input/output pins for the IIC clock (simple IIC mode)
SDAn I/O Input/output pins for the IIC data (simple IIC mode)
SCKn I/O Input/output pins for the clock (simple SPI mode)
MISOn I/O Input/output pins for slave transmission of data (simple SPI mode)
MOSIn I/O Input/output pins for master transmission of data (simple SPI mode)
RXDXn Input Input pins for received data (Extended Serial Mode)
TXDXn Output Output pins for transmitted data (Extended Serial Mode)
SIOXn I/O Input/output pins for received or transmitted data (Extended Serial
Mode)
SSn Input Chip-select input pins (simple SPI mode), active-low
IIC SCLn I/O Input/output pins for the clock
SDAn I/O Input/output pins for data
SPI RSPCKA, RSPCKB I/O Clock input/output pin
MOSIA, MOSIB I/O Input or output pins for data output from the master
MISOA, MISOB I/O Input or output pins for data output from the slave
SSLA0, SSLB0 I/O Input or output pin for slave selection
SSLA1 to SSLA3, SSLB1 Output Output pins for slave selection
to SSLB3
CAN or CANFD CRXn Input Receive data
CTXn Output Transmit data

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Table 1.15 Pin functions (4 of 7)

Function Signal I/O Description

USBFS VCC_USB Input Power supply pin

VSS_USB Input Ground pin
USB_DP I/O D+ pin of the USB on-chip transceiver. Connect this pin to the D+
pin of the USB bus.
USB_DM I/O D- pin of the USB on-chip transceiver. Connect this pin to the D- pin
of the USB bus.
USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the
USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
USB_EXICEN Output Low-power control signal for external power supply (OTG) chip
USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA, Input Connect the external overcurrent detection signals to these pins.
USB_OVRCURB Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_OVRCURA-DS, Input Overcurrent pins for USBFS that can also be used in Deep Software
USB_OVRCURB-DS Standby mode.
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_ID Input Connect the MicroAB connector ID input signal to this pin during
operation in OTG mode
USBHS VCC_USBHS Input Power supply pin
VSS1_USBHS, Input Ground pin
VSS2_USBHS
AVCC_USBHS Input Analog power supply
AVSS_USBHS Input Analog ground pin
Must be shorted to the PVSS_USBHS pin
PVSS_USBHS Input PLL circuit ground pin for the USBHS
Must be shorted to the AVSS_USBHS pin.
USBHS_RREF I/O Reference current source pin for the USBHS
Must be connected to the AVSS_USBHS pin through a 2.2-kΩ
(±1%) resistor.
USBHS_DP I/O Input/output pin for the D+ data line of the USB bus
USBHS_DM I/O Input/output pin for the D- data line of the USB bus
USBHS_EXICEN Output Must be connected to the OTG power supply IC
USBHS_ID input Must be connected to the OTG power supply IC
USBHS_VBUSEN Output VBUS power supply enable pin for the USBHS
USBHS_OVRCURA, Input Overcurrent pin for the USBHS
USBHS_OVRCURB
USBHS_VBUS Input USB cable connection monitor input pin
QSPI QSPCLK Output QSPI clock output pin
QSSL Output QSPI slave output pin
QIO0 to QIO3 I/O Data0 to Data3

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Table 1.15 Pin functions (5 of 7)

Function Signal I/O Description

OSPI OM_SCLK Output Clock output (OCTACLK divided by 2)

OM_CSn Output Chip select signal for an OctaFlash device, active-low
OM_DQS I/O Read data strobe/write data mask signal
OM_SIOn I/O Data input/output
OM_RESET Output Reset signal for both OctaFlash and OctaRAM devices, active-low
OM_ECS Input ECC error detection signal from the external memory, active-low
SSIE SSIBCK0 I/O SSIE serial bit clock pins
SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins
SSITXD0 Output Serial data output pin
SSIRXD0 Input Serial data input pin
SSIDATA0 I/O Serial data input/output pins
AUDIO_CLK Input External clock pin for audio (input oversampling clock)
SDHI/MMC SD0CLK Output SD/MMC clock output pins
SD0CMD I/O Command output pin and response input signal pins
SD0DAT0 to SD0DAT7 I/O SD/MMC data bus pins
SD0CD Input SD/MMC card detection pins
SD0WP Input SD/MMC write-protect signals

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Table 1.15 Pin functions (6 of 7)

Function Signal I/O Description

ETHERC REF50CK0 Input 50-MHz reference clock. This pin inputs reference signal for
transmission/reception timing in RMII mode.
RMII0_CRS_DV Input Indicates carrier detection signals and valid receive data on
RMII0_RXD1 and RMII0_RXD0 in RMII mode.
RMII0_TXDn Output 2-bit transmit data in RMII mode
RMII0_RXDn Input 2-bit receive data in RMII mode
RMII0_TXD_EN Output Output pin for data transmit enable signal in RMII mode
RMII0_RX_ER Input Indicates an error occurred during reception of data in RMII mode.
ET0_CRS Input Carrier detection/data reception enable signal
ET0_RX_DV Input Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0
ET0_EXOUT Output General-purpose external output pin
ET0_LINKSTA Input Input link status from the PHY-LSI
ET0_ETXDn Output 4 bits of MII transmit data
ET0_ERXDn Input 4 bits of MII receive data
ET0_TX_EN Output Transmit enable signal. Functions as signal indicating that transmit
data is ready on ET0_ETXD3 to ET0_ETXD0.
ET0_TX_ER Output Transmit error pin. Functions as signal notifying the PHY_LSI of an
error during transmission.
ET0_RX_ER Output Receive error pin. Functions as signal to recognize an error during
reception.
ET0_TX_CLK Input Transmit clock pin. This pin inputs reference signal for output timing
from ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER.
ET0_RX_CLK Input Receive clock pin. This pin inputs reference signal for input timing to
ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER.
ET0_COL Input Input collision detection signal
ET0_WOL Output Receive Magic packets
ET0_MDC Output Output reference clock signal for information transfer through
ET0_MDIO
ET0_MDIO I/O Input or output bidirectional signal for exchange of management
data with PHY-LSI
Analog power supply AVCC0 Input Analog voltage supply pin. This is used as the analog power supply
for the respective modules. Supply this pin with the same voltage as
the VCC pin.
AVSS0 Input Analog ground pin. This is used as the analog ground for the
respective modules. Supply this pin with the same voltage as the
VSS pin.
VREFH Input Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to AVCC0 when not using the ADC12
(unit 1) and D/A Converter.
VREFL Input Analog reference ground pin for the ADC12 and D/A Converter.
Connect this pin to AVSS0 when not using the ADC12 (unit 1) and
D/A Converter.
VREFH0 Input Analog reference voltage supply pin for the ADC12 (unit 0). Connect
this pin to AVCC0 when not using the ADC12 (unit 0).
VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12 (unit 0).

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Table 1.15 Pin functions (7 of 7)

Function Signal I/O Description

ADC12 ANmn Input Input pins for the analog signals to be processed by the A/D
converter.
(m: ADC unit number, n: pin number)
ADTRGm Input Input pins for the external trigger signals that start the A/D
conversion, active-low.
DAC12 DAn Output Output pins for the analog signals processed by the D/A converter.
CTSU TSn Input Capacitive touch detection pins (touch pins)
TSCAP I/O Secondary power supply pin for the touch driver
I/O ports Pmn I/O General-purpose input/output pins
(m: port number, n: pin number)
P200 Input General-purpose input pin
CEC CECIO I/O CEC data communication

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1.6 Pin Assignments

The following figures show the pin assignments from the top view.

P108/TMS/SWDIO
P109/TDO
P110/TDI
PA00
PA01

PA10
PA09
PA08
P100
P101
P102
P103
P104
P105
P106
P107

P600
P601
P602
P603
P604
P605
P606
P607

P615
P614
P613
P612

P610
P609
P608
P611

P115
P114
P113
P112
P111
VCC

VCC

VCC
VSS

VSS

VSS
VCL
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P800 133 88 P300/TCK/SWCLK
P801 134 87 P301
P802 135 86 P302
P803 136 85 P303
P804 137 84 VCC
VCC 138 83 VSS
VSS 139 82 P304
P500 140 81 P305
P501 141 80 P306
P502 142 79 P307
P503 143 78 P308
P504 144 77 P309
P505 145 76 P310
P506 146 75 P311
P507 147 74 P312
P508 148 73 P905
VCC 149 72 P906
VSS 150 71 P907
P015 151 70 P908
P014 152 69 P200
VREFL 153 68 P201/MD
VREFH 154 67 RES
AVCC0 155 66 P208
AVSS0 156 65 P209
VREFL0 157 64 P210
VREFH0 158 63 P211
P010 159 62 P214
P009 160 61 VCC
P008 161 60 VSS
P007 162 59 P901
P006 163 58 P900
P005 164 57 P315
P004 165 56 P314
P003 166 55 P313
P002 167 54 P202
P001 168 53 P203
P000 169 52 P204
VSS 170 51 P205
VCC 171 50 P206
P806 172 49 P207
P805 173 48 VCC_USB
P513 174 47 USB_DP
P512 175 46 USB_DM
P511 176 45 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
P400
P401
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705
P706
P707
PB00
PB01

VCL0
XCIN
XCOUT
VSS

VCC

USBHS_RREF

PVSS_USBHS
VSS2_USBHS
USBHS_DM
USBHS_DP
VSS1_USBHS
VCC_USBHS
P708
P415
P414
P413
P412

P408
P407
P410
P409
VBATT

P213/XTAL
P212/EXTAL

AVSS_USBHS
AVCC_USBHS

P411

Figure 1.3 Pin assignment for LQFP 176-pin

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A B C D E F G H J K L M N P R

USBHS_ PVSS_ P212

15 P407 P409 P411 P414 P708 XCIN VCL0 P707 P703 P700 P405 P401 15
DM USBHS /EXTAL

USBHS_ AVSS_ P213

14 USB_DP USB_DM P410 P412 P415 XCOUT VBATT P706 P701 P406 P402 P512 14
DP USBHS /XTAL

VCC_ VSS_ VCC_ USBHS_ AVCC_

13 P204 P408 P413 VSS PB01 P704 P404 P400 P511 P805 13
USB USB USBHS RREF USBHS

VSS1_ VSS2_
12 P313 P202 P207 P206 P205 VCC PB00 P705 P702 P403 P513 P806 P000 12
USBHS USBHS

11 P900 P315 P314 P203 VCC P001 P004 P002 11

10 P214 P211 P901 VSS VSS P006 P008 P005 10

9 P210 P209 RES VCC P009 AVSS0 VREFL0 VREFH0 9

8 P208 P201/MD P200 P908 P010 AVCC0 VREFL VREFH 8

7 P906 P905 P312 P907 VCC VSS P015 P014 7

6 P310 P309 P307 P311 P007 P507 P505 P508 6

5 P308 P305 VSS VCC P003 P503 P504 P506 5

P300/TCK
4 P306 P304 P111 VSS P613 PA09 PA00 P607 VCC VSS VSS VCC P501 P502 4
/SWCLK

P108/TMS
3 P303 P302 P110/TDI VCC P610 VCC VSS P604 P603 P105 P102 P800 P804 P500 3
SWDIO

2 P301 P112 P114 P608 P611 P614 PA10 PA01 P605 P601 P107 P104 P101 P802 P803 2

1 P109/TDO P113 P115 P609 P612 P615 PA08 VCL P606 P602 P600 P106 P103 P100 P801 1

A B C D E F G H J K L M N P R

Figure 1.4 Pin assignment for BGA 176-pin

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P108/TMS/SWDIO
P109/TDO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107

P600
P601
P602
P603
P604
P605

P614
P613
P612

P610
P609
P608
P611

P115
P114
P113
P112
P111
VCC

VCC

VCC
VSS

VSS

VSS
VCL
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P800 109 72 P300/TCK/SWCLK
P801 110 71 P301
VCC 111 70 P302
VSS 112 69 P303
P500 113 68 VCC
P501 114 67 VSS
P502 115 66 P304
P503 116 65 P305
P504 117 64 P306
P505 118 63 P307
P506 119 62 P308
P507 120 61 P309
VCC 121 60 P310
VSS 122 59 P311
P015 123 58 P312
P014 124 57 P200
VREFL 125 56 P201/MD
VREFH 126 55 RES
AVCC0 127 54 P208
AVSS0 128 53 P209
VREFL0 129 52 P210
VREFH0 130 51 P211
P009 131 50 P214
P008 132 49 VCC
P007 133 48 VSS
P006 134 47 P313
P005 135 46 P202
P004 136 45 P203
P003 137 44 P204
P002 138 43 P205
P001 139 42 P206
P000 140 41 P207
VSS 141 40 VCC_USB
VCC 142 39 USB_DP
P512 143 38 USB_DM
P511 144 37 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
P400
P401
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705

VCL0
XCIN
XCOUT
VSS

VCC
P713
P712

P710
P709
P708
P415
P414
P413
P412

P409
P408
P407
P410
VBATT

P213/XTAL
P212/EXTAL

P711

P411

Figure 1.5 Pin assignment for LQFP 144-pin

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A B C D E F G H J K L M N

P212 P213
13 P408 P410 P412 /EXTAL XCOUT XCIN P705 P700 P405 P403 P400 P401 13
/XTAL

12 USB_DM P407 P413 P414 P708 P711 P713 P703 P702 P404 P402 P511 P512 12

11 USB_DP P409 P411 P415 P710 P712 P709 P704 P701 P406 P001 P002 P000 11

10 P206 P207 P205 VCC_USB VSS_USB VCC VSS VCL0 VBATT VCC P005 P004 P003 10

9 P202 P204 P203 VSS VSS P007 P009 P006 9

8 P211 P214 P313 VCC P008 AVSS0 VREFL0 VREFH0 8

7 P208 P210 P209 VSS VSS AVCC0 VREFL VREFH 7

6 P200 P201/MD RES VCC VCC P503 P014 P015 6

5 P309 P311 P310 VSS VSS P505 P507 P506 5

4 P305 P306 P312 VSS VCC VCC VSS VCL VCC VCC P502 P501 P504 4

3 P304 P307 P308 P110/TDI P114 P608 P610 P605 P603 P105 P102 P500 P801 3

P108/TMS
2 P303 P301 P109/TDO P112 P612 P614 P604 P601 P107 P104 P101 P800 2
/SWDIO

P300/TCK
1 P302 P111 P113 P115 P609 P611 P613 P602 P600 P106 P103 P100 1
/SWCLK

A B C D E F G H J K L M N

Figure 1.6 Pin assignment for BGA 144-pin

P108/TMS/SWDIO
P109/TDO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602

P610
P609
P608
P115
P114
P113
P112
P111
VCC
VSS
VCL
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75

P500 76 50 P300/TCK/SWCLK
P501 77 49 P301
P502 78 48 P302
P503 79 47 P303
P504 80 46 VCC
P505 81 45 VSS
VCC 82 44 P304
VSS 83 43 P305
P015 84 42 P306
P014 85 41 P307
VREFL 86 40 P200
VREFH 87 39 P201/MD
AVCC0 88 38 RES
AVSS0 89 37 P208
VREFL0 90 36 P209
VREFH0 91 35 P210
P008 92 34 P211
P007 93 33 P214
P006 94 32 P205
P005 95 31 P206
P004 96 30 P207
P003 97 29 VCC_USB
P002 98 28 USB_DP
P001 99 27 USB_DM
P000 100 26 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9

VSS

VCC
P400
P401
P402
P403
P404
P405
P406

P708
P415
P414
P413
P412

P410
P409
P408
P407
XCIN
VCL0

P411
XCOUT
VBATT

P213/XTAL
P212/EXTAL

Figure 1.7 Pin assignment for LQFP 100-pin

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A B C D E F G H J K L M N

USBHS_ USBHS_ VSS2_ P212 P213

13 PB00 XCOUT XCIN P403 P401 P400 13
DP DM USBHS EXTAL /XTAL

VSS1_ VCC_ PVSS_ AVSS_ AVCC_

12 P409 PB01 P706 P402 P005 P001 P002 P000 12
USBHS USBHS USBHS USBHS USBHS

USBHS_
11 P708 P707 P004 11
RREF

10 P408 P407 P007 P003 10

9 USB_DM VSS_USB VCL0 P008 P006 9

8 USB_DP VCC_USB P207 VCC VSS VBATT AVSS0 VREFH0 VREFL0 8

7 P214 P206 P205 VSS VCC VSS VREFH VREFL 7

6 P210 P211 P209 VCC VSS VCC AVCC0 P014 P015 6

5 RES P208 VCL P503 P505 5

4 P201/MD P200 P501 P504 4

3 P301 P610 P105 P502 3

P300/TCK P108/TMS
2 P303 P110/TDI P112 P114 P608 P601 P107 P104 P102 P101 P500 2
/SWCLK /SWDIO

1 P302 P109/TDO P111 P113 P115 P609 P602 P600 P106 P103 P100 1

A B C D E F G H J K L M N

Figure 1.8 Pin assignment for BGA 100-pin

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1.7 Pin Lists

Table 1.16 Pin list (1 of 5)
LQFP176

LQFP144

LQFP100
BGA176

BGA144

BGA100

Power, System, SCI/IIC/SPI/CAN/USBFS/USBHS/

Clock, Debug, I/O QSPI/OSPI/SSIE/SDHI/MMC/
CAC ports Ex. Bus Ex. Interrupt EHTERC(MII,RMII)/CEC GPT/AGT/RTC ADC12/DAC12 CTSU

N13 1 M13 1 N13 1 — P400 — IRQ0 SCK4/SCK7/SCL0_A/AUDIO_CLK/ GTIOC6A/AGTIO1 ADTRG1 —

ET0_WOL/ET0_WOL

R15 2 N13 2 M13 2 — P401 — IRQ5-DS CTS4_RTS4/TXD7/SDA0_A/CTX0/ GTETRGA/GTIOC6B — —

ET0_MDC/ET0_MDC

P14 3 L12 3 J12 3 CACREF P402 — IRQ4-DS CTS4/RXD7/CRX0/AUDIO_CLK/ AGTIO0/AGTIO1/ — —

ET0_MDIO/ET0_MDIO AGTIO2/AGTIO3/
RTCIC0

M12 4 L13 4 K13 4 — P403 — IRQ14-DS CTS7_RTS7/SSIBCK0_A/ GTIOC3A/AGTIO0/ — —

ET0_LINKSTA/ET0_LINKSTA AGTIO1/AGTIO2/
AGTIO3/RTCIC1

M13 5 K12 5 — — 5 — P404 — IRQ15-DS CTS7/SSILRCK0_A/ GTIOC3B/ —

ET0_EXOUT/ AGTIO0_G/
ET0_EXOUT AGTIO1/AGTIO2/
AGTIO3/RTCIC2

P15 6 K13 6 — 6 — P405 — — SSITXD0_A/ET0_TX_EN/ GTIOC1A — —

RMII0_TXD_EN_B

N14 7 K11 7 — 7 — P406 — — SSLA3_C/SSIRXD0_A/ET0_RX_ER/ GTIOC1B/AGTO5 — —

RMII0_TXD1_B

N15 8 J13 8 — — — P700 — — MISOA_C/ET0_ETXD1/ GTIOC5A/AGTO4 — —

RMII0_TXD0_B

M14 9 J11 9 — — — P701 — — MOSIA_C/ET0_ETXD0/REF50CK0_B GTIOC5B/AGTO3 — —

L12 10 J12 10 — — — P702 — — RSPCKA_C/ET0_ERXD1/ GTIOC6A/AGTO2 — —

RMII0_RXD0_B

M15 11 H12 11 — — — P703 — — SSLA0_C/ET0_ERXD0/ GTIOC6B/AGTO1 — —

RMII0_RXD1_B

L13 12 H11 12 — — — P704 — — SSLA1_C/CTX0/ET0_RX_CLK/ AGTO0 — —

RMII0_RX_ER_B

K12 13 H13 13 — — — P705 — — CTS3/SSLA2_C/CRX0/ET0_CRS/ AGTIO0 — —

RMII0_CRS_DV_B

L14 14 — — H12 — — P706 — IRQ7 USBHS_OVRCURB/RXD3_B — — —

L15 15 — — H11 — — P707 — IRQ8 USBHS_OVRCURA/TXD3_B — — —

J12 16 — — E13 — — PB00 — — USBHS_VBUSEN/SCK3_B — — —

K13 17 — — G12 — — PB01 — — USBHS_VBUS/CTS_RTS3_B — — —

K14 18 J10 14 H8 8 VBATT — — — — — — —

K15 19 H10 15 G9 9 VCL0 — — — — — — —

J15 20 G13 16 J13 10 XCIN — — — — — — —

J14 21 F13 17 H13 11 XCOUT — — — — — — —

J13 22 G10 18 G8 12 VSS — — — — — — —

H14 23 E13 19 G13 13 XTAL P213 — IRQ2 TXD1 GTETRGC/GTIOC0A/ ADTRG1 —

AGTEE2

H15 24 D13 20 F13 14 EXTAL P212 — IRQ3 RXD1 GTETRGD/GTIOC0B/ — —

AGTEE1

H12 25 F10 21 F8 15 VCC — — — — — — —

H13 26 — — F12 — AVCC_USBHS — — — — — — —

G13 27 — — F11 — USBHS_RREF — — — — — — —

G14 28 — — E12 — AVSS_USBHS — — — — — — —

G15 29 — — C12 — PVSS_USBHS — — — — — — —

G12 30 — — D13 — VSS2_USBHS — — — — — — —

F15 31 — — B13 — USBHS_DM — — — — — — —

F14 32 — — A13 — USBHS_DP — — — — — — —

F12 33 — — A12 — VSS1_USBHS — — — — — — —

F13 34 — — B12 — VCC_USBHS — — — — — — —

— — G12 22 — — — P713 — — — GTIOC2A/AGTOA0 — TS17

— — F11 23 — — — P712 — — — GTIOC2B/AGTOB0 — TS16

— — F12 24 — — — P711 — — CTS1_RTS1/ET0_TX_CLK AGTEE0 — TS15

— — E11 25 — — — P710 — — SCK1/ET0_TX_ER — — TS14

R01DS0366EJ0140 Rev.1.40 Page 24 of 123

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RA6M5 Datasheet 1. Overview

Table 1.16 Pin list (2 of 5)

LQFP176

LQFP144

LQFP100
BGA176

BGA144

BGA100
Power, System, SCI/IIC/SPI/CAN/USBFS/USBHS/
Clock, Debug, I/O QSPI/OSPI/SSIE/SDHI/MMC/
CAC ports Ex. Bus Ex. Interrupt EHTERC(MII,RMII)/CEC GPT/AGT/RTC ADC12/DAC12 CTSU

— — G11 26 — — — P709 — IRQ10 TXD1/ET0_ETXD2 — — TS13

E15 35 E12 27 B11 16 CACREF P708 — IRQ11 RXD1/SSLB3_B/AUDIO_CLK/ — — TS12

ET0_ETXD3/CECIO

E14 36 D11 28 — 17 — P415 — IRQ8 SCL2_B/SSLB2_B/USB_VBUSEN/ GTIOC0A/AGTIO4 — TS11

SD0CD/ET0_TX_EN/
RMII0_TXD_EN_A

D15 37 D12 29 — 18 — P414 — IRQ9 SDA2_B/CTS0/SSLB1_B/SD0WP/ GTIOC0B/AGTIO5 — TS10

ET0_RX_ER/RMII0_TXD1_A

E13 38 C12 30 — 19 — P413 — — CTS0_RTS0/SSLB0_B/SD0CLK_A/ GTOUUP/AGTEE3 — TS09

ET0_ETXD1/RMII0_TXD0_A

D14 39 C13 31 — 20 — P412 — — SCK0/CTS3/RSPCKB_B/SD0CMD_A/ GTOULO/AGTEE1 — TS08

ET0_ETXD0/REF50CK0_A

C15 40 C11 32 — 21 — P411 — IRQ4 TXD0/CTS3_RTS3/MOSIB_B/ GTOVUP/GTIOC9A/ — TS07

SD0DAT0_A/ET0_ERXD1/ AGTOA1
RMII0_RXD0_A

C14 41 B13 33 — 22 — P410 — IRQ5 RXD0/SCL2_A/SCK3/MISOB_B/ GTOVLO/GTIOC9B/ — TS06

SD0DAT1_A/ET0_ERXD0/ AGTOB1
RMII0_RXD1_A

B15 42 B11 34 D12 23 — P409 — IRQ6 TXD3/SDA2_A/USB_EXICEN/ GTOWUP/AGTOA2 — TS05

USBHS_EXICEN/ET0_RX_CLK/
RMII0_RX_ER_A

D13 43 A13 35 A10 24 — P408 — IRQ7 CTS4/RXD3/SCL0_B/USB_ID/ GTOWLO/GTIOC6B/ — TS04

USBHS_ID/ET0_CRS/ AGTOB2
RMII0_CRS_DV_A

A15 44 B12 36 B10 25 — P407 — — CTS4_RTS4/SDA0_B/SSLA3_A/ GTIOC6A/AGTIO0/ ADTRG0 TS03

USB_VBUS/ET0_EXOUT/ RTCOUT
ET0_EXOUT

C13 45 E10 37 B9 26 VSS_USB — — — — — — —

B14 46 A12 38 A9 27 USB_DM — — — — — — —

A14 47 A11 39 A8 28 USB_DP — — — — — — —

B13 48 D10 40 B8 29 VCC_USB — — — — — — —

C12 49 B10 41 C8 30 — P207 A17 — TXD4/SSLA2_A/QSSL — — TSCAP

D12 50 A10 42 B7 31 — P206 WAIT IRQ0-DS RXD4/CTS9/SDA1_B/SSLA1_A/ GTIU — TS02

USB_VBUSEN/SD0DAT2_A/
ET0_LINKSTA/ET0_LINKSTA/CECIO/
SSIDATA0_C

E12 51 C10 43 E7 32 CLKOUT P205 A16 IRQ1-DS TXD4/CTS9_RTS9/SCL1_B/ GTIV/GTIOC4A/AGTO1 — TS01

SSLA0_A/USB_OVRCURA-
DS/SSILRCK0_C/SD0DAT3_A/
ET0_WOL/ET0_WOL

A13 52 B9 44 — — CACREF P204 A18 — SCK4/SCK9/RSPCKA_A/ GTIW/GTIOC4B/ — TS00

USB_OVRCURB-DS/SSIBCK0_C/ AGTIO1
SD0DAT4_A/ET0_RX_DV

D11 53 C9 45 — — — P203 A19 IRQ2-DS CTS2_RTS2/TXD9/MOSIA_A/CTX0/ GTIOC5A/AGTOA3 — TS18

SD0DAT5_A/ET0_COL

B12 54 A9 46 — — — P202 WR1/BC1 IRQ3-DS SCK2/RXD9/MISOA_A/CRX0/ GTIOC5B/AGTOB3 — TS19

SD0DAT6_A/ET0_ERXD2

A12 55 C8 47 — — — P313 A20 — SD0DAT7_A/ET0_ERXD3 — — —

C11 56 — — — — — P314 A21 — — — ADTRG0 —

B11 57 — — — — — P315 A22 — RXD4_C — — —

A11 58 — — — — — P900 A23 — TXD4_C — — —

C10 59 — — — — — P901 — — SCK4_C AGTIO1_E — —

D10 60 D9 48 — — VSS — — — — — — —

D9 61 D8 49 — — VCC — — — — — — —

A10 62 B8 50 A7 33 TCLK P214 — — QSPCLK/SD0CLK_B/ET0_MDC/ GTIU/AGTO5 — —

ET0_MDC

B10 63 A8 51 B6 34 TDATA0 P211 CS7 — QIO0/SD0CMD_B/ET0_MDIO/ GTIV/AGTOA5 — —

ET0_MDIO

A9 64 B7 52 A6 35 TDATA1 P210 CS6 — QIO1/SD0CD/ET0_WOL/ET0_WOL GTIW/AGTOB5 — —

B9 65 C7 53 C6 36 TDATA2 P209 CS5 — QIO2/SD0WP/ET0_EXOUT/ GTOVUP/AGTEE5 — —

ET0_EXOUT

A8 66 A7 54 B5 37 TDATA3 P208 CS4 — QIO3/SD0DAT0_B/ET0_LINKSTA/ GTOVLO — —

ET0_LINKSTA

R01DS0366EJ0140 Rev.1.40 Page 25 of 123

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RA6M5 Datasheet 1. Overview

Table 1.16 Pin list (3 of 5)

LQFP176

LQFP144

LQFP100
BGA176

BGA144

BGA100
Power, System, SCI/IIC/SPI/CAN/USBFS/USBHS/
Clock, Debug, I/O QSPI/OSPI/SSIE/SDHI/MMC/
CAC ports Ex. Bus Ex. Interrupt EHTERC(MII,RMII)/CEC GPT/AGT/RTC ADC12/DAC12 CTSU

C9 67 C6 55 A5 38 RES — — — — — — —

B8 68 B6 56 A4 39 MD P201 — — — — — —

C8 69 A6 57 B4 40 — P200 — NMI — — — —

D8 70 — — — — — P908 — IRQ11 USBHS_EXICEN — — —

D7 71 — — — — — P907 — IRQ10 USBHS_ID — — —

A7 72 — — — — — P906 — IRQ9 USB_EXICEN_C — — —

B7 73 — — — — — P905 — IRQ8 USB_ID_C — — —

C7 74 C4 58 — — — P312 CS3 — CTS3_RTS3 AGTOA1 — —

D6 75 B5 59 — — — P311 CS2 — SCK3 AGTOB1 — —

A6 76 C5 60 — — — P310 A15 — TXD3/QIO3 AGTEE1 — —

B6 77 A5 61 — — — P309 A14 — RXD3/QIO2 AGTOA4 — —

A5 78 C3 62 — — — P308 A13 — CTS6/CTS3/QIO1 AGTOB4 — —

C6 79 B3 63 — 41 — P307 A12 — CTS6_RTS6/QIO0 GTOUUP_D/AGTEE4 — —

A4 80 B4 64 — 42 — P306 A11 — SCK6/QSSL GTOULO_D/AGTOA2 — —

B5 81 A4 65 — 43 — P305 A10 IRQ8 TXD6/QSPCLK GTOWUP/AGTOB2 — —

B4 82 A3 66 — 44 — P304 A9 IRQ9 RXD6 GTOWLO/GTIOC7A/ — —

AGTEE2

C5 83 D7 67 F7 45 VSS — — — — — — —

D5 84 D6 68 F6 46 VCC — — — — — — —

A3 85 A2 69 A2 47 — P303 A8 — CTS9 GTIOC7B — —

B3 86 A1 70 A1 48 — P302 A7 IRQ5 TXD2/SSLA3_B GTOUUP/GTIOC4A — —

A2 87 B2 71 B3 49 — P301 A6 IRQ6 RXD2/CTS9_RTS9/SSLA2_B GTOULO/GTIOC4B/ — —

AGTIO0

C4 88 B1 72 B2 50 TCK/SWCLK P300 — — SSLA1_B GTOUUP/GTIOC0A — —

C3 89 C2 73 C2 51 TMS/SWDIO P108 — — CTS9_RTS9/SSLA0_B GTOULO/GTIOC0B/ — —

AGTOA3

A1 90 D2 74 B1 52 TDO/SWO/CLKOUT P109 — — TXD9/MOSIA_B/CTX1 GTOVUP/GTIOC1A/ — —

AGTOB3

D3 91 D3 75 D2 53 TDI P110 — IRQ3 CTS2_RTS2/RXD9/MISOA_B/CRX1 GTOVLO/GTIOC1B/ — —

AGTEE3

D4 92 C1 76 D1 54 — P111 A5 IRQ4 SCK2/SCK9/RSPCKA_B GTIOC3A/AGTOA5 — —

B2 93 E2 77 E2 55 — P112 A4 — TXD2/SCK1/SSLA0_B/QSSL/ GTIOC3B/AGTOB5 — —

OM_CS1/SSIBCK0_B

B1 94 D1 78 E1 56 — P113 A3 — RXD2/SSILRCK0_B GTIOC2A/AGTEE5 — —

C2 95 E3 79 F2 57 — P114 A2 — CTS9/SSIRXD0_B GTIOC2B/AGTIO5 — —

C1 96 E1 80 F1 58 — P115 A1 — SSITXD0_B GTIOC4A — —

E3 97 E4 81 — — VCC — — — — — — —

E4 98 D5 82 — — VSS — — — — — — —

D2 99 F3 83 G2 59 — P608 A0/BC0 — — GTIOC4B — —

D1 100 F1 84 G1 60 — P609 CS1 — CTX1/OM_ECS GTIOC5A/AGTO5 — —

F3 101 G3 85 F3 61 — P610 CS0 — CTS7/CRX1/OM_CS0 GTIOC5B/AGTO4 — —

E2 102 G1 86 — — CACREF/CLKOUT P611 — — CTS7_RTS7 AGTO3 — —

E1 103 F2 87 — — — P612 D8 — SCK7 AGTO2 — —

F4 104 H1 88 — — — P613 D9 — TXD7 AGTO1 — —

F2 105 G2 89 — — — P614 D10 — RXD7 AGTO0 — —

F1 106 — — — — — P615 — IRQ7 USB_VBUSEN_D — — —

G1 107 — — — — — PA08 — IRQ6 USB_OVRCURA_C — — —

G4 108 — — — — — PA09 — IRQ5 USB_OVRCURB_C — — —

G2 109 — — — — — PA10 — IRQ4 — — — —

G3 110 F4 90 H6 62 VCC — — — — — — —

H3 111 D4 91 G6 63 VSS — — — — — — —

H1 112 H4 92 G5 64 VCL — — — — — — —

R01DS0366EJ0140 Rev.1.40 Page 26 of 123

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RA6M5 Datasheet 1. Overview

Table 1.16 Pin list (4 of 5)

LQFP176

LQFP144

LQFP100
BGA176

BGA144

BGA100
Power, System, SCI/IIC/SPI/CAN/USBFS/USBHS/
Clock, Debug, I/O QSPI/OSPI/SSIE/SDHI/MMC/
CAC ports Ex. Bus Ex. Interrupt EHTERC(MII,RMII)/CEC GPT/AGT/RTC ADC12/DAC12 CTSU

H2 113 — — — — — PA01 — — SCK8_C — — —

H4 114 — — — — — PA00 — — TXD8_C — — —

J4 115 — — — — — P607 — — RXD8_C — — —

J1 116 — — — — — P606 — — CTS_RTS8_C RTCOUT_B — —

J2 117 H3 93 — — — P605 D11 — CTS8 GTIOC8A/AGTO4 — —

J3 118 H2 94 — — — P604 D12 — CTS9 GTIOC8B/AGTEE4 — —

K3 119 J3 95 — — — P603 D13 — CTS9_RTS9 GTIOC7A/AGTIO4 — —

K1 120 J1 96 H1 65 — P602 BCLK — TXD9/OM_CS1 GTIOC7B/AGTO3 — —

K2 121 J2 97 H2 66 — P601 WR/WR0 — RXD9/OM_SIO2 GTIOC6A/AGTEE3 — —

L1 122 K1 98 J1 67 CACREF/CLKOUT P600 RD — SCK9/OM_SIO4 GTIOC6B/AGTIO3 — —

K4 123 J4 99 — — VCC — — — — — — —

L4 124 G4 100 — — VSS — — — — — — —

L2 125 K2 101 J2 68 — P107 D7 — CTS8_RTS8/OM_SIO3 GTIOC8A/AGTOA0 — —

M1 126 L1 102 K1 69 — P106 D6 — SCK8/SSLB3_A/OM_SIO0 GTIOC8B/AGTOB0 — —

L3 127 K3 103 H3 70 — P105 D5 IRQ0 TXD8/SSLB2_A/OM_SIO5 GTETRGA/GTIOC1A/ — —

AGTO2

M2 128 L2 104 K2 71 — P104 D4 IRQ1 RXD8/SSLB1_A/QIO2/OM_DQS GTETRGB/GTIOC1B/ — —

AGTEE2

N1 129 M1 105 M1 72 — P103 D3 — CTS0_RTS0/SSLB0_A/CTX0/QIO3/ GTOWUP/GTIOC2A/ — —

OM_SIO6 AGTIO2

M3 130 L3 106 L2 73 — P102 D2 — SCK0/RSPCKB_A/CRX0/QIO0/ GTOWLO/GTIOC2B/ ADTRG0 —

OM_SIO1 AGTO0

N2 131 M2 107 M2 74 — P101 D1 IRQ1 TXD0/CTS1_RTS1/MOSIB_A/QIO1/ GTETRGB/GTIOC5A/ — —

OM_SIO7 AGTEE0

P1 132 N1 108 N1 75 — P100 D0 IRQ2 RXD0/SCK1/MISOB_A/QSPCLK/ GTETRGA/GTIOC5B/ — —

OM_SCLK AGTIO0

N3 133 N2 109 — — — P800 D14 — CTS0 AGTOA4 AN125 —

R1 134 N3 110 — — — P801 D15 — CTS8 AGTOB4 AN126 —

P2 135 — — — — — P802 — IRQ3 — — AN127 —

R2 136 — — — — — P803 — IRQ2 — — AN128 —

P3 137 — — — — — P804 — IRQ1 — — — —

N4 138 K4 111 — — VCC — — — — — — —

M4 139 K5 112 — — VSS — — — — — — —

R3 140 M3 113 N2 76 CACREF P500 — — CTS5/USB_VBUSEN/QSPCLK GTIU/AGTOA0 AN116 —

P4 141 M4 114 M4 77 — P501 — IRQ11 TXD5/USB_OVRCURA/QSSL GTIV/AGTOB0 AN117 —

R4 142 L4 115 M3 78 — P502 — IRQ12 CTS6/RXD5/USB_OVRCURB/QIO0 GTIW/AGTOA2 AN118 —

N5 143 L6 116 M5 79 — P503 — — CTS6_RTS6/SCK5/USB_EXICEN/ GTETRGC/AGTOB2 AN119 —

QIO1

P5 144 N4 117 N4 80 — P504 ALE — SCK6/CTS5_RTS5/USB_ID/QIO2 GTETRGD/AGTOA3 AN120 —

P6 145 L5 118 N5 81 — P505 — IRQ14 RXD6/QIO3 AGTOB3 AN121 —

R5 146 N5 119 — — — P506 — IRQ15 TXD6 — AN122 —

N6 147 M5 120 — — — P507 — — SCK6/SCK5 — AN123 —

R6 148 — — — — — P508 — — CTS_RTS5_B — AN124 —

M7 149 K6 121 H7 82 VCC — — — — — — —

N7 150 K7 122 J7 83 VSS — — — — — — —

P7 151 N6 123 N6 84 — P015 — IRQ13 — — AN013/DA1 —

R7 152 M6 124 M6 85 — P014 — — — — AN012/DA0 —

P8 153 M7 125 N7 86 VREFL — — — — — — —

R8 154 N7 126 M7 87 VREFH — — — — — — —

N8 155 L7 127 L6 88 AVCC0 — — — — — — —

N9 156 L8 128 L8 89 AVSS0 — — — — — — —

P9 157 M8 129 N8 90 VREFL0 — — — — — — —

R01DS0366EJ0140 Rev.1.40 Page 27 of 123

Mar 14, 2025
RA6M5 Datasheet 1. Overview

Table 1.16 Pin list (5 of 5)

LQFP176

LQFP144

LQFP100
BGA176

BGA144

BGA100
Power, System, SCI/IIC/SPI/CAN/USBFS/USBHS/
Clock, Debug, I/O QSPI/OSPI/SSIE/SDHI/MMC/
CAC ports Ex. Bus Ex. Interrupt EHTERC(MII,RMII)/CEC GPT/AGT/RTC ADC12/DAC12 CTSU

R9 158 N8 130 M8 91 VREFH0 — — — — — — —

M8 159 — — — — — P010 — IRQ14 — — AN010 —

M9 160 M9 131 — — — P009 — IRQ13-DS — — AN009 —

P10 161 K8 132 M9 92 — P008 — IRQ12-DS — — AN008 —

M6 162 L9 133 M10 93 — P007 — — — — AN007 —

N10 163 N9 134 N9 94 — P006 — IRQ11-DS — — AN006 —

R10 164 L10 135 K12 95 — P005 — IRQ10-DS — — AN005 —

P11 165 M10 136 M11 96 — P004 — IRQ9-DS — — AN004 —

M5 166 N10 137 N10 97 — P003 — — — — AN003 —

R11 167 M11 138 M12 98 — P002 — IRQ8-DS — — AN002/AN102 —

N11 168 L11 139 L12 99 — P001 — IRQ7-DS — — AN001/AN101 —

R12 169 N11 140 N12 100 — P000 — IRQ6-DS — — AN000/AN100 —

M10 170 K9 141 — — VSS — — — — — — —

M11 171 K10 142 — — VCC — — — — — — —

P12 172 — — — — — P806 — IRQ0 — — — —

R13 173 — — — — — P805 — — TXD5_B — — —

N12 174 — — — — — P513 — — RXD5_B — — —

R14 175 N12 143 — — — P512 — IRQ14 TXD4/SCL1_A/CTX1 GTIOC0A — —

P13 176 M12 144 — — — P511 — IRQ15 RXD4/SDA1_A/CRX1 GTIOC0B — —

Note: Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.

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RA6M5 Datasheet 2. Electrical Characteristics

2. Electrical Characteristics
Supported peripheral functions and pins differ from one product name to another.
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
● VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
● 2.7 ≤ VREFH0/VREFH ≤ AVCC0
● VSS = AVSS0 = VREFL0/VREFL = VSS_USB = VSS1_USBHS = VSS2_USBHS = AVSS_USBHS = PVSS_USBHS
=0V
● Ta = Topr

Figure 2.1 shows the timing conditions.

For example, P100

VOH = VCC × 0.7, VOL = VCC × 0.3

VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF

Figure 2.1 Input or output timing measurement conditions

The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings
Parameter Symbol Value Unit

Power supply voltage VCC, VCC_USB*2 –0.3 to +4.0 V

VBATT power supply voltage VBATT –0.3 to +4.0 V

Input voltage (except for 5 V-tolerant ports*1) Vin –0.3 to VCC + 0.3 V

Input voltage (5 V-tolerant ports*1) Vin –0.3 to + VCC + 4.0 (max. 5.8) V

Reference power supply voltage VREFH/VREFH0 –0.3 to VCC + 0.3 V

USBHS power supply voltage VCC_USBHS –0.3 to +4.0 V
USBHS analog power supply voltage AVCC_USBHS –0.3 to +4.0 V
Analog power supply voltage AVCC0*2 –0.3 to +4.0 V

Analog input voltage VAN –0.3 to AVCC0 + 0.3 V

Operating temperature*3 *4 Topr –40 to +105 °C

Storage temperature Tstg –55 to +125 °C

Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, and P708 to P713 are 5 V tolerant.

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RA6M5 Datasheet 2. Electrical Characteristics

Note 2. Connect AVCC0 and VCC_USB to VCC.

Note 3. See section 2.2.1. Tj/Ta Definition.
Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.

Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.

Table 2.2 Recommended operating conditions

Parameter Symbol Value Min Typ Max Unit

Power supply voltages VCC When USB/USBHS is not 2.7 — 3.6 V

used
When USB/USBHS is used 3.0 — 3.6 V
VSS — 0 — V
USB power supply voltages VCC_USB, VCC_USBHS — VCC — V
VSS_USB, AVSS_USBHS, PVSS_USBHS, — 0 — V
VSS1_USBHS, VSS2_USBHS
VBATT power supply voltage VBATT 1.65*2 — 3.6 V

Analog power supply voltages AVCC0*1 — VCC — V

AVSS0 — 0 — V
Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0,
AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/
VREFL0 pins to VSS, respectively.
Note 2. Low CL crystal cannot be used below VBATT = 1.8V.

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics
Parameter Symbol Typ Max Unit Test conditions

Permissible junction temperature Tj — 125 °C High-speed mode

Low-speed mode
105*1 Subosc-speed mode
Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL +
ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. If the part number shows the operation
temperature to 85°C, then Tj max is 105°C, otherwise, 125°C.

2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL (1 of 2)
Parameter Symbol Min Typ Max Unit

Input voltage Peripheral EXTAL (external clock input), WAIT, SPI (except VIH VCC × — — V
(except for function pin RSPCK), OSPI (except ECS) 0.8
Schmitt trigger
input pins) VIL — — VCC × 0.2

D00 to D15 VIH VCC × — —

0.7
VIL — — VCC × 0.3

ETHERC VIH 2.3 — —

VIL — — VCC × 0.2

IIC (SMBus) VIH 2.1 — VCC + 3.6

(max 5.8)
VIL — — 0.8

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.4 I/O VIH, VIL (2 of 2)

Parameter Symbol Min Typ Max Unit

Schmitt trigger Peripheral IIC (except for SMBus) VIH VCC × — VCC + 3.6 V
input voltage function pin 0.7 (max 5.8)
VIL — — VCC × 0.3

ΔVT VCC × — —
0.05
CEC VIH 2.0 — —

VIL — — 0.8

ΔVT — 0.4 —

5 V-tolerant ports*1 *5 VIH VCC × — VCC + 3.6

0.8 (max 5.8)
VIL — — VCC × 0.2

ΔVT VCC × — —
0.05
RTCIC0, When using the When VBATT VIH VBATT × — VBATT + 0.3
RTCIC1, Battery Backup power supply is 0.8
RTCIC2 Function selected
VIL — — VBATT × 0.2

ΔVT VBATT × — —
0.05
When VCC VIH VCC × — Higher
power supply is 0.8 voltage
selected either
VCC + 0.3 V
or
VBATT + 0.3
V
VIL — — VCC × 0.2

ΔVT VCC × — —
0.05
When not using the Battery Backup VIH VCC × — VCC + 0.3
Function 0.8
VIL — — VCC × 0.2

ΔVT VCC × — —
0.05

Other input pins*2 VIH VCC × — —

0.8
VIL — — VCC × 0.2

ΔVT VCC × — —
0.05
Ports 5 V-tolerant ports*3 *5 VIH VCC × — VCC + 3.6 V
0.8 (max 5.8)
VIL — — VCC × 0.2

Other input pins*4 VIH VCC × — —

0.8
VIL — — VCC × 0.2

Note 1. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01 (total
23 pins).
Note 2. All input pins except for the peripheral function pins already described in the table.
Note 3. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01 (total 22 pins).
Note 4. All input pins except for the ports already described in the table.
Note 5. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.

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RA6M5 Datasheet 2. Electrical Characteristics

2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL (1 of 2)
Parameter Symbol Min Typ Max Unit

Permissible output current (average Ports P000 to P010, P014, P015, P201 — IOH — — –2.0 mA
value per pin)
IOL — — 2.0 mA

Ports P205, P206, P407 to P415, P708 to Low drive*1 IOH — — –2.0 mA
P713, PB01 (total 18 pins)
IOL — — 2.0 mA

Middle drive*2 IOH — — –4.0 mA

IOL — — 4.0 mA

High drive*3 IOH — — –20 mA

IOL — — 20 mA

Ports P100 to P107, P208 to P211, P214, Low drive*1 IOH — — –2.0 mA
P600, P601 (total 15 pins)
IOL — — 2.0 mA

Middle drive*2 IOH — — –4.0 mA

IOL — — 4.0 mA

High drive*3 IOH — — –16 mA

IOL — — 16 mA

High speed IOH — — –20 mA

high drive*4
IOL — — 20 mA

Other output pins*5 Low drive*1 IOH — — –2.0 mA

IOL — — 2.0 mA

Middle drive*2 IOH — — –4.0 mA

IOL — — 4.0 mA

High drive*3 IOH — — –16 mA

IOL — — 16 mA

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.5 I/O IOH, IOL (2 of 2)

Parameter Symbol Min Typ Max Unit

Permissible output current (max value Ports P000 to P010, P014, P015, P201 — IOH — — –4.0 mA
per pin)
IOL — — 4.0 mA

Ports P205, P206, P407 to P415, P708 to Low drive*1 IOH — — –4.0 mA
P713, PB01 (total 18 pins)
IOL — — 4.0 mA

Middle drive*2 IOH — — –8.0 mA

IOL — — 8.0 mA

High drive*3 IOH — — –40 mA

IOL — — 40 mA

Ports P100 to P107, P208 to P211, P214, Low drive*1 IOH — — –4.0 mA
P600, P601 (total 15 pins)
IOL — — 4.0 mA

Middle drive*2 IOH — — –8.0 mA

IOL — — 8.0 mA

High drive*3 IOH — — –32 mA

IOL — — 32 mA

High speed IOH — — –40 mA

high drive*4
IOL — — 40 mA

Other output pins*5 Low drive*1 IOH — — –4.0 mA

IOL — — 4.0 mA

Middle drive*2 IOH — — –8.0 mA

IOL — — 8.0 mA

High drive*3 IOH — — –32 mA

IOL — — 32 mA

Permissible output current (max value Maximum of all output pins ΣIOH (max) — — –80 mA
of total of all pins)
ΣIOL (max) — — 80 mA

Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 4. This is the value when high speed high driving ability is selected in the Port Drive Capability in the PmnPFS register. The selected
driving ability is retained in Deep Software Standby mode.
Note 5. Except for P200, which is an input port.

Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table.
The average output current indicates the average value of current measured during 100 µs.

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RA6M5 Datasheet 2. Electrical Characteristics

2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL, and other characteristics
Parameter Symbol Min Typ Max Unit Test conditions

Output voltage IIC VOL — — 0.4 V IOL = 3.0 mA

VOL — — 0.6 IOL = 6.0 mA

IIC*1 VOL — — 0.4 IOL = 15.0 mA ([Link] = 1)

VOL — 0.4 — IOL = 20.0 mA ([Link] = 1)

ETHERC VOH VCC – 0.5 — — IOH = –1.0 mA

VOL — — 0.4 IOL = 1.0 mA

CEC VOL — — 0.6 IOL = 2.1 mA

Ports P205, P206, P407 to P415, VOH VCC – 1.0 — — IOH = –20 mA
P708 to P713, PB01 (total of 18 VCC = 3.3 V
pins)*2
VOL — — 1.0 IOL = 20 mA
VCC = 3.3 V
Other output pins VOH VCC – 0.5 — — IOH = –1.0 mA

VOL — — 0.5 IOL = 1.0 mA

Input leakage current RES |Iin| — — 5.0 µA Vin = 0 V

Vin = 5.5 V

Port P200 — — 1.0 Vin = 0 V

Vin = VCC

Three-state leakage 5 V-tolerant ports |ITSI| — — 5.0 µA Vin = 0 V

current (off state) Vin = 5.5 V

Other ports (except for port P200) — — 1.0 Vin = 0 V

Vin = VCC

Input pull-up MOS current Ports P0 to PB Ip –300 — –10 µA VCC = 2.7 to 3.6 V
Vin = 0 V

Input capacitance Ports P014, P015 Cin — — 16 pF Vbias = 0 V

Vamp = 20 mV
USB_DP and USB_DM — — 12 f = 1 MHz
USBHS_DP, USBHS_DM, and — — 10 Ta = 25°C
ports P400, P401, P511, P512
Other input pins — — 8
Note 1. SCL0_A, SDA0_A, SCL1_A, SDA1_A (total 4 pins).
Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.

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RA6M5 Datasheet 2. Electrical Characteristics

2.2.5 Operating and Standby Current

Table 2.7 Operating and standby current (1 of 2)
Parameter Symbol Min Typ Max Unit Test conditions

Supply High-speed Maximum*2 ICC*3 — — 143 mA ICLK = 200 MHz

current*1 mode PCLKA = 100 MHz
Maximum (without USBHS) — — 130 PCLKB = 50 MHz
— 22 — PCLKC = 50 MHz
CoreMark®*5 *6
PCLKD = 100 MHz
Normal mode All peripheral clocks enabled, — 32 — FCLK = 50 MHz
while (1) code executing from BCLK = 100 MHz
flash*4
All peripheral clocks — 18 —
disabled, while (1) code
executing from flash*5 *6

Sleep mode*5 *6 — 11 55

Increase Data flash P/E — 6 —

during BGO
operation Code flash P/E — 8 —

Low-speed mode*5 *9 — 1.9 — ICLK = 1 MHz

Subosc-speed mode*5 *10 — 1.7 — ICLK = 32.768 kHz

Software Standby mode [Link] = 1 — — 40 —

[Link] = 0 — 2.1 — —
Deep Power supplied to Standby SRAM and USB — 16.9 131 µA —
Software resume detecting unit
Standby
mode Power not Power-on reset circuit low — 11.8 33.7 —
supplied to power function disabled
SRAM or USB
resume Power-on reset circuit low — 4.8 23.8 —
detecting unit power function enabled

Increase when When the low-speed on-chip — 4.5 — —

the RTC and oscillator (LOCO) is in use
AGT are
operating When a crystal oscillator for — 1.2 — —
low clock loads is in use
When a crystal oscillator for — 1.5 — —
standard clock loads is in use
RTC operating while VCC is off (with the When a crystal — 0.9 — VBATT = 1.8 V,
battery backup function, only the RTC oscillator for low VCC = 0 V
and sub-clock oscillator operate) clock loads is in use
— 1.3 — VBATT = 3.3 V,
VCC = 0 V
When a crystal — 1.1 — VBATT = 1.8 V,
oscillator for VCC = 0 V
standard clock
loads is in use — 1.8 — VBATT = 3.3 V,
VCC = 0 V
Inrush current on returning from Deep Inrush current*7 IRUSH — 160 — mA
Software Standby mode
Energy of inrush ERUSH — 1.0 — µC
current*7
Analog During 12-bit A/D conversion AICC — 0.8 1.1 mA —
power
supply Temperature sensor — 0.1 0.2 mA —
current During D/A conversion (per unit) Without AMP output — 0.1 0.2 mA —
With AMP output — 0.6 1.1 mA —
Waiting for A/D, D/A conversion (all units) — 0.9 1.6 mA —

ADC12, DAC12 in standby modes (all units)*8 — 2 8 µA —

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.7 Operating and standby current (2 of 2)

Parameter Symbol Min Typ Max Unit Test conditions

Reference During 12-bit A/D conversion (unit 0) AIREFH0 — 70 120 µA —

power
supply Waiting for 12-bit A/D conversion (unit 0) — 0.07 0.5 µA —
current ADC12 in standby modes (unit 0) — 0.07 0.5 µA —
(VREFH0)
Reference During 12-bit A/D conversion (unit 1) AIREFH — 70 120 µA —
power
supply During D/A conversion (per unit) Without AMP output — 0.1 0.4 mA —
current With AMP output — 0.1 0.4 mA —
(VREFH)
Waiting for 12-bit A/D (unit 1), D/A (all units) conversion — 0.07 0.8 µA —
ADC12 unit 1 in standby modes — 0.07 0.8 µA —
USB Low speed USB ICCUSBLS — 3.5 6.5 mA VCC_USB
operating
current USBHS — 10.5 13.5 mA VCC_USBHS =
AVCC_USBHS
([Link] = 0)
USBHS — 2.8 3.6 mA VCC_USBHS =
AVCC_USBHS
([Link] = 1)
Full speed USB ICCUSBFS — 4.0 10.0 mA VCC_USB
USBHS — 14 22 mA VCC_USBHS =
AVCC_USBHS
([Link] = 0)
USBHS — 6.5 13.0 mA VCC_USBHS =
AVCC_USBHS
([Link] = 1)
High speed USBHS ICCUSBHS — 50 65 mA VCC_USBHS =
AVCC_USBHS
Standby mode (direct power down) USBHS ICCUSBSBY — 0.5 4.5 µA VCC_USBHS =
AVCC_USBHS
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows.
ICC Max. = 0.34 × f + 58 (max. operation in high-speed mode)
ICC Typ. = 0.07 × f + 3.7 (normal operation in high-speed mode, all peripheral clocks disabled)
ICC Typ. = 0.2 × f + 1.7 (low-speed mode)
ICC Max. = 0.035 × f + 58 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).
Note 7. Reference value
Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and
MSTPCRD.MSTPD15 (12-bit A/D converter 1 module stop bit) are in the module-stop state.
Note 9. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).
Note 10. BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.

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 RA6M5 Datasheet 2. Electrical Characteristics

Table 2.8 Coremark and normal mode current

Parameter Symbol Typ Unit Test conditions

Supply Current*1 Coremark ICC 107 µA/MHz ICLK = 200MHz

PCLKA =
Normal mode All peripheral 104 PCLKB =
clocks disabled, PCLKC =
cache on, PCLKD =
while (1) code FCLK =
executing from BCLK =
flash*2 3.125MHz
All peripheral 87
clocks disabled,
cache off,
while (1) code
executing from
flash*2
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Average value of the tested upper-limit samples during product evaluation.
2.19
7.40 100.0
24.53
35.93
52.13
10.0
ICC (mA)

1.0
‐40 ‐20 0 20 40 60 80 100

0.1
Ta (℃)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper‐limit samples during product evaluation.

Figure 2.2 Figure

Temperature dependency
52.2 Temperature in Software
dependency Standby
in Software mode
Standby (reference
mode (referencedata)
data)

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 RA6M5 Datasheet 2. Electrical Characteristics
Average value of the tested upper-limit samples during product evaluation.
15.32
25.72 1000
80.72
127.08
202.35
100
ICC (uA)

10

1
‐40 ‐20 0 20 40 60 80 100
Ta (℃)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper‐limit samples during product evaluation.

Figure 2.3 Figure 52.3 Temperature

Temperature dependency
dependency in Deep
in Deep Software
Software Standby
Standby mode,power
mode, Powersupplied
supplied to
toStandby
standbySRAM
SRAMand USB re
and USB resume detecting unit (reference data)
Average value of the tested upper-limit samples during product evaluation.
13.39
15.42 100
20.98
25.48
33.93
ICC (uA)

10

1
‐40 ‐20 0 20 40 60 80 100
Ta (℃)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper‐limit samples during product evaluation.

Figure 2.4 Figure 52.4 Temperature

Temperature dependency
dependency in Deep
in Deep Software
Software Standby
Standby mode,power
mode, Powernot
not supplied
supplied totoSRAM
SRAMoror
USB resume d
USB
resume detecting unit, power-on reset circuit low power function disabled (reference data)

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 RA6M5 Datasheet 2. Electrical Characteristics
Average value of the tested upper-limit samples during product evaluation.
7.04
8.36 100
13.35
17.67
25.91
ICC (uA)

10

1
‐40 ‐20 0 20 40 60 80 100
Ta (℃)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper‐limit samples during product evaluation.

Figure 2.5 Figure 52.5 Temperature

Temperature dependency
dependency in Deep
in Deep Software
Software Standby
Standby mode,power
mode, Powernot
not supplied
supplied totoSRAM
SRAMoror
USB resume d
USB
resume detecting unit, power-on reset circuit low power function enabled (reference data)

2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.9 Rise and fall gradient characteristics
Test
Parameter Symbol Min Typ Max Unit conditions

VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084 — 20 ms/V —
Voltage monitor 0 reset enabled at startup 0.0084 — — —

SCI/USB boot mode*1 0.0084 — 20 —

VCC falling gradient*2 SfVCC 0.0084 — — ms/V —

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the [Link] bit.
Note 2. This applies when VBATT is used.

Table 2.10 Rising and falling gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7
V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter Symbol Min Typ Max Unit Test conditions

Allowable ripple fr (VCC) — — 10 kHz Figure 2.6

frequency Vr (VCC) ≤ VCC × 0.2

— — 1 MHz Figure 2.6

Vr (VCC) ≤ VCC × 0.08

— — 10 MHz Figure 2.6

Vr (VCC) ≤ VCC × 0.06

Allowable voltage dt/dVCC 1.0 — — ms/V When VCC change

change rising and exceeds VCC ±10%
falling gradient

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RA6M5 Datasheet 2. Electrical Characteristics

1 / fr(VCC)

VCC Vr(VCC)

Figure 2.6 Ripple waveform

2.2.7 Thermal Characteristics

Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”.
Tj is calculated by either of the following equations.
● Tj = Ta + θja × Total power consumption
● Tj = Tt + Ψjt × Total power consumption
– Tj : Junction Temperature (°C)
– Ta : Ambient Temperature (°C)
– Tt : Top Center Case Temperature (°C)
– θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W)
– Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
● Total power consumption = Voltage × (Leakage current + Dynamic current)
● Leakage current of IO = Σ (IOL × VOL) /Voltage + Σ (|IOH| × |VCC – VOH|) /Voltage
● Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage
– Cin: Input capacitance
– Cload: Output capacitance

Regarding θja and Ψjt, see Table 2.11.

Table 2.11 Thermal Resistance
Parameter Package Symbol Value*1 Unit Test conditions

Thermal Resistance 100-pin LQFP (PLQP0100KB-B) θja 35.0 °C/W JESD 51-2 and 51-7
compliant
144-pin LQFP (PLQP0144KA-B) 33.0
176-pin LQFP (PLQP0176KB-C) 32.3
100-pin BGA (PLBG0100KB-A) 36.3 JESD 51-2 and 51-9
compliant
144-pin BGA (PLBG0144KB-A) 36.3
176-pin BGA (PLBG0176GF-A) 35.4
100-pin LQFP (PLQP0100KB-B) Ψjt 0.76 °C/W JESD 51-2 and 51-7
compliant
144-pin LQFP (PLQP0144KA-B) 0.63
176-pin LQFP (PLQP0176KB-C) 0.48
100-pin BGA (PLBG0100KB-A) 0.60 JESD 51-2 and 51-9
compliant
144-pin BGA (PLBG0144KB-A) 0.60
176-pin BGA (PLBG0176GF-A) 0.52

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RA6M5 Datasheet 2. Electrical Characteristics

Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the
board. For details, refer to the JEDEC standards.

[Link] Calculation guide of ICCmax

Table 2.12 shows the power consumption of each unit.
Table 2.12 Power consumption of each unit (1 of 2)
Dynamic current/ MCU Frequency Current Current*1
Leakage current Domain Category Item [MHz] [uA/MHz] [mA]

Leakage current Analog LDO and Leak*2 Ta = 75 °C*3 — — 28.6

Ta = 85 °C*3 — — 34.0

Ta = 95 °C*3 — — 41.1

Ta = 105 °C*3 — — 50.5

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.12 Power consumption of each unit (2 of 2)

Dynamic current/ MCU Frequency Current Current*1
Leakage current Domain Category Item [MHz] [uA/MHz] [mA]

Dynamic current CPU Operation with Coremark 200 90.786 18.16

Flash and SRAM
Peripheral Unit Timer GPT16 (6ch)*4 100 5.101 0.51

GPT32 (4ch)*4 100 3.990 0.40

POEG (4 Groups)*4 50 1.364 0.07

AGT (6ch)*4 50 11.852 0.59

RTC 50 4.872 0.24

WDT 50 0.740 0.04
IWDT 50 0.282 0.01
Communication ETHERC 100 8.307 0.83
interfaces
USBFS 50 9.631 0.48
USBHS 50 23.571 1.18

SCI (10ch)*4 100 12.631 1.26

IIC (2ch)*4 50 4.210 0.21

CAN/CANFD 50 23.346 1.17

(2ch)*4
CEC 100 0.336 0.03

SPI (2ch)*4 100 7.503 0.75

OSPI 50 33.444 1.67

QSPI 100 2.511 0.25
SSIE 50 3.480 0.17
SDHI 50 7.781 0.39
Analog ADC12 (2 Units)*4 100 4.725 0.47

DAC12 (2ch)*4 100 3.630 0.36

TSN 50 0.161 0.01

Human machine CTSU 50 0.761 0.04
interfaces
Event link ELC 50 1.002 0.05
Security SCE9 100 218.100 21.81
Data processing CRC 100 0.569 0.06
DOC 100 0.441 0.04
System CAC 50 0.990 0.05
DMA DMAC 200 4.519 0.90
DTC 200 4.427 0.89
Note 1. The values are guaranteed by design.
Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current.
It is selected according to the temperature of Ta.
Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current.
Note 4. To determine the current consumption per channel or unit, divide Current [mA] by the number of channels, groups or units.
Table 2.13 shows the outline of operation for each unit.

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.13 Outline of operation for each unit (1 of 2)

Peripheral Outline of operation

GPT Operating modes is set to saw-wave PWM mode.

GPT is operating with PCLKD.
POEG Only clear module stop bit.
AGT AGT is operating with PCLKB.
RTC RTC is operating with LOCO.
WDT WDT is operating with PCLKB.
IWDT IWDT is operating with IWDTCLK.
ETHERC Operation modes is set to full-duplex mode.
ETHERC is operating using Reduced Media Independent Interface (RMII).
USBFS Transfer types is set to bulk transfer.
USBFS is operating using Full-speed transfer (12 Mbps).
USBHS Transfer types is set to bulk transfer.
USBHS is operating using High-speed transfer.
SCI SCI is transmitting data in clock synchronous mode.
IIC Communication format is set to I2C-bus format.
IIC is transmitting data in master mode.
CANFD CANFD is transmitting and receiving data in self-test mode 1.
SPI SPI mode is set to SPI operation (4-wire method).
SPI master/slave mode is set to master mode.
SPI is transmitting 8-bit width data.
OSPI Transfer mode is single continuous write mode.
OSPI is issuing memory write command to OctaRAM.
QSPI QSPI is issuing Fast Read Quad I/O Instruction.
SSIE Communication mode is set to Master.
System word length is set to 32 bits.
Data word length is set to 20 bits.
SSIE is transmitting data using I2S format.
CEC CEC operation clock is set to CECCLK.
CEC is transmitting and receiving header block and data block.
SDHI Transfer bus mode is set to 4-bit wide bus mode.
SDHI is issuing CMD24 (single-block write).
ADC12 Resolution is set to 12-bit accuracy.
Data registers is set to A/D-converted value addition mode.
ADC12 is converting the analog input in continuous scan mode.
DAC12 DAC12 is outputting the conversion result while updating the value of data register.
TSN TSN is operating.
CTSU CTSU is operating in self-capacitance single scan mode.
ELC Only clear module stop bit.
SCE9 SCE9 is executing built-in self test.
CRC CRC is generating CRC code using 32-bit CRC32-C polynomial.
DOC DOC is operating in data addition mode.
CAC Measurement target clocks is set to PCLKB.
Measurement reference clocks is set to PCLKB.
CAC is measuring the clock frequency accuracy.
DMAC Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DMAC is transferring data from SRAM0 to SRAM0.

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.13 Outline of operation for each unit (2 of 2)

Peripheral Outline of operation

DTC Bit length of transfer data is set to 32 bits.

Transfer mode is set to block transfer mode.
DTC is transferring data from SRAM0 to SRAM0.

[Link] Example of Tj calculation

Assumption :
● Package 176-pin LQFP : θja = 32.3 °C/W
● Ta = 100 °C
● ICCmax = 70 mA
● VCC = 3.5 V (VCC = AVCC0 = AVCC_USBHS = VCC_USB = VCC_USBHS)
● IOH = 1 mA, VOH = VCC – 0.5 V, 12 Outputs
● IOL = 20 mA, VOL = 1.0 V, 8 Outputs
● IOL = 1 mA, VOL = 0.5 V, 12 Outputs
● Cin = 8 pF, 32 pins, Input frequency = 10 MHz
● Cload = 30 pF, 32 pins, Output frequency = 10 MHz

Leakage current of IO = Σ (VOL × IOL) / Voltage + Σ ((VCC - VOH) × IOH) / Voltage

= (20 mA × 1 V) × 8 / 3.5 V + (1 mA × 0.5 V) × 12 / 3.5 V + ((VCC - (VCC - 0.5 V)) × 1 mA) × 12 / 3.5 V
= 45.7 mA + 1.71 mA + 1.71 mA
= 49.1 mA

Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage

= ((8 pF × 32) × 10 MHz + (30 pF × 32) × 10 MHz) × 3.5 V

= 42.6 mA

Total power consumption = Voltage × (Leakage current + Dynamic current)

= (70 mA × 3.5 V) + (49.1 mA + 42.6 mA) × 3.5 V
= 566 mW (0.566 W)

Tj = Ta + θja × Total power consumption

= 100 °C + 32.3 °C/W × 0.566W
= 118.7 °C

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2.3 AC Characteristics

2.3.1 Frequency
Table 2.14 Operation frequency value in high-speed mode
Parameter Symbol Min Typ Max Unit

Operation frequency System clock (ICLK) f — — 200 MHz

Peripheral module clock (PCLKA) — — 100
Peripheral module clock (PCLKB) — — 50
Peripheral module clock (PCLKC) —*2 — 50

Peripheral module clock (PCLKD) — — 100

Flash interface clock (FCLK) —*1 — 50

External bus clock (BCLK) — — 100

EBCLK pin output — — 50
Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Table 2.15 Operation frequency value in low-speed mode

Parameter Symbol Min Typ Max Unit

Operation frequency System clock (ICLK) f — — 1 MHz

Peripheral module clock (PCLKA) — — 1
Peripheral module clock (PCLKB) — — 1

Peripheral module clock (PCLKC) *2 —*2 — 1

Peripheral module clock (PCLKD) — — 1

Flash interface clock (FCLK)*1 — — 1

External bus clock (BCLK) — — 1

EBCLK pin output — — 1
Note 1. Programming or erasing the flash memory is disabled in low-speed mode.
Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Table 2.16 Operation frequency value in Subosc-speed mode

Parameter Symbol Min Typ Max Unit

Operation frequency System clock (ICLK) f 29.4 — 36.1 kHz

Peripheral module clock (PCLKA) — — 36.1
Peripheral module clock (PCLKB) — — 36.1

Peripheral module clock (PCLKC) *2 — — 36.1

Peripheral module clock (PCLKD) — — 36.1

Flash interface clock (FCLK)*1 29.4 — 36.1

External bus clock (BCLK) — — 36.1

EBCLK pin output — — 36.1
Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.
Note 2. The ADC12 cannot be used.

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2.3.2 Clock Timing

Table 2.17 Clock timing except for sub-clock oscillator
Parameter Symbol Min Typ Max Unit Test conditions

EBCLK pin output cycle time tBcyc 20 — — ns Figure 2.7

EBCLK pin output high pulse width tCH 3.3 — — ns

EBCLK pin output low pulse width tCL 3.3 — — ns

EBCLK pin output rise time tCr — — 5.0 ns

EBCLK pin output fall time tCf — — 5.0 ns

EXTAL external clock input cycle time tEXcyc 41.66 — — ns Figure 2.8

EXTAL external clock input high pulse width tEXH 15.83 — — ns

EXTAL external clock input low pulse width tEXL 15.83 — — ns

EXTAL external clock rise time tEXr — — 5.0 ns

EXTAL external clock fall time tEXf — — 5.0 ns

Main clock oscillator frequency fMAIN 8 — 24 MHz —

Main clock oscillation stabilization wait time (crystal)*1 tMAINOSCWT — — —*1 ms Figure 2.9

LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz —

LOCO clock oscillation stabilization wait time tLOCOWT — — 60.4 µs Figure 2.10

ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz —

MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz —

MOCO clock oscillation stabilization wait time tMOCOWT — — 15.0 µs —

HOCO clock oscillator oscillation Without FLL fHOCO16 15.78 16 16.22 MHz –20 ≤ Ta ≤ 105°C
frequency
fHOCO18 17.75 18 18.25

fHOCO20 19.72 20 20.28

fHOCO16 15.71 16 16.29 –40 ≤ Ta ≤ –20°C

fHOCO18 17.68 18 18.32

fHOCO20 19.64 20 20.36

With FLL fHOCO16 15.960 16 16.040 –40 ≤ Ta ≤ 105°C

Sub-clock frequency accuracy is
fHOCO18 17.955 18 18.045 ±50 ppm.
fHOCO20 19.950 20 20.050

HOCO clock oscillation stabilization wait time*2 tHOCOWT — — 64.7 µs —

HOCO period jitter — — ±85 — ps —

FLL stabilization wait time tFLLWT — — 1.8 ms —

PLL clock frequency fPLL 120 — 200 MHz —

PLL2 clock frequency fPLL2 120 — 240 MHz —

PLL/PLL2 clock oscillation stabilization wait time tPLLWT — — 174.9 µs Figure 2.11

PLL/PLL2 period jitter — — ±100 — ps —

PLL/PLL2 long term jitter — — ±300 — ps Term: 1µs, 10µs
Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
value.
After changing the setting in the [Link] bit to start main clock operation, read the [Link] flag to confirm that
it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed
operation.

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Table 2.18 Clock timing for the sub-clock oscillator

Parameter Symbol Min Typ Max Unit Test conditions

Sub-clock frequency fSUB — 32.768 — kHz —

Sub-clock oscillation stabilization wait time tSUBOSCWT — — —*1 s Figure 2.12

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the [Link] bit to start sub-clock operation, only start using the sub-clock oscillator after the
sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended.

tBcyc
tCH
tCf

EBCLK pin output

tCr
tCL

Figure 2.7 EBCLK output timing

tXcyc
tXH tXL

EXTAL external clock input VCC × 0.5

tXr tXf

Figure 2.8 EXTAL external clock input timing

[Link]

Main clock oscillator output

tMAINOSCWT

Main clock

Figure 2.9 Main clock oscillation start timing

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[Link]

On-chip oscillator output

tLOCOWT

LOCO clock

Figure 2.10 LOCO clock oscillation start timing

[Link]
PLL2CR.PLL2STP

PLL/PLL2 circuit output

tPLLWT
[Link]
OSCSF.PLL2SF

PLL/PLL2 clock

Figure 2.11 PLL/PLL2 clock oscillation start timing

[Link]

Sub-clock oscillator output

tSUBOSCWT
Sub-clock

Figure 2.12 Sub-clock oscillation start timing

2.3.3 Reset Timing

Table 2.19 Reset timing (1 of 2)
Parameter Symbol Min Typ Max Unit Test conditions

RES pulse width Power-on tRESWP 0.7 — — ms Figure 2.13

Deep Software Standby mode tRESWD 0.6 — — ms Figure 2.14

Software Standby mode, Subosc-speed tRESWS 0.3 — — ms

mode
All other tRESW 200 — — µs

Wait time after RES cancellation tRESWT — 37.3 41.2 µs Figure 2.13

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Table 2.19 Reset timing (2 of 2)

Parameter Symbol Min Typ Max Unit Test conditions

Wait time after internal reset cancellation tRESW2 — 324 397.7 µs —

(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error
reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset)

VCC VCCmin

RES

tRESWP
Internal reset signal
(low is valid)

tRESWT

Figure 2.13 RES pin input timing under the condition that VCC exceeds VPOR voltage threshold

tRESWD, tRESWS, tRESW

RES

Internal reset signal

(low is valid)

tRESWT

Figure 2.14 Reset input timing

2.3.4 Wakeup Timing

Table 2.20 Timing of recovery from low power modes (1 of 2)
Parameter Symbol Min Typ Max Unit Test conditions

Recovery time from Crystal resonator System clock source is tSBYMC*13 — 2.1 2.4 ms Figure 2.15
Software Standby connected to main clock main clock oscillator*2 The division ratio of all
mode*1 oscillator oscillators is 1.
System clock source is tSBYPC*13 — 2.2 2.6 ms
PLL with main clock
oscillator*3
External clock input to System clock source is tSBYEX*13 — 45 125 μs
main clock oscillator main clock oscillator*4
System clock source is tSBYPE*13 — 170 255 μs
PLL with main clock
oscillator*5

System clock source is sub-clock oscillator*6 *11 tSBYSC*13 — 0.7 0.8 ms

System clock source is LOCO*7 *11 tSBYLO*13 — 0.7 0.9 ms

System clock source is HOCO clock oscillator*8 tSBYHO*13 — 55 130 µs

System clock source is PLL with HOCO*9 tSBYPH*13 — 175 265 µs

System clock source is MOCO clock oscillator*10 tSBYMO*13 — 35 65 µs

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Table 2.20 Timing of recovery from low power modes (2 of 2)

Parameter Symbol Min Typ Max Unit Test conditions

Recovery time from [Link][1] = 0 and tDSBY — 0.38 0.54 ms Figure 2.16
Deep Software [Link][5:0] = 0x0E
Standby mode
[Link][1] = 1 and tDSBY — 0.55 0.73 ms
[Link][5:0] = 0x19
Wait time after cancellation of Deep Software Standby mode tDSBYWT 56 — 57 tcyc

Recovery time from High-speed mode when system clock source is tSNZ — 35*12 70*12 μs Figure 2.17
Software Standby HOCO (20 MHz)
mode to Snooze
mode High-speed mode when system clock source is tSNZ — 11*12 14*12 μs
MOCO (8 MHz)
Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators
- tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC
module stop))
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the
greatest value of the internal clock division setting is 1.
Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest
value of the internal clock division setting is 4.
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and
the greatest value of the internal clock division setting is 1.
Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest
value of the internal clock division setting is 4.
Note 6. The Sub-clock oscillator frequency is 32.768 kHz and the greatest value of the internal clock division setting is 1.
Note 7. The LOCO frequency is 32.768 kHz and the greatest value of the internal clock division setting is 1.
Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.
Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.
Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.
Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 12. When the [Link] bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs
(maximum).
Note 13. The recovery time can be calculated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the following
value and equation. For n, the greatest value is selected from among the internal clock division settings.

Wakeup time TYP MAX Unit

tSBYOSCWT tSBYSEQ tSBYOSCWT tSBYSEQ

tSBYMC (MSTS[7:0]*32 + 3) / 35 + 18 / fICLK + 4n / fMAIN (MSTS[7:0]*32 + 14 / 62 + 18 / fICLK + 4n / fMAIN µs

0.262 0.236
tSBYPC (MSTS[7:0]*32 + 34) / 35 + 18 / fICLK + 4n / fPLL (MSTS[7:0]*32 + 45) / 62 + 18 / fICLK + 4n / fPLL µs
0.262 0.236
tSBYEX 10 35 + 18 / fICLK + 4n / fEXMAIN 62 62 + 18 / fICLK + 4n / fEXMAIN µs
tSBYPE 135 35 + 18 / fICLK + 4n / fPLL 192 62 + 18 / fICLK + 4n / fPLL µs
tSBYSC 0 35 + 18 / fICLK + 4n / fSUB 0 62 + 18 / fICLK + 4n / fSUB µs
tSBYLO 0 35 + 18 / fICLK + 4n / fLOCO 0 62 + 18 / fICLK + 4n / fLOCO µs
tSBYHO 20 35 + 18 / fICLK + 4n / fHOCO 67 62 + 18 / fICLK + 4n / fHOCO µs
tSBYPH 140 35 + 18 / fICLK + 4n / fPLL 202 62 + 18 / fICLK + 4n / fPLL µs
tSBYMO 0 35 + 18 / fICLK + 4n / fMOCO 0 62 + 18 / fICLK + 4n / fMOCO µs

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RA6M5 Datasheet 2. Electrical Characteristics

Oscillator
(system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock)

ICLK

IRQ
Software Standby mode

tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO

When stabilization of the system clock oscillator is slower

Oscillator
(system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock)

tSBYOSCWT
ICLK

IRQ

Software Standby mode

tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.15 Software Standby mode cancellation timing

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RA6M5 Datasheet 2. Electrical Characteristics

Oscillator

IRQ

Deep Software Standby

reset
(low is valid)

Internal reset
(low is valid)

Deep Software Standby mode

tDSBY
tDSBYWT

Reset exception handling start

Figure 2.16 Deep Software Standby mode cancellation timing

Oscillator

ICLK (except DTC, SRAM)

ICLK (to DTC, SRAM)*1 PCLK

IRQ

Software Standby mode Snooze mode

tSNZ

Note 1. When [Link] bit is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.17 Recovery timing from Software Standby mode to Snooze mode

2.3.5 NMI and IRQ Noise Filter

Table 2.21 NMI and IRQ noise filter
Parameter Symbol Min Typ Max Unit Test conditions

NMI pulse tNMIW 200 — — ns NMI digital filter tPcyc × 2 ≤ 200 ns

width disabled
tPcyc × 2*1 — — tPcyc × 2 > 200 ns

200 — — NMI digital filter tNMICK × 3 ≤ 200 ns

enabled
tNMICK × 3.5*2 — — tNMICK × 3 > 200 ns

IRQ pulse tIRQW 200 — — ns IRQ digital filter tPcyc × 2 ≤ 200 ns

width disabled
tPcyc × 2*1 — — tPcyc × 2 > 200 ns

200 — — IRQ digital filter tIRQCK × 3 ≤ 200 ns

enabled
tIRQCK × 3.5*3 — — tIRQCK × 3 > 200 ns

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RA6M5 Datasheet 2. Electrical Characteristics

Note: 200 ns minimum in Software Standby mode.

Note: If the clock source is switched, add 4 clock cycles of the switched source.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.

NMI

tNMIW

Figure 2.18 NMI interrupt input timing

IRQ

tIRQW

Figure 2.19 IRQ interrupt input timing

2.3.6 Bus Timing

Table 2.22 Bus timing
Condition:
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.
EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

Address delay tAD — 12.5 ns Figure 2.22 to Figure

2.25
Byte control delay tBCD — 12.5 ns

CS delay tCSD — 12.5 ns

ALE delay time tALED — 12.5 ns

RD delay tRSD — 12.5 ns

Read data setup time tRDS 12.5 — ns

Read data hold time tRDH 0 — ns

WR/WRn delay tWRD — 12.5 ns

Write data delay tWDD — 12.5 ns

Write data hold time tWDH 0 — ns

WAIT setup time tWTS 12.5 — ns Figure 2.26

WAIT hold time tWTH 0 — ns

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RA6M5 Datasheet 2. Electrical Characteristics

Address cycle Data cycle

Ta1 Ta1 Tan
TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2

EBCLK

tAD
Address bus

tRDS tRDH
tAD tAD
Address bus/
data bus

tALED tALED
Address latch
(ALE)

tRSD tRSD
Data read
(RD)

tCSD
tCSD
Chip select
(CSn)

Figure 2.20 Address/data multiplexed bus read access timing

Address cycle Data cycle

Ta1 Ta1 Tan
TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 Tn3

EBCLK

tAD
Address bus

tAD tAD tWDD tWDH

Address bus/
data bus

tALED tALED
Address latch
(ALE)

tWRD tWRD
Data write
(WRm)

tCSD
tCSD
Chip select
(CSn)

Figure 2.21 Address/data multiplexed bus write access timing

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RA6M5 Datasheet 2. Electrical Characteristics

CSRWAIT: 2

RDON:1
CSROFF: 2
CSON: 0

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A23 to A00

1-write strobe mode

tAD tAD

A23 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tRSD tRSD

RD (read)

tRDS tRDH

D15 to D00 (read)

Figure 2.22 External bus timing for normal read cycle with bus clock synchronized

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RA6M5 Datasheet 2. Electrical Characteristics

CSWWAIT: 2

WRON: 1
WDON: 1*1
CSWOFF: 2

CSON:0 WDOFF: 1*1

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A23 to A00

1-write strobe mode

tAD tAD

A23 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tWRD tWRD

WR1, WR0, WR (write)

tWDD
tWDH

D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.23 External bus timing for normal write cycle with bus clock synchronized

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RA6M5 Datasheet 2. Electrical Characteristics

CSRWAIT:2 CSPRWAIT:2 CSPRWAIT:2 CSPRWAIT:2

RDON:1 RDON:1 RDON:1 RDON:1 CSROFF:2

CSON:0
TW1 TW2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD tAD

A23 to A00

1-write strobe mode tAD tAD tAD tAD tAD

A23 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode tCSD
tCSD
CS7 to CS0
tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD

RD (Read)

tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH

D15 to D00 (Read)

Figure 2.24 External bus timing for page read cycle with bus clock synchronized

CSWWAIT:2 CSPWWAIT:2 CSPWWAIT:2 CSWOFF:2

WRON:1
WRON:1 WRON:1
WDON:1*1 WDOFF:1*1 WDOFF:1*1 WDOFF:1*1
WDON:1*1 WDON:1*1
CSON:0 TW1 TW2 Tend Tdw1 Tpw1 Tpw2 Tend Tdw1 Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD

A23 to A00

1-write strobe mode tAD tAD tAD tAD

A23 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD
CS7 to CS0

tWRD tWRD tWRD tWRD tWRD tWRD

WR1, WR0, WR (write)

tWDD tWDD tWDD

tWDH tWDH tWDH
D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.25 External bus timing for page write cycle with bus clock synchronized

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CSRWAIT:3
CSWWAIT:3

TW1 TW2 TW3 (Tend) Tend Tn1 Tn2

EBCLK

A23 to A00

CS7 to CS0

RD (read)

WR (write)

External wait

tWTS tWTH tWTS tWTH

WAIT

Figure 2.26 External bus timing for external wait control

2.3.7 I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing
Table 2.23 I/O ports, POEG, GPT, AGT, and ADC12 trigger timing (1 of 2)
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

I/O ports Input data pulse width tPRW 1.5 — tPcyc Figure 2.27

POEG POEG input trigger pulse width tPOEW 3 — tPcyc Figure 2.28

GPT Input capture pulse width Single edge tGTICW 1.5 — tPDcyc Figure 2.29
Dual edge 2.5 —
GTIOCxY output skew Middle drive buffer tGTISK*1 — 4 ns Figure 2.30
(x = 0 to 3, Y = A or B)
High drive buffer — 4
GTIOCxY output skew Middle drive buffer — 4
(x = 4 to 9, Y = A or B)
High drive buffer — 4
GTIOCxY output skew Middle drive buffer — 6
(x = 0 to 9, Y = A or B)
High drive buffer — 6
OPS output skew tGTOSK — 5 ns Figure 2.31
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO

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Table 2.23 I/O ports, POEG, GPT, AGT, and ADC12 trigger timing (2 of 2)
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

AGT AGTIO, AGTEE input cycle tACYC*2 100 — ns Figure 2.32

AGTIO, AGTEE input high width, low width tACKWH, tACKWL 40 — ns

AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 — ns

ADC12 ADC12 trigger input pulse width tTRGW 1.5 — tPcyc Figure 2.33

Note: tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.
Note 2. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Port

tPRW

Figure 2.27 I/O ports input timing

POEG input trigger

tPOEW

Figure 2.28 POEG input trigger timing

Input capture

tGTICW

Figure 2.29 GPT input capture timing

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PCLKD

Output delay

GPT output

tGTISK

Figure 2.30 GPT output delay skew

PCLKD

Output delay

GPT output

tGTOSK

Figure 2.31 GPT output delay skew for OPS

tACYC

tACKWL tACKWH

AGTIO, AGTEE
(input)

tACYC2

AGTIO, AGTO,
AGTOA, AGTOB
(output)

Figure 2.32 AGT input/output timing

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RA6M5 Datasheet 2. Electrical Characteristics

ADTRG0,
ADTRG1
tTRGW

Figure 2.33 ADC12 trigger input timing

2.3.8 CAC Timing

Table 2.24 CAC timing
Parameter Symbol Min Typ Max Unit Test conditions

CAC CACREF input pulse tPBcyc ≤ tcac *1 tCACREF 4.5 × tcac + 3 × tPBcyc — — ns —
width
tPBcyc > tcac*1 5 × tcac + 6.5 × tPBcyc — — ns

Note: tPBcyc: PCLKB cycle.

Note 1. tcac: CAC count clock source cycle.

2.3.9 SCI Timing

Table 2.25 SCI timing (1)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

SCI Input clock cycle Asynchronous tScyc 4 — tPcyc Figure 2.34

Clock synchronous 6 —
Input clock pulse width tSCKW 0.4 0.6 tScyc

Input clock rise time tSCKr — 5 ns

Input clock fall time tSCKf — 5 ns

Output clock cycle Asynchronous tScyc 6 (other than SCI1, — tPcyc

SCI2)
8 (SCI1, SCI2)
Clock synchronous 4 —
Output clock pulse width tSCKW 0.4 0.6 tScyc

Output clock rise time tSCKr — 5 ns

Output clock fall time tSCKf — 5 ns

Transmit data delay Clock synchronous master mode (internal tTXD — 5 ns Figure 2.35
clock)
Clock synchronous slave mode (external tTXD — 25 ns
clock)
Receive data setup time Clock synchronous master mode (internal tRXS 15 — ns
clock)
Clock synchronous slave mode (external tRXS 5 — ns
clock)
Receive data hold time Clock synchronous tRXH 5 — ns

Note: tPcyc: PCLKA cycle.

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tSCKW tSCKr tSCKf

SCKn

tScyc
Note: n = 0 to 9

Figure 2.34 SCK clock input/output timing

SCKn

tTXD

TXDn

tRXS tRXH

RXDn

Note: n = 0 to 9

Figure 2.35 SCI input/output timing in clock synchronous mode

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Table 2.26 SCI timing (2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

Simple SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.36
SCK clock cycle input (slave) 6 65536
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc

SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc

SCK clock rise and fall time tSPCKr, tSPCKf — 5 ns

Data input setup time master tSU 15 — ns Figure 2.37 to Figure

2.40
slave 5 — ns
Data input hold time tH 5 — ns

SS input setup time tLEAD 1 — tSPcyc

SS input hold time tLAG 1 — tSPcyc

Data output delay master tOD — 5 ns

slave — 25 ns
Data output hold time tOH -5 — ns

Data rise and fall time tDr, tDf — 5 ns

SS input rise and fall time tSSLr, tSSLf — 5 ns

Slave access time tSA — 3 × tPcyc + 25 ns Figure 2.40

Slave output release time tREL — 3 × tPcyc + 25 ns

Note: tPcyc: PCLKA cycle.

tSPCKWH tSPCKr tSPCKf

VOH VOH VOH VOH

SCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

SCKn
slave select input VIL VIL VIL
tSPCKWL
tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note: n = 0 to 9

Figure 2.36 SCI simple SPI mode clock timing

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SCKn
CKPOL = 0
output

SCKn
CKPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

Note: n = 0 to 9

Figure 2.37 SCI simple SPI mode timing for master when CKPH = 1

SCKn
CKPOL = 1
output

SCKn
CKPOL = 0
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

Note: n = 0 to 9

Figure 2.38 SCI simple SPI mode timing for master when CKPH = 0

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tTD
SSn
input
tLEAD tLAG

SCKn
CKPOL = 0
input

SCKn
CKPOL = 1
input
tSA tOH tOD tREL

MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

Note: n = 0 to 9

Figure 2.39 SCI simple SPI mode timing for slave when CKPH = 1

tTD

SSn
input
tLEAD tLAG

SCKn
CKPOL = 1
input

SCKn
CKPOL = 0
input
tSA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

Note: n = 0 to 9

Figure 2.40 SCI simple SPI mode timing for slave when CKPH = 0

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.27 SCI timing (3)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

Simple IIC SDA input rise time tSr — 1000 ns Figure 2.41
(Standard mode)
SDA input fall time tSf — 300 ns

SDA input spike pulse removal time tSP 0 4 × tIICcyc ns

Data input setup time tSDAS 250 — ns

Data input hold time tSDAH 0 — ns

SCL, SDA capacitive load Cb *1 — 400 pF

Simple IIC SDA input rise time tSr — 300 ns Figure 2.41
(Fast mode)
SDA input fall time tSf — 300 ns

SDA input spike pulse removal time tSP 0 4 × tIICcyc ns

Data input setup time tSDAS 100 — ns

Data input hold time tSDAH 0 — ns

SCL, SDA capacitive load Cb*1 — 400 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.

VIH
SDAn
VIL

tSr tSf
tSP

SCLn

P*1 S*1 Sr*1 P*1

tSDAH tSDAS

Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA

Note: n = 0 to 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition

Figure 2.41 SCI simple IIC mode timing

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2.3.10 SPI Timing

Table 2.28 SPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

SPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc Figure 2.42
Slave 4 4096
RSPCK clock high Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / — ns
pulse width 2–3
Slave 0.4 0.6 tSPcyc

RSPCK clock low Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / — ns

pulse width 2–3
Slave 0.4 0.6 tSPcyc

RSPCK clock rise and Master tSPCKr, tSPCKf — 5 ns

fall time
Slave — 1 µs
Data input setup time Master tSU 4 — ns Figure 2.43 to Figure
2.48
Slave 5 —
Data input hold time Master tHF 0 — ns
(PCLKA
division ratio
set to 1/2)
Master tH tPcyc —
(PCLKA
division ratio
set to a value
other than
1/2)
Slave tH 20 —

SSL setup time Master tLEAD N × tSPcyc - 10*1 N × tSPcyc + ns

100*1
Slave 4 × tPcyc — ns

SSL hold time Master tLAG N × tSPcyc - 10*2 N × tSPcyc + ns

100*2
Slave 4 × tPcyc — ns

Data output delay Master tOD1 — 6.3 ns

tOD2 6.3

Slave tOD — 20

Data output hold time Master tOH 0 — ns

Slave 0 —
Successive Master tTD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 ns
transmission delay × tPcyc

Slave 4 × tPcyc

MOSI and MISO rise Output tDr, tDf — 5 ns

and fall time
Input — 1 µs
SSL rise and fall time Output tSSLr, tSSLf — 5 ns
Input — 1 µs
Slave access time tSA — 25 ns Figure 2.47 and
Figure 2.48
Slave output release time tREL — 25

Note: tPcyc: PCLKA cycle.

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Note: Must use pins that have a letter appended to their name, for instance _A, _B, to indicate group membership. For the SPI interface,
the AC portion of the electrical characteristics is measured for each group.
Note 1. N is set to an integer from 1 to 8 by the SPCKD register.
Note 2. N is set to an integer from 1 to 8 by the SSLND register.

tSPCKWH tSPCKr tSPCKf

VOH VOH VOH VOH

RSPCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

RSPCKn
slave select input VIL VIL VIL
tSPCKWL
tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Note: n = A or B

Figure 2.42 SPI clock timing

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD2

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

tOD1

Note: n = A or B

Figure 2.43 SPI timing for master when CPHA = 0

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SPI tTD

SSLn0 to
SSLn3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tHF

MISOn MSB IN DATA LSB IN MSB IN

input

tDr, tDf tOH tOD2

MOSIn MSB OUT DATA LSB OUT IDLE MSB OUT

output

tOD1

Note: n = A or B

Figure 2.44 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD2 tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

Note: n = A or B

Figure 2.45 SPI timing for master when CPHA = 1

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SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD2 tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

Note: n = A or B

Figure 2.46 SPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

tTD
SSLn0
input
tLEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
tSA tOH tOD tREL

MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

Note: n = A or B

Figure 2.47 SPI timing for slave when CPHA = 0

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tTD

SSLn0
input
tLEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
tSA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

Note: n = A or B

Figure 2.48 SPI timing for slave when CPHA = 1

2.3.11 QSPI Timing

Table 2.29 QSPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

QSPI QSPCK clock cycle tQScyc 2 48 tPcyc Figure 2.49

QSPCK clock high pulse tQSWH tQScyc × 0.4 — ns

width
QSPCK clock low pulse tQSWL tQScyc × 0.4 — ns
width
Data input setup time tSu 10 — ns Figure 2.50

Data input hold time tIH 0 — ns

QSSL setup time tLEAD (N + 0.5) × tQscyc - 5*1 (N + 0.5) × tQscyc + ns

100*1
QSSL hold time tLAG (N + 0.5) × tQscyc - 5*2 (N + 0.5) × tQscyc + ns
100*2
Data output delay tOD — 4 ns

Data output hold time tOH –3.3 — ns

Successive transmission tTD 1 16 tQScyc

delay
Note: tPcyc: PCLKA cycle.
Note 1. N is set to 0 or 1 in SFMSLD.
Note 2. N is set to 0 or 1 in SFMSHD.

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tQSWH tQSWL

QSPCLK output

tQScyc

Figure 2.49 QSPI clock timing

tTD

QSSL
output
tLEAD tLAG

QSPCLK
output

tSU tH

QIO0-3
MSB IN DATA LSB IN
input

tOH tOD

QIO0-3
MSB OUT DATA LSB OUT IDLE
output

Figure 2.50 Transmit and receive timing

2.3.12 OSPI Timing

Table 2.30 OSPI timing (1 of 2)
(1) Conditions: High speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:
OM_SCLK, OM_DQS, OM_SIO0-7.
(2) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_CS0,
OM_CS1.
Parameter Symbol Min Max Unit Test conditions

OM_SCLK SPI fOCcyc — 50 MHz Figure 2.51

clock
frequency SOPI/DOPI fOCcyc — 100 MHz

OM_SCLK high pulse width tOCwh 0.475 0.525 tOCcyc

OM_SCLK low pulse width tOCwl 0.475 0.525 tOCcyc

OM_SCLK rise time tOCr — 1.8 ns

OM_SCLK fall time tOCf — 1.8 ns

OM_CS SPI/SOPI tOCLEAD 1.5 × tOCcyc – 10.4 2.5 × tOCcyc + 6.9 ns Figure 2.52, Figure
setup time (Minimum register settings) (Maximum register settings) 2.53

DOPI tOCLEAD 1.25 × tOCcyc – 7.9 2.25 × tOCcyc + 4.4 ns Figure 2.54
(Minimum register settings) (Maximum register settings)
OM_CS hold SPI/SOPI tOCLAG 1 × tOCcyc – 6.9 4.5 × tOCcyc + 10.4 ns Figure 2.52, Figure
time (Minimum register settings) (Maximum register settings) 2.53

DOPI read tOCLAG 3.25 × tOCcyc – 4.4 4.25 × tOCcyc + 7.9 ns Figure 2.54
(Minimum register settings) (Maximum register settings)
DOPI write tOCLAG 0.75 × tOCcyc – 4.4 4.25 × tOCcyc + 7.9 ns
(Minimum register settings) (Maximum register settings)

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Table 2.30 OSPI timing (2 of 2)

(1) Conditions: High speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:
OM_SCLK, OM_DQS, OM_SIO0-7.
(2) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_CS0,
OM_CS1.
Parameter Symbol Min Max Unit Test conditions

Continuous transfer delay tOCTD 1 × tOCcyc – 1 8.5 × tOCcyc + 1 ns Figure 2.52, Figure
time (Minimum register settings) (Maximum register settings) 2.53, Figure 2.54

Data input SPI SCLK tSU 10.5 — ns Figure 2.52

setup time base point
Data input tH 0.5 — ns
hold time
Data input SOPI/DOPI tSU -1.3 — ns Figure 2.53, Figure
setup time DQS base 2.54
point*1
Data input tH 3.25 — ns
hold time
Skew of Clock to Data tCKDS — 20 ns
Strobe
Data output SPI/SOPI tOD — 2.65 ns Figure 2.52, Figure
delay time 2.53
Data output tOH -2.65 — ns
hold time
Data output SOPI tBOFF 2.1 — ns Figure 2.53
buffer off
time
Data output DOPI*1 tOD — 3.65 ns Figure 2.54, Figure
delay time 2.55
Data output tOH 1.1 — ns
hold time
Data output DOPI tBOFF 1.1 — ns Figure 2.54
buffer off
time
DQS refresh input setup tDQSS 20 — ns Figure 2.56
time
DQS refresh input hold tDQSH 0.5 × tOCcyc — ns
time
Note: tOCcyc indicates the OM_SCLK cycle.
Note 1. OM_SCLK frequency: 100 MHz

tOCwh tOCwl

OM_SCLK output

tOCcyc

Figure 2.51 Clock Timing

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tOCTD

OM_CS0
OM_CS1
tOCLEAD tOCLAG

OM_SCLK

tOD tOH

OM_SIO0
tSU tH

OM_SIO1

Figure 2.52 SPI Transfer Format Transmission and Reception Timing

tOCTD

OM_CS0
OM_CS1
tOCLEAD tOCLAG

OM_SCLK
tCKDS
OM_DQS
tOH
tOD tBOFF tSU tH

OM_SIO7 to
OM_SIO0

Figure 2.53 SOPI Transfer Format Transmission and Reception Timing

tOCTD

OM_CS0
OM_CS1
tOCLEAD tOCLAG

OM_SCLK
tCKDS

OM_DQS
tOD tOH tBOFF tSU tH
OM_SIO7 to 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
OM_SIO0 A B A B

Figure 2.54 DOPI Transfer Format Transmission and Reception Timing

tOCTD

OM_CS0
OM_CS1
tOCLEAD tOCLAG

OM_SCLK
tOD tOH
OM_DQS
tOD tOH tOD tOH
OM_SIO7 to 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
OM_SIO0 A B A B

Figure 2.55 DOPI Transfer Format Transmission Timing

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OM_CS1
3 × tOCcyc

OM_SCLK
tDQSS tDQSH
OM_DQS

OM_SIO7 to
47:40 39:32 31:24 23:16 15:8 7:0
OM_SIO0

Figure 2.56 DQS Refresh input Timing (OctaRAM™ Read/Write)

2.3.13 IIC Timing

Table 2.31 IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B, SDA2_A, SCL2_A, SDA2_B, SCL2_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Test
Parameter Symbol Min Max Unit conditions

IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 — ns Figure 2.57
(Standard mode,
SMBus) SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns
[Link] = 0
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns

SCL, SDA rise time tSr — 1000 ns

SCL, SDA fall time tSf — 300 ns

SCL, SDA input spike pulse tSP 0 1 (4) × tIICcyc ns

removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 — ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc + — ns
wakeup function is enabled 300
START condition input hold time tSTAH tIICcyc + 300 — ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + 300 — ns
when wakeup function is enabled
Repeated START condition input tSTAS 1000 — ns
setup time
STOP condition input setup time tSTOS 1000 — ns

Data input setup time tSDAS tIICcyc + 50 — ns

Data input hold time tSDAH 0 — ns

SCL, SDA capacitive load Cb — 400 pF

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Table 2.31 IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B, SDA2_A, SCL2_A, SDA2_B, SCL2_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Test
Parameter Symbol Min Max Unit conditions

IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 600 — ns Figure 2.57
(Fast mode)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns

SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns

SCL, SDA rise time tSr 20 × (external pullup 300 ns

voltage/5.5V)*1
SCL, SDA fall time tSf 20 × (external pullup 300 ns
voltage/5.5V)*1
SCL, SDA input spike pulse tSP 0 1 (4) × tIICcyc ns
removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 — ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc + — ns
wakeup function is enabled 300
START condition input hold time tSTAH tIICcyc + 300 — ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + 300 — ns
when wakeup function is enabled
Repeated START condition input tSTAS 300 — ns
setup time
STOP condition input setup time tSTOS 300 —

Data input setup time tSDAS tIICcyc + 50 — ns

Data input hold time tSDAH 0 — ns

SCL, SDA capacitive load Cb — 400 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note: Values in parentheses apply when [Link][1:0] is set to 11b while the digital filter is enabled with [Link] set to 1.
Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. Only supported for SCL0_A, SDA0_A, SCL1_A, and SDA1_A.

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Table 2.32 IIC timing (2)

Setting of the SCL0/1_A, SDA0/1_A pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

IIC SCL input cycle time tSCL 6 (12) × tIICcyc + — ns Figure 2.57
(Fast-mode+) 240
[Link] = 1
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 — ns

SCL input low pulse width tSCLL 3 (6) × tIICcyc + 120 — ns

SCL, SDA rise time tSr — 120 ns

SCL, SDA fall time tSf 20 × (external 120 ns

pullup voltage/
5.5V)
SCL, SDA input spike pulse tSP 0 1 (4) × tIICcyc ns
removal time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 120 — ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × — ns
wakeup function is enabled tPcyc + 120

Start condition input hold time tSTAH tIICcyc + 120 — ns

when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + — ns
when wakeup function is enabled tPcyc + 120

Restart condition input setup time tSTAS 120 — ns

Stop condition input setup time tSTOS 120 — ns

Data input setup time tSDAS tIICcyc + 30 — ns

Data input hold time tSDAH 0 — ns

SCL, SDA capacitive load Cb*1 — 550 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note: Values in parentheses apply when [Link][1:0] is set to 11b while the digital filter is enabled with [Link] set to 1.
Note 1. Cb indicates the total capacity of the bus line.

VIH
SDAn
VIL

tBUF
tSCLH
tSTAH tSTAS tSP tSTOS

SCLn

P*1 S*1 Sr*1 P*1

tSCLL
tSf tSr tSDAS
tSCL
tSDAH

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition
P: Stop condition
Sr: Restart condition

Figure 2.57 I2C bus interface input/output timing

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2.3.14 SSIE Timing

Table 2.33 SSIE timing
(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” , “_B” or “_C” to indicate group membership. For the SSIE
interface, the AC portion of the electrical characteristics is measured for each group.
Target specification
Parameter Symbol Min. Max. Unit Comments

SSIBCK0 Cycle Master tO 80 — ns Figure 2.58

Slave tI 80 — ns

High level/ low Master tHC/tLC 0.35 — tO

level
Slave 0.35 — tI

Rising time/ Master tRC/tFC — 0.15 tO / tI

falling time
Slave — 0.15 tO / tI

SSILRCK0/ Input set up Master tSR 12 — ns Figure 2.60,

SSIFS0, time Figure 2.61
SSITXD0, Slave 12 — ns
SSIRXD0, Input hold time Master tHR 8 — ns
SSIDATA0
Slave 15 — ns
Output delay Master tDTR -10 5 ns
time
Slave 0 20 ns Figure 2.60,
Figure 2.61
Output delay Slave tDTRW — 20 ns Figure 2.62*1
time from
SSILRCK0/
SSIFS0 change
GTIOC2A, Cycle tEXcyc 20 — ns Figure 2.59
AUDIO_CLK
High level/ low level tEXL/tEXH 0.4 0.6 tEXcyc

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.

tHC tRC tFC

SSIBCK0 tLC

tO, tI

Figure 2.58 SSIE clock input/output timing

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tEXcyc

tEXH tEXL

GTIOC2A,
AUDIO_CLK 1/2 VCC
(input)

tEXf tEXr

Figure 2.59 Clock input timing

SSIBCK0
(Input or Output)

SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)

tSR tHR

SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)

tDTR

Figure 2.60 SSIE data transmit and receive timing when [Link] = 0

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SSIBCK0
(Input or Output)

SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)

tSR tHR

SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)

tDTR

Figure 2.61 SSIE data transmit and receive timing when [Link] = 1

SSILRCK0/SSIFS0 (input)

SSITXD0,
SSIDATA0 (output)

tDTRW

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.62 SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.15 SD/MMC Host Interface Timing

Table 2.34 SD/MMC Host Interface signal timing (n = 0, m = 0 to 7)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Clock duty ratio is 50%.
Parameter Symbol Min Max Unit Test conditions

SDnCLK clock cycle TSDCYC 20 — ns Figure 2.63

SDnCLK clock high pulse width TSDWH 6.5 — ns

SDnCLK clock low pulse width TSDWL 6.5 — ns

SDnCLK clock rise time TSDLH — 3 ns

SDnCLK clock fall time TSDHL — 3 ns

SDnCMD/SDnDATm output data delay TSDODLY –7 4 ns

SDnCMD/SDnDATm input data setup TSDIS 4.5 — ns

SDnCMD/SDnDATm input data hold TSDIH 1.5 — ns

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Note: Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC
Host interface, the AC portion of the electrical characteristics is measured for each group.

TSDCYC
TSDWL TSDWH
SDnCLK
(output) TSDLH
TSDHL TSDODLY(max) TSDODLY(min)
SDnCMD/SDnDATm
(output)
TSDIS TSDIH
SDnCMD/SDnDATm
(input)

n = 0, m = 0 to 7

Figure 2.63 SD/MMC Host Interface signal timing

2.3.16 ETHERC Timing

Table 2.35 ETHERC timing (1 of 2)
Conditions: ETHERC (RMII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:
ET0_MDC, ET0_MDIO.
For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
ETHERC (MII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

ETHERC REF50CK0 cycle time Tck 20 — ns Figure 2.64 to

(RMII) Figure 2.67
REF50CK0 frequency, typical 50 MHz — — 50 + 100 ppm MHz
REF50CK0 duty — 35 65 %
REF50CK0 rise/fall time Tckr/ckf 0.5 3.5 ns

RMII_xxxx*1 output delay Tco 2.5 12.0 ns

RMII_xxxx*2 setup time Tsu 3 — ns

RMII_xxxx*2 hold time Thd 1 — ns

RMII_xxxx*1, *2 rise/fall time Tr/Tf 0.5 4 ns

ET0_WOL output delay tWOLd 1 23.5 ns Figure 2.68

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Table 2.35 ETHERC timing (2 of 2)

Conditions: ETHERC (RMII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:
ET0_MDC, ET0_MDIO.
For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
ETHERC (MII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions

ETHERC (MII) ET0_TX_CLK cycle time tTcyc 40 — ns —

ET0_TX_EN output delay tTENd 1 20 ns Figure 2.69

ET0_ETXD0 to ET_ETXD3 output delay tMTDd 1 20 ns

ET0_CRS setup time tCRSs 10 — ns

ET0_CRS hold time tCRSh 10 — ns

ET0_COL setup time tCOLs 10 — ns Figure 2.70

ET0_COL hold time tCOLh 10 — ns

ET0_RX_CLK cycle time tTRcyc 40 — ns —

ET0_RX_DV setup time tRDVs 10 — ns Figure 2.71

ET0_RX_DV hold time tRDVh 10 — ns

ET0_ERXD0 to ET_ERXD3 setup time tMRDs 10 — ns

ET0_ERXD0 to ET_ERXD3 hold time tMRDh 10 — ns

ET0_RX_ER setup time tRERs 10 — ns Figure 2.72

ET0_RX_ER hold time tRESh 10 — ns

ET0_WOL output delay tWOLd 1 23.5 ns Figure 2.73

Note: The following pins must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership.
For the ETHERC (RMII) Host interface, the AC portion of the electrical characteristics is measured for each group. REF50CK0_A,
REF50CK0_B, RMII0_xxxx_A, RMII0_xxxx_B.
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0.
Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER.

Tck

90% Tckr
REF50CK0 50%
Tckf
10%

Tco Tsu Thd

Tr Tf
90%
Change Change
RMII_xxxx *1
50% Change in
in signal Signal Signal in signal
signal level
level level
10%

Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0, RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER

Figure 2.64 REF50CK0 and RMII signal timing

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TCK

REF50CK0

TCO

RMII_TXD_EN

TCO

RMII_TXD1,
Preamble SFD DATA CRC
RMII_TXD0

Figure 2.65 RMII transmission timing

REF50CK0

Tsu Thd

RMII_CRS_DV
Thd
Tsu

RMII_RXD1,
Preamble DATA CRC
RMII_RXD0

SFD
RMII_RX_ER
L

Figure 2.66 RMII reception timing in normal operation

REF50CK0

RMII_CRS_DV

RMII_RXD1,
Preamble SFD DATA xxxx
RMII_RXD0
Thd
Tsu

RMII_RX_ER

Figure 2.67 RMII reception timing when an error occurs

REF50CK0

tWOLd

ET0_WOL

Figure 2.68 WOL output timing for RMII

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ET0_TX_CLK
tTENd

ET0_TX_EN
tMTDd

ET0_ETXD[3:0] Preamble SFD DATA CRC

ET0_TX_ER
tCRSs tCRSh

ET0_CRS

ET0_COL

Figure 2.69 MII transmission timing in normal operation

ET0_TX_CLK

ET0_TX_EN

ET0_ETXD[3:0] Preamble JAM

ET0_TX_ER

ET0_CRS tCOLs tCOLh

ET0_COL

Figure 2.70 MII transmission timing when a conflict occurs

ET0_RX_CLK

tRDVs tRDVh

ET0_RX_DV
tMRDh
tMRDs

ET0_ERXD[3:0] Preamble SFD DATA CRC

ET0_RX_ER

Figure 2.71 MII reception timing in normal operation

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ET0_RX_CLK

ET0_RX_DV

Preamble SFD DATA xxxx

ET0_ERXD[3:0]
tRERh
tRERs

ET0_RX_ER

Figure 2.72 MII reception timing when an error occurs

ET0_RX_CLK

tWOLd

ET0_WOL

Figure 2.73 WOL output timing for MII

2.3.17 CEC Timing

Table 2.36 CEC timing
Parameter Symbol Min Max Unit Test conditions

CEC rise time tcf — 50 µs Cb = 1600pF, Rb =

27kΩ
Cb = 7700pF, Rb =
3kΩ
Note: Cb: Capacitive load of the CEC line.
Rb: External pull-up of the CEC line.

2.4 USB Characteristics

2.4.1 USBFS Timing

Table 2.37 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (1 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —

Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |

Differential common-mode range VCM 0.8 — 2.5 V —

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Table 2.37 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (2 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA

Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.74

Rise time tLR 75 — 300 ns

Fall time tLF 75 — 300 ns

Rise/fall time ratio tLR / tLF 80 — 125 % tLR/ tLF

Pull-up and USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —

pull-down resistance in host controller mode
characteristics

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tLR tLF

Figure 2.74 USB_DP and USB_DM output timing in low-speed mode

Observation
point
USB_DP

200 pF to
600 pF 3.6 V
27 
1.5 K
USB_DM

200 pF to
600 pF

Figure 2.75 Test circuit in low-speed mode

Table 2.38 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics) (1 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —

Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |

Differential common-mode range VCM 0.8 — 2.5 V —

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Table 2.38 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics) (2 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA

Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.76

Rise time tLR 4 — 20 ns

Fall time tLF 4 — 20 ns

Rise/fall time ratio tLR / tLF 90 — 111.11 % tFR/ tFF

Output resistance ZDRV 28 — 44 Ω USBFS: Rs = 27 Ω included

Pull-up and DM pull-up resistance in device controller Rpu 0.900 — 1.575 kΩ During idle state
pull-down mode
characteristics 1.425 — 3.090 kΩ During transmission and
reception
USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —
resistance in host controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tFR tFF

Figure 2.76 USB_DP and USB_DM output timing in full-speed mode

Observation
point
USB_DP

50 pF
27 

USB_DM

50 pF

Figure 2.77 Test circuit in full-speed mode

Table 2.39 USBFS characteristics (USB_DP and USB_DM pin characteristics)

Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Battery Charging D+ sink current IDP_SINK 25 — 175 µA —

Specification
D- sink current IDM_SINK 25 — 175 µA —

DCD source current IDP_SRC 7 — 13 µA —

Data detection voltage VDAT_REF 0.25 — 0.4 V —

D+ source voltage VDP_SRC 0.5 — 0.7 V Output current = 250 µA

D- source voltage VDM_SRC 0.5 — 0.7 V Output current = 250 µA

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2.4.2 USBHS Timing

Table 2.40 USBHS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —

Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |

Differential common-mode range VCM 0.8 — 2.5 V —

Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA

Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.78

Rise time tLR 75 — 300 ns

Fall time tLF 75 — 300 ns

Rise/fall time ratio tLR / tLF 80 — 125 % tLR/ tLF

Pull-up and USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —

pull-down resistance in host controller mode
characteristics

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tLR tLF

Figure 2.78 USB_DP and USB_DM output timing in low-speed mode

Observation
point
USB_DP

200 pF to
600 pF 3.6 V

1.5 K
USB_DM

200 pF to
600 pF

Figure 2.79 Test circuit in low-speed mode

Table 2.41 USBHS full-speed characteristics (USB_DP and USB_DM pin characteristics) (1 of 2)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 — — V —

characteristics
Input low voltage VIL — — 0.8 V —

Differential input sensitivity VDI 0.2 — — V | USB_DP - USB_DM |

Differential common-mode range VCM 0.8 — 2.5 V —

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Table 2.41 USBHS full-speed characteristics (USB_DP and USB_DM pin characteristics) (2 of 2)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Output Output high voltage VOH 2.8 — 3.6 V IOH = –200 µA

characteristics
Output low voltage VOL 0.0 — 0.3 V IOL = 2 mA

Cross-over voltage VCRS 1.3 — 2.0 V Figure 2.80

Rise time tLR 4 — 20 ns

Fall time tLF 4 — 20 ns

Rise/fall time ratio tLR / tLF 90 — 111.11 % tFR/ tFF

Output resistance ZDRV 40.5 — 49.5 Ω Rs Not used

([Link][1:0] =
01b
and PHYSET. HSEB = 0)
Pull-up and DM pull-up resistance in device controller Rpu 0.900 — 1.575 kΩ During idle state
pull-down mode
characteristics 1.425 — 3.090 kΩ During transmission and
reception
USB_DP and USB_DM pull-down Rpd 14.25 — 24.80 kΩ —
resistance in host controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tFR tFF

Figure 2.80 USB_DP and USB_DM output timing in full-speed mode

Observation
point
USB_DP

50 pF

USB_DM

50 pF

Figure 2.81 Test circuit in full-speed mode

Table 2.42 USB High Speed Characteristics (USB_DP and USB_DM Pin Characteristics) (1 of 2)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz
Item Symbol Min Typ Max Unit Test conditions

Input Squelch detect sensitivity VHSSQ 100 — 150 mV Figure 2.82

characteristics
Disconnect detect sensitivity VHSDSC 525 — 625 mV Figure 2.83
Common mode voltage VHSCM -50 — 500 mV —

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Table 2.42 USB High Speed Characteristics (USB_DP and USB_DM Pin Characteristics) (2 of 2)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz
Item Symbol Min Typ Max Unit Test conditions

Output Idle state VHSOI -10 — 10 mV —

characteristics
Output high level voltage VHSOH 360 — 440 mV —
Output low level voltage VHSOL -10 — 10 mV —
Chirp J output voltage (difference) VCHIRPJ 700 — 1100 mV —
Chirp K output voltage (difference) VCHIRPK -900 — -500 mV —
AC Rise time tHSR 500 — — ps —
characteristics
Fall time tHSF 500 — — ps Figure 2.84
Output resistance ZHSDRV 40.5 — 49.5 Ω —

USB_DP, USB_DM VHSSQ

Figure 2.82 USB_DP and USB_DM squelch detect sensitivity (high-speed)

USB_DP, USB_DM VHSDSC

Figure 2.83 USB_DP and USB_DM disconnect detect sensitivity (high-speed)

90% 90%
USB_DP, USB_DM
10% 10%

tHSR tHSF

Figure 2.84 USB_DP and USB_DM output timing (high-speed)

Observation
USB_DP point

45 Ω

USB_DM

45 Ω

Figure 2.85 Test circuit (high-speed)

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Table 2.43 USBHS high-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 12/20/24 MHz
Parameter Symbol Min Typ Max Unit Test conditions

Battery Charging D+ sink current IDP_SINK 25 — 175 µA —

Specification
D- sink current IDM_SINK 25 — 175 µA —

DCD source current IDP_SRC 7 — 13 µA —

Data detection voltage VDAT_REF 0.25 — 0.4 V —

D+ source voltage VDP_SRC 0.5 — 0.7 V Output current = 250 µA

D- source voltage VDM_SRC 0.5 — 0.7 V Output current = 250 µA

2.5 ADC12 Characteristics

Table 2.44 A/D conversion characteristics for unit 0
Conditions: PCLKC = 1 to 50 MHz
Parameter Min Typ Max Unit Test conditions

Frequency 1 — 50 MHz —
Analog input capacitance — — 30 pF —
Quantization error — ±0.5 — LSB —
Resolution — — 12 Bits —
High-precision high-speed Conversion time*1 Permissible signal 0.52 (0.26)*2 — — μs Sampling in 13
channels (operation at PCLKC = source impedance states
(AN000 to AN005) 50 MHz) Max. = 1 kΩ
Max. = 400 Ω 0.40 (0.14)*2 — — μs Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
3.0 V ≤ VREFH0 ≤
AVCC0
Offset error — ±1.0 ±2.5 LSB —
Full-scale error — ±1.0 ±2.5 LSB —
Absolute accuracy — ±2.0 ±4.5 LSB —
DNL differential nonlinearity error — ±0.5 ±1.5 LSB —
INL integral nonlinearity error — ±1.0 ±2.5 LSB —
High-precision normal-speed Conversion time*1 Permissible signal 0.92 (0.66)*2 — — μs Sampling in 33
channels (Operation at PCLKC = source impedance states
(AN006 to AN010, AN012, 50 MHz) Max. = 1 kΩ
AN013)
Offset error — ±1.0 ±2.5 LSB —
Full-scale error — ±1.0 ±2.5 LSB —
Absolute accuracy — ±2.0 ±4.5 LSB —
DNL differential nonlinearity error — ±0.5 ±1.5 LSB —
INL integral nonlinearity error — ±1.0 ±2.5 LSB —
Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D
conversion, values might not fall within the indicated ranges.
The use of pins AN000 to AN010, AN012, AN013 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note: When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
● AN100 and AN000 or AN001 or AN002
● AN101 and AN000 or AN001 or AN002 or AN003
● AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.

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Table 2.45 A/D conversion characteristics for unit 1

Conditions: PCLKC = 1 to 50 MHz
Parameter Min Typ Max Unit Test conditions

Frequency 1 — 50 MHz —
Analog input capacitance — — 30 pF —
Quantization error — ±0.5 — LSB —
Resolution — — 12 Bits —
High-precision high-speed Conversion time*1 Permissible signal 0.52 (0.26)*2 — — μs Sampling in 13
channels (Operation at PCLKC = source impedance states
(AN100 to AN102) 50 MHz) Max. = 1 kΩ
Max. = 400 Ω 0.40 (0.14)*2 — — μs Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
3.0 V ≤ VREFH ≤
AVCC0
Offset error — ±1.0 ±2.5 LSB —
Full-scale error — ±1.0 ±2.5 LSB —
Absolute accuracy — ±2.0 ±4.5 LSB —
DNL differential nonlinearity error — ±0.5 ±1.5 LSB —
INL integral nonlinearity error — ±1.0 ±2.5 LSB —
Normal-precision normal- Conversion time*1 Permissible signal 0.92 (0.66)*2 — — μs Sampling in 33
speed channels (Operation at PCLKC = source impedance states
(AN116 to AN128) 50 MHz) Max. = 1 kΩ

Offset error — ±1.0 ±5.5 LSB —

Full-scale error — ±1.0 ±5.5 LSB —
Absolute accuracy — ±2.0 ±7.5 LSB —
DNL differential nonlinearity error — ±0.5 ±4.5 LSB —
INL integral nonlinearity error — ±1.0 ±5.5 LSB —
Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D
conversion, values might not fall within the indicated ranges.
The use of pins AN100 to AN102 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note: When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
● AN100 and AN000 or AN001 or AN002
● AN101 and AN000 or AN001 or AN002 or AN003
● AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.

Table 2.46 A/D conversion characteristics for interleaving (1 of 2)

Conditions: PCLKC = 1 to 50 MHz
Parameter Min Typ Max Unit Test conditions

Frequency 1 — 50 MHz —
Analog input capacitance — — 30 pF —
Quantization error — ±0.5 — LSB —
Resolution — — 12 Bits —

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Table 2.46 A/D conversion characteristics for interleaving (2 of 2)

Conditions: PCLKC = 1 to 50 MHz
Parameter Min Typ Max Unit Test conditions

High-precision high-speed channels Conversion Max. = 400 Ω 0.20 —

time*1 — µs Sampling in 7 states
(AN000 & AN100, AN001 & AN101, AN002 (operation at PCLKC = 50 VCC = AVCC0 = 3.0 to
& AN102)) MHz) 3.6 V
3.0 V ≤ VREFH0 ≤
AVCC0
Offset error — ±1.0 ±2.5 LSB —
Full-scale error — ±1.0 ±2.5 LSB —
Absolute accuracy — ±2.0 ±4.5 LSB —
DNL differential nonlinearity error — ±0.5 ±3.5 LSB —
INL integral nonlinearity error — ±1.0 ±3.5 LSB —
Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D
conversion, values might not fall within the indicated ranges.
The use of pins AN000 to AN010, AN012, AN013, AN100 to AN102 as digital outputs is not allowed when the 12-Bit A/D converter
is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.

Table 2.47 A/D internal reference voltage characteristics

Parameter Min Typ Max Unit Test conditions

A/D internal reference voltage 1.13 1.18 1.23 V —

Sampling time 4.15 — — µs —

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RA6M5 Datasheet 2. Electrical Characteristics

0xFFF
Full-scale error

Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic

Ideal A/D conversion

characteristic Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

0x000 Offset error

0 Analog input voltage VREFH0
(full-scale)

Figure 2.86 Illustration of ADC12 characteristic terms

Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the
analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D
conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical
A/D conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.

Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

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RA6M5 Datasheet 2. Electrical Characteristics

Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6 DAC12 Characteristics

Table 2.48 D/A conversion characteristics
Parameter Min Typ Max Unit Test conditions

Resolution — — 12 Bits —
Without output amplifier
Absolute accuracy — — ±24 LSB Resistive load 2 MΩ
INL — ±2.0 ±8.0 LSB Resistive load 2 MΩ
DNL — ±1.0 ±2.0 LSB —
Output impedance — 8.5 — kΩ —
Conversion time — — 3 µs Resistive load 2 MΩ, Capacitive load 20 pF
Output voltage range 0 — VREFH V —
With output amplifier
INL — ±2.0 ±4.0 LSB —
DNL — ±1.0 ±2.0 LSB —
Conversion time — — 4.0 µs —
Resistive load 5 — — kΩ —
Capacitive load — — 50 pF —
Output voltage range 0.2 — VREFH – 0.2 V —

2.7 TSN Characteristics

Table 2.49 TSN characteristics
Parameter Symbol Min Typ Max Unit Test conditions

Relative accuracy — — ± 1.0 — °C —

Temperature slope — — 4.0 — mV/°C —
Output voltage (at 25 °C) — — 1.24 — V —
Temperature sensor start time tSTART — — 30 µs —

Sampling time — 4.15 — — µs —

2.8 OSC Stop Detect Characteristics

Table 2.50 Oscillation stop detection circuit characteristics
Parameter Symbol Min Typ Max Unit Test conditions

Detection time tdr — — 1 ms Figure 2.87

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RA6M5 Datasheet 2. Electrical Characteristics

Main clock
tdr
[Link]

MOCO clock

ICLK

Figure 2.87 Oscillation stop detection timing

2.9 POR and LVD Characteristics

Table 2.51 Power-on reset circuit and voltage detection circuit characteristics (1)
Un
Parameter Symbol Min Typ Max it Test conditions

Voltage detection Power-on reset [Link][1:0] = 00b or VPOR 2.5 2.6 2.7 V Figure 2.88
level (POR) 01b.
[Link][1:0] = 11b. 1.8 2.25 2.7
Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.89

Vdet0_2 2.77 2.87 2.97

Vdet0_3 2.70 2.80 2.90

Voltage detection circuit (LVD1) Vdet1_1 2.89 2.99 3.09 Figure 2.90

Vdet1_2 2.82 2.92 3.02

Vdet1_3 2.75 2.85 2.95

Voltage detection circuit (LVD2) Vdet2_1 2.89 2.99 3.09 Figure 2.91

Vdet2_2 2.82 2.92 3.02

Vdet2_3 2.75 2.85 2.95

Internal reset time Power-on reset time tPOR — 4.5 — ms Figure 2.88

LVD0 reset time tLVD0 — 0.51 — Figure 2.89

LVD1 reset time tLVD1 — 0.38 — Figure 2.90

LVD2 reset time tLVD2 — 0.38 — Figure 2.91

Minimum VCC down time*1 tVOFF 200 — — µs Figure 2.88,

Figure 2.89
Response delay tdet — — 200 µs Figure 2.89 to
Figure 2.91
LVD operation stabilization time (after LVD is enabled) td(E-A) — — 10 µs Figure 2.90,
Figure 2.91
Hysteresis width (LVD1 and LVD2) VLVH — 70 — m
V
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for POR and LVD.

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tVOFF

VPOR
VCC

Internal reset signal

(active-low)

tdet tPOR tdet tdet tPOR

Figure 2.88 Power-on reset timing

tVOFF

VCC Vdet0 VLVH

Internal reset signal

(active-low)
tdet tdet tLVD0

Figure 2.89 Voltage detection circuit timing (Vdet0)

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RA6M5 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet1 VLVH

LVCMPCR.LVD1E

Td(E-A)
LVD1
Comparator output

[Link]

[Link]
Internal reset signal
(active-low)
When [Link] = 0

tdet tdet tLVD1

When [Link] = 1

tLVD1

Figure 2.90 Voltage detection circuit timing (Vdet1)

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RA6M5 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet2 VLVH

LVCMPCR.LVD2E

Td(E-A)
LVD2
Comparator output

[Link]

[Link]
Internal reset signal
(active-low)
When [Link] = 0

tdet tdet tLVD2

When [Link] = 1

tLVD2

Figure 2.91 Voltage detection circuit timing (Vdet2)

2.10 VBATT Characteristics

Table 2.52 Battery backup function characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.65 to 3.6 V*1
Parameter Symbol Min Typ Max Unit Test conditions

Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.92

Lower-limit VBATT voltage for power supply VBATTSW 2.70 — — V

switching caused by VCC voltage drop
VCC-off period for starting power supply tVOFFBATT 200 — — µs
switching
VBATT low voltage detection level Vbattldet 1.8 1.9 2.0 V Figure 2.93

Minimum VBATT down time tBATTOFF 200 — — µs

Response delay tBATTdet — — 200 µs

VBATT monitor operation stabilization td(E-A) — — 20 µs

time (after [Link] is
changed to 1)
VBATT current increase (when IVBATTSEL — 140 350 nA
[Link] is 1 compared
to the case that [Link]
is 0)
Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage
level for switching to battery backup (VDETBATT).
Note 1. Low CL crystal cannot be used below VBATT = 1.8 V.

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RA6M5 Datasheet 2. Electrical Characteristics

tVOFFBATT

VDETBATT
VCC

VBATT VBATTSW

Backup power
VCC supply VBATT supply VCC supply
area

Figure 2.92 Battery backup function characteristics

tBATTOFF

Vbattldet
VBATT
td(E-A)

VBATTMON

tBATTdet tBATTdet

VBATTMNSEL

Figure 2.93 Battery backup function characteristics

2.11 CTSU Characteristics

Table 2.53 CTSU characteristics
Parameter Symbol Min Typ Max Unit Test conditions

External capacitance connected to TSCAP pin Ctscap 9 10 11 nF —

TS pin capacitive load Cbase — — 50 pF —

Permissible output high current ΣIoH — — -40 mA When the mutual capacitance
method is applied

2.12 Flash Memory Characteristics

2.12.1 Code Flash Memory Characteristics

Table 2.54 Code flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz
Test
Parameter Symbol Min Typ*6 Max Min Typ*6 Max Unit conditions

Programming time 128-byte tP128 — 0.75 13.2 — 0.34 6.0 ms

NPEC ≤ 100 times
8-KB tP8K — 49 176 — 22 80 ms

32-KB tP32K — 194 704 — 88 320 ms

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RA6M5 Datasheet 2. Electrical Characteristics

Table 2.54 Code flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz
Test
Parameter Symbol Min Typ*6 Max Min Typ*6 Max Unit conditions

Programming time 128-byte tP128 — 0.91 15.8 — 0.41 7.2 ms

NPEC > 100 times
8-KB tP8K — 60 212 — 27 96 ms

32-KB tP32K — 234 848 — 106 384 ms

Erasure time 8-KB tE8K — 78 216 — 43 120 ms

NPEC ≤ 100 times
32-KB tE32K — 283 864 — 157 480 ms

Erasure time 8-KB tE8K — 94 260 — 52 144 ms

NPEC > 100 times
32-KB tE32K — 341 1040 — 189 576 ms

Reprogramming/erasure cycle*4 NPEC 10000*1 — — 10000*1 — — Times

Suspend delay during programming tSPD — — 264 — — 120 µs

Programming resume time tPRT — — 110 — — 50 µs

First suspend delay during erasure in suspend tSESD1 — — 216 — — 120 µs

priority mode
Second suspend delay during erasure in suspend tSESD2 — — 1.7 — — 1.7 ms
priority mode
Suspend delay during erasure in erasure priority tSEED — — 1.7 — — 1.7 ms
mode
First erasing resume time during erasure in suspend tREST1 — — 1.7 — — 1.7 ms
priority mode*5
Second erasing resume time during erasure in tREST2 — — 144 — — 80 µs
suspend priority mode
Erasing resume time during erasure in erasure tREET — — 144 — — 80 µs
priority mode
Forced stop command tFD — — 32 — — 20 µs

Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years

30*2 *3 — — 30*2 *3 — — Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3V and room temperature.

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RA6M5 Datasheet 2. Electrical Characteristics

• Suspension during programming

FACI command Program Suspend Resume

tSPD

[Link] Ready Not Ready Ready

tPRT
Programming pulse Programming Programming

• Suspension during erasure in suspend priority mode

FACI command Erase Suspend Resume Suspend Resume

tSESD1 tSESD2

[Link] Ready Not Ready Ready Not Ready Ready Not Ready

tREST1
tREST2
Erasure pulse Erasing Erasing Erasing

• Suspension during erasure in erasure priority mode

FACI command Erase Suspend Resume

tSEED

[Link] Ready Not Ready Ready Not Ready

tREET
Erasure pulse Erasing Erasing

• Forced Stop

FACI command Forced Stop

tFD

[Link] Not Ready Ready

Figure 2.94 Suspension and forced stop timing for flash memory programming and erasure

2.12.2 Data Flash Memory Characteristics

Table 2.55 Data flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz
Test
Parameter Symbol Min Typ*6 Max Min Typ*6 Max Unit conditions

Programming time 4-byte tDP4 — 0.36 3.8 — 0.16 1.7 ms

8-byte tDP8 — 0.38 4.0 — 0.17 1.8

16-byte tDP16 — 0.42 4.5 — 0.19 2.0

Erasure time 64-byte tDE64 — 3.1 18 — 1.7 10 ms

128-byte tDE128 — 4.7 27 — 2.6 15

256-byte tDE256 — 8.9 50 — 4.9 28

Blank check time 4-byte tDBC4 — — 84 — — 30 µs

Reprogramming/erasure cycle*1 NDPEC 125000*2 — — 125000*2 — — —

Suspend delay during programming 4-byte tDSPD — — 264 — — 120 µs

8-byte — — 264 — — 120
16-byte — — 264 — — 120
Programming resume time tDPRT — — 110 — — 50 µs

First suspend delay during erasure in 64-byte tDSESD1 — — 216 — — 120 µs

suspend priority mode
128-byte — — 216 — — 120
256-byte — — 216 — — 120

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Table 2.55 Data flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz
Test
Parameter Symbol Min Typ*6 Max Min Typ*6 Max Unit conditions

Second suspend delay during erasure in 64-byte tDSESD2 — — 300 — — 300 µs

suspend priority mode
128-byte — — 390 — — 390
256-byte — — 570 — — 570
Suspend delay during erasing in erasure 64-byte tDSEED — — 300 — — 300 µs
priority mode
128-byte — — 390 — — 390
256-byte — — 570 — — 570
First erasing resume time during erasure in suspend tDREST1 — — 300 — — 300 µs
priority mode*5
Second erasing resume time during erasure in tDREST2 — — 126 — — 70 µs
suspend priority mode
Erasing resume time during erasure in erasure tDREET — — 126 — — 70 µs
priority mode
Forced stop command tFD — — 32 — — 20 µs

Data hold time*3 tDRP 10*3 *4 — — 10*3 *4 — — Year

30*3 *4 — — 30*3 *4 — — Ta = +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 4. This result is obtained from reliability testing.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3 V and room temperature.

2.12.3 Option Setting Memory Characteristics

Table 2.56 Option setting memory characteristics
Conditions: Program: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 50 MHz

Parameter Symbol Min Typ*4 Max Min Typ*4 Max Unit Test conditions

Programming time tOP — 83 309 — 45 162 ms

NOPC ≤ 100 times

Programming time tOP — 100 371 — 55 195 ms

NOPC > 100 times

Reprogramming cycle NOPC 20000*1 — — 20000*1 — — Times

Data hold time*2 tDRP 10*2 *3 — — 10*2 *3 — — Years

30*2 *3 — — 30*2 *3 — — Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reference value at VCC = 3.3 V and room temperature.

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RA6M5 Datasheet 2. Electrical Characteristics

2.13 Boundary Scan

Table 2.57 Boundary scan characteristics
Parameter Symbol Min Typ Max Unit Test conditions

TCK clock cycle time tTCKcyc 100 — — ns Figure 2.95

TCK clock high pulse width tTCKH 45 — — ns

TCK clock low pulse width tTCKL 45 — — ns

TCK clock rise time tTCKr — — 5 ns

TCK clock fall time tTCKf — — 5 ns

TMS setup time tTMSS 20 — — ns Figure 2.96

TMS hold time tTMSH 20 — — ns

TDI setup time tTDIS 20 — — ns

TDI hold time tTDIH 20 — — ns

TDO data delay tTDOD — — 40 ns

Boundary scan circuit startup time*1 TBSSTUP tRESWP — — — Figure 2.97

Note 1. Boundary scan does not function until the power-on reset becomes negative.

tTCKcyc
tTCKH

TCK tTCKf

tTCKr
tTCKL

Figure 2.95 Boundary scan TCK timing

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.96 Boundary scan input/output timing

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RA6M5 Datasheet 2. Electrical Characteristics

VCC

RES

tBSSTUP Boundary scan

(= tRESWP) execute

Figure 2.97 Boundary scan circuit startup timing

2.14 Joint Test Action Group (JTAG)

Table 2.58 JTAG
Parameter Symbol Min Typ Max Unit Test conditions

TCK clock cycle time tTCKcyc 40 — — ns Figure 2.98

TCK clock high pulse width tTCKH 15 — — ns

TCK clock low pulse width tTCKL 15 — — ns

TCK clock rise time tTCKr — — 5 ns

TCK clock fall time tTCKf — — 5 ns

TMS setup time tTMSS 8 — — ns Figure 2.99

TMS hold time tTMSH 8 — — ns

TDI setup time tTDIS 8 — — ns

TDI hold time tTDIH 8 — — ns

TDO data delay time tTDOD — — 20 ns

tTCKcyc

tTCKH

TCK tTCKf

tTCKr
tTCKL

Figure 2.98 JTAG TCK timing

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RA6M5 Datasheet 2. Electrical Characteristics

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.99 JTAG input/output timing

2.15 Serial Wire Debug (SWD)

Table 2.59 SWD
Parameter Symbol Min Typ Max Unit Test conditions

SWCLK clock cycle time tSWCKcyc 40 — — ns Figure 2.100

SWCLK clock high pulse width tSWCKH 15 — — ns

SWCLK clock low pulse width tSWCKL 15 — — ns

SWCLK clock rise time tSWCKr — — 5 ns

SWCLK clock fall time tSWCKf — — 5 ns

SWDIO setup time tSWDS 8 — — ns Figure 2.101

SWDIO hold time tSWDH 8 — — ns

SWDIO data delay time tSWDD 2 — 28 ns

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RA6M5 Datasheet 2. Electrical Characteristics

tSWCKcyc

tSWCKH

SWCLK

tSWCKL

Figure 2.100 SWD SWCLK timing

SWCLK

tSWDS tSWDH

SWDIO
(Input)

tSWDD

SWDIO
(Output)

tSWDD

SWDIO
(Output)

tSWDD

SWDIO
(Output)

Figure 2.101 SWD input/output timing

2.16 Embedded Trace Macro Interface (ETM)

Table 2.60 ETM (1 of 2)
Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Typ Max Unit Test conditions

TCLK clock cycle time tTCLKcyc 20 — — ns Figure 2.102

TCLK clock high pulse width tTCLKH 9 — — ns

TCLK clock low pulse width tTCLKL 9 — — ns

TCLK clock rise time tTCLKr — — 1 ns

TCLK clock fall time tTCLKf — — 1 ns

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Table 2.60 ETM (2 of 2)

Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Typ Max Unit Test conditions

TDATA[3:0] output setup time tTRDS 2.5 — — ns Figure 2.103

TDATA[3:0] output hold time tTRDH 1.5 — — ns

tTCLKcyc

tTCLKH

TCLK tTCLKf

tTCLKr
tTCLKL

Figure 2.102 ETM TCLK timing

TCLK

tTRDS tTRDH tTRDS tTRDH

TDATA[3:0]

Figure 2.103 ETM output timing

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RA6M5 Datasheet Appendix 1. Port States in Each Processing Mode

Appendix 1. Port States in Each Processing Mode

After Deep Software Standby
mode is canceled (return to
Software Standby mode startup mode)
Deep Software
Function Pin function Reset OPE = 0 OPE = 1 Standby mode IOKEEP = 0 IOKEEP = 1*1

Mode MD Pull-up Keep-O Keep Hi-Z Keep

JTAG TCK/TMS/TDI Pull-up Keep-O Keep Hi-Z Keep

TDO output Keep-O Keep TDO output Keep

IRQ IRQx Hi-Z Keep-O*2 Keep Hi-Z Keep

IRQx-DS Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

AGT AGTIOn Hi-Z Keep-O*2 Keep Hi-Z Keep

AGTIOn (n=1,3) Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

SCI RXD0 Hi-Z Keep-O*2 Keep Hi-Z Keep

IIC SCLn/SDAn Hi-Z Keep-O*2 Keep Hi-Z Keep

USBFS USB_OVRCURx Hi-Z Keep-O*2 Keep Hi-Z Keep

USB_OVRCURx-DS/ Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

USB_VBUS

USB_DP/USB_DM Hi-Z Keep-O*4 Keep*3 Hi-Z Keep

USBHS USBHS_OVRCURx/ Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

USBHS_VBUS

USBHS_DP/ Hi-Z Keep-O*4 Keep*5 Hi-Z Keep

USBHS_DM

RTC RTCICx Hi-Z Keep-O*2 Keep*3 Hi-Z Keep

RTCOUT Hi-Z [RTCOUT selected] RTCOUT output Keep Hi-Z Keep

CLKOUT CLKOUT Hi-Z [CLKOUT selected] CLKOUT output Keep Hi-Z Keep

DAC DAn Hi-Z [DAn output (DAOE = 1)] D/A output retained Keep Hi-Z Keep

External EBCLK Hi-Z [EBCLK output] H Keep Hi-Z Keep

bus
(CS area) Dx Hi-Z [Dx output] Hi-Z Keep Hi-Z Keep

Ax Hi-Z [Ax output] Hi-Z [Ax output] Keep-O Keep Hi-Z Keep

BCx/CSx/RD/WRx Hi-Z [BCx/CSx/RD/WRx [BCx/CSx/RD/WRx Keep Hi-Z Keep

output] Hi-Z output] H

ALE Hi-Z [ALE output] Hi-Z [ALE output] L Keep Hi-Z Keep

Others — Hi-Z Keep-O Keep Hi-Z Keep

Note: H: High-level
L: Low-level
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins go to high-impedance.
Keep: Pin states are retained during periods in Software Standby mode.
Note 1. Retains the I/O port state until the [Link] bit is cleared to 0.
Note 2. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Note 3. Input is enabled if the pin is specified as the Deep Software Standby canceling source.
Note 4. Input is enabled while the pin is used as an input pin.
Note 5. For host operation, set the [Link] bit to 1 to enable the USBHS_DP and USBHS_DM pull-down resistors. For
device operation, set the [Link] bit to 1 to enable the DP pull-up resistor.

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RA6M5 Datasheet Appendix 2. Package Dimensions

Appendix 2. Package Dimensions

Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.

JEITA Package Code RENESAS Code MASS (Typ.) [g]

P-LFQFP176-24×24-0.50 PLQP0176KB-C 1.8

HD
*1 D

132 89

133 88

HE
E
*2

176 45

1 44 NOTE 4

Index area NOTE)

1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH.
NOTE 3
2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL; SIZE MAY VARY.
F
S Dimension in Millimeters
Reference
Symbol
Min. Nom. Max.

y S *3 b D 23.8 24.0 24.2

e p
x M E 23.8 24.0 24.2
A2 — 1.4 —
HD 25.8 26.0 26.2
HE 25.8 26.0 26.2
0.25

A — — 1.7
A2

c
A

A1 0.05 — 0.15
θ
A1

Lp bp 0.15 0.20 0.27

L1 c 0.09 — 0.20
θ 0° 3.5° 8°
Detail F
e — 0.5 —
x — — 0.08
y — — 0.08
Lp 0.45 0.6 0.75
L1 — 1.0 —

Figure A2.1 LQFP 176-pin

© 2019 Renesas Electronics Corporation. All rights reserved.

R01DS0366EJ0140 Rev.1.40 Page 110 of 123

Mar 14, 2025
 RDK-G-001605 1/1
外形図 Outline drawing
RA6M5 Datasheet (PLBG0176GF-A) ルネサスエレクトロニクス株式会社
Appendix 2. Package Dimensions
Renesas Electronics Corporation

JEITA Package Code RENESAS Code MASS(TYP.)[g]

P-LFBGA176-13x13-0.80 PLBG0176GF-A 0.39

E
A
B

INDEX AREA

４x
aaa C
ccc C
C
A

ddd C
A1

E1
e Reference Dimension in Millimeters
Symbol
Min. Nom. Max.
R D － 13.00 －
P E － 13.00 －
N
E1 － 11.20 －
M
D1 － 11.20 －
L
K A － － 1.40
J A1 0.35 0.40 0.45
D1

H b 0.45 0.50 0.55

G
e － 0.80 －
e

F
aaa － － 0.10
E
D ccc － － 0.10
C ddd － － 0.10
B eee － － 0.15
A
fff － － 0.08
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 n － 176 －

Φb(n×) eee C A B
fff C

Figure A2.2 BGA 176-pin

R01DS0366EJ0140 Rev.1.40 Page 111 of 123

Mar 14, 2025
RA6M5 Datasheet Appendix 2. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP144-20x20-0.50 PLQP0144KA-B — 1.2

HD Unit: mm
*1 D

108 73

109 72

HE
E
144
37 *2

1 36 NOTE 4
NOTE)
Index area
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
NOTE 3
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
F LOCATED WITHIN THE HATCHED AREA.
S 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

*3 Symbol
e bp Min Nom Max
y S M
D 19.9 20.0 20.1
E 19.9 20.0 20.1
A2  1.4 
HD 21.8 22.0 22.2
HE 21.8 22.0 22.2
A   1.7
0.25


A2

A1 0.05 0.15
A

bp 0.17 0.20 0.27



c 0.09  0.20
A1

 0 3.5 8
Lp
L1 e  0.5 
x   0.08
Detail F
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 

© 2016 Renesas Electronics Corporation. All rights reserved.

Figure A2.3 LQFP 144-pin

R01DS0366EJ0140 Rev.1.40 Page 112 of 123

Mar 14, 2025
 RDK-G-00xxxx 1/1
外形図 Outline drawing
Renesasコード PLBG0144KB-A ルネサスエレクトロニクス株式会社
RA6M5 Datasheet Appendix 2. Corporation
Renesas Electronics Package Dimensions

JEITA Package code RENESAS code MASS(TYP.)[g]

P-LFBGA144-7x7-0.50 PLBG0144KB-A 0.13

A
B

INDEX AREA

4X
aaa C

ccc C

C
A

Dimension in Millimeters
Reference
A1

Symbol
Min. Nom. Max.
ddd C D － 7.00 －
E － 7.00 －
D1 － 6.00 －
E1 － 6.00 －
A － － 1.29

A1 0.11 － －
b 0.22 0.27 0.32

e － 0.50 －
aaa － － 0.15

ccc － － 0.10
e

ddd － － 0.08

eee － － 0.15

fff － － 0.05
n x φb Φ eee C A B
Φ fff C n － 144 －

Figure A2.4 BGA 144-pin

R01DS0366EJ0140 Rev.1.40 Page 113 of 123

Mar 14, 2025
RA6M5 Datasheet Appendix 2. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6

HD
Unit: mm
*1 D

75 51

76 50

HE
E
*2
100
26

1 25 NOTE 4
Index area NOTE)
NOTE 3 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
F
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
S
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

y S Symbol
*3 Min Nom Max
e bp
M
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2  1.4 
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
0.25

A   1.7
A2
A

A1 0.05  0.15


bp 0.15 0.20 0.27

A1

c 0.09  0.20
Lp
 0 3.5 8
L1
e  0.5 
Detail F
x   0.08
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 

© 2015 Renesas Electronics Corporation. All rights reserved.

Figure A2.5 LQFP 100-pin

R01DS0366EJ0140 Rev.1.40 Page 114 of 123

Mar 14, 2025
 RDK-G-001859 1/1
外形図 Outline drawing
Renesasコード PLBG0100KB-A ルネサスエレクトロニクス株式会社
RA6M5 Datasheet Appendix 2. Package Dimensions
Renesas Electronics Corporation

JEITA Package code RENESAS code MASS(TYP.)[g]

P-LFBGA100-7x7-0.50 PLBG0100KB-A 0.12

A
B

INDEX AREA

4X
aaa C

TOP VIEW

ccc C

C
A

Dimension in Millimeters
Reference
A1

Symbol
ddd C Min. Nom. Max.

D － 7.00 －
E － 7.00 －
E1
D1 － 6.00 －

N
E1 － 6.00 －
M
A － － 1.30
L
K A1 0.11 － －
J
H b 0.22 0.27 0.32
D1

G
F e － 0.50 －
e

E
D
aaa － － 0.15
C
ccc － － 0.10
B
A ddd － － 0.08
1 2 3 4 5 6 7 8 9 10 11 12 13
eee － － 0.15
n x φb Φ eee C A B
Φ fff C fff － － 0.05

n － 100 －
BOTTOM VIEW

Figure A2.6 BGA 100-pin

R01DS0366EJ0140 Rev.1.40 Page 115 of 123

Mar 14, 2025
RA6M5 Datasheet Appendix 3. I/O Registers

Appendix 3. I/O Registers

This appendix describes I/O register address and access cycles by function.

3.1 Peripheral Base Addresses

This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description,
and the base address of each peripheral.
Table A3.1 Peripheral base address (1 of 3)
Name Description Base address

RMPU Renesas Memory Protection Unit 0x4000_0000

TZF TrustZone Filter 0x4000_0E00
SRAM SRAM Control 0x4000_2000
BUS BUS Control 0x4000_3000
DMAC0 Direct memory access controller 0 0x4000_5000
DMAC1 Direct memory access controller 1 0x4000_5040
DMAC2 Direct memory access controller 2 0x4000_5080
DMAC3 Direct memory access controller 3 0x4000_50C0
DMAC4 Direct memory access controller 4 0x4000_5100
DMAC5 Direct memory access controller 5 0x4000_5140
DMAC6 Direct memory access controller 6 0x4000_5180
DMAC7 Direct memory access controller 7 0x4000_51C0
DMA DMAC Module Activation 0x4000_5200
DTC Data Transfer Controller 0x4000_5400
ICU Interrupt Controller 0x4000_6000
CACHE CACHE 0x4000_7000
CPSCU CPU System Security Control Unit 0x4000_8000
DBG Debug Function 0x400_1B000
FCACHE Flash Cache 0x400_1C100
SYSC System Control 0x4001_E000
PORT0 Port 0 Control Registers 0x4008_0000
PORT1 Port 1 Control Registers 0x4008_0020
PORT2 Port 2 Control Registers 0x4008_0040
PORT3 Port 3 Control Registers 0x4008_0060
PORT4 Port 4 Control Registers 0x4008_0080
PORT5 Port 5 Control Registers 0x4008_00A0
PORT6 Port 6 Control Registers 0x4008_00C0
PORT7 Port 7 Control Registers 0x4008_00E0
PORT8 Port 8 Control Registers 0x4008_0100
PORT9 Port9 Control Registers 0x4008_0120
PORTA Port A Control Registers 0x4008_0140
PORTB Port B Control Registers 0x4008_0160
PFS Pmn Pin Function Control Register 0x4008_0800
ELC Event Link Controller 0x4008_2000
RTC Realtime Clock 0x4008_3000

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RA6M5 Datasheet Appendix 3. I/O Registers

Table A3.1 Peripheral base address (2 of 3)

Name Description Base address

IWDT Independent Watchdog Timer 0x4008_3200

WDT Watchdog Timer 0x4008_3400
CAC Clock Frequency Accuracy Measurement Circuit 0x4008_3600
MSTP Module Stop Control A, B, C, D 0x4008_4000
POEG Port Output Enable Module for GPT 0x4008_A000
USBFS USB 2.0 FS Module 0x4009_0000
SDHI0 SD Host Interface 0 0x4009_2000
SSIE0 Serial Sound Interface Enhanced (SSIE) 0x4009_D000
IIC0 Inter-Integrated Circuit 0 0x4009_F000
IIC0WU Inter-Integrated Circuit 0 Wake-up Unit 0x4009_F014
IIC1 Inter-Integrated Circuit 1 0x4009_F100
IIC2 Inter-Integrated Circuit 2 0x4009_F200
OSPI Octa Serial Peripheral Interface 0x400A_6000
CEC Consumer Electronics Control 0x400A_C000
CANFD CANFD Module Control 0x400B_0000
CTSU Capacitive Touch Sensing Unit 0x400D_0000
PSCU Peripheral Security Control Unit 0x400E_0000
AGT0 Low Power Asynchronous General purpose Timer 0 0x400E_8000
AGT1 Low Power Asynchronous General purpose Timer 1 0x400E_8100
AGT2 Low Power Asynchronous General purpose Timer 2 0x400E_8200
AGT3 Low Power Asynchronous General purpose Timer 3 0x400E_8300
AGT4 Low Power Asynchronous General purpose Timer 4 0x400E_8400
AGT5 Low Power Asynchronous General purpose Timer 5 0x400E_8500
TSN Temperature Sensor 0x400F_3000
CRC CRC Calculator 0x4010_8000
DOC Data Operation Circuit 0x4010_9000
USBHS USB 2.0 High-Speed Module 0x4011_1000
EDMAC0 DMA Controller for the Ethernet Controller Channel 0 0x4011_4000
ETHERC0 Ethernet Controller Channel 0 0x4011_4100
SCI0 Serial Communication Interface 0 0x4011_8000
SCI1 Serial Communication Interface 1 0x4011_8100
SCI2 Serial Communication Interface 2 0x4011_8200
SCI3 Serial Communication Interface 3 0x4011_8300
SCI4 Serial Communication Interface 4 0x4011_8400
SCI5 Serial Communication Interface 5 0x4011_8500
SCI6 Serial Communication Interface 6 0x4011_8600
SCI7 Serial Communication Interface 7 0x4011_8700
SCI8 Serial Communication Interface 8 0x4011_8800
SCI9 Serial Communication Interface 9 0x4011_8900
SPI0 Serial Peripheral Interface 0 0x4011_A000
SPI1 Serial Peripheral Interface 1 0x4011_A100
SCE9 Secure Cryptographic Engine 0x4016_1000

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RA6M5 Datasheet Appendix 3. I/O Registers

Table A3.1 Peripheral base address (3 of 3)

Name Description Base address

GPT320 General PWM 32-Bit Timer 0 0x4016_9000

GPT321 General PWM 32-Bit Timer 1 0x4016_9100
GPT322 General PWM 32-Bit Timer 2 0x4016_9200
GPT323 General PWM 32-Bit Timer 3 0x4016_9300
GPT164 General PWM 16-Bit Timer 4 0x4016_9400
GPT165 General PWM 16-Bit Timer 5 0x4016_9500
GPT166 General PWM 16-Bit Timer 6 0x4016_9600
GPT167 General PWM 16-Bit Timer 7 0x4016_9700
GPT168 General PWM 16-Bit Timer 8 0x4016_9800
GPT169 General PWM 16-Bit Timer 9 0x4016_9900
GPT_OPS Output Phase Switching Controller 0x4016_9A00
ADC120 12bit A/D Converter 0 0x4017_0000
ADC121 12bit A/D Converter 1 0x4017_0200
DAC12 12-bit D/A converter 0x4017_1000
FLAD Data Flash 0x407F_C000
FACI Flash Application Command Interface 0x407F_E000
QSPI Quad-SPI 0x6400_0000
Note: Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral

3.2 Access Cycles

This section provides access cycle information for the I/O registers described in this manual.
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.

Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus masters such as DTC or DMAC.

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RA6M5 Datasheet Appendix 3. I/O Registers

Table A3.2 Access cycles (1 of 3)

Number of access cycles

Address ICLK = PCLK ICLK > PCLK*1

Cycle
Peripherals From To Read Write Read Write Unit Related function

RMPU, TZF, 0x4000_0000 0x4000_6FFF 4 3 4 3 ICLK Renesas Memory

SRAM, BUS, Protection Unit,
DMACn, DMA, TrustZone Filter,
DTC, ICU SRAM Control,
BUS Control, Direct
memory access
controller n, DMAC
Module Activation,
DTC Control Register,
Interrupt Controller

CACHE 0x4000_7000 0x4000_7FFF 3 5 3 5 ICLK CACHE

CPSCU, DBG, 0x4000_8000 0x4001_CFFF 4 3 4 3 ICLK CPU System Security

FCACHE Control Unit, Debug
Function, Flash Cache

SYSC 0x4001_E000 0x4001_E3FF 5 4 5 4 ICLK System Control

SYSC 0x4001_E400 0x4001_E5FF 9 8 5 to 8 5 to 8 PCLKB System Control

PORTn, PFS 0x4008_0000 0x4008_0FFF 5 4 2 to 5 2 to 4 PCLKB Port n Control

Registers, Pmn Pin
Function Control
Register

ELC, RTC, IWDT, 0x4008_2000 0x4008_3FFF 5 4 3 to 5 2 to 4 PCLKB Event Link

WDT, CAC Controller, Realtime
Clock, Independent
Watchdog Timer,
Watchdog
Timer, Clock
Frequency Accuracy
Measurement Circuit

MSTP 0x4008_4000 0x4008_4FFF 5 4 2 to 5 2 to 4 PCLKB Module Stop Control

POEG 0x4008_A000 0x4008_AFFF 5 4 3 to 5 2 to 4 PCLKB Port Output Enable

Module for GPT

USBFS 0x4009_0000 0x4009_03FF 6 5 3 to 6 3 to 5 PCLKB USB 2.0 FS Module

USBFS 0x4009_0400 0x4009_04FF 4 3 1 to 4 1 to 3 PCLKB USB 2.0 FS Module

SDHI0, SSIE0, 0x4009_2000 0x4009_FFFF 5 4 2 to 5 2 to 4 PCLKB SD Host Interface

IICn, IIC0WU 0, Serial Sound
Interface Enhanced,
Inter-Integrated Circuit
n, Inter-Integrated
Circuit 0 Wake-up Unit

OSPI 0x400A_6000 0x400A_6FFF 15 17 12 to 15 15 to 17 PCLKB Octa Serial Peripheral

Interface

CANn 0x400A_8000 0x400A_9FFF 5 4 2 to 5 2 to 4 PCLKB CANn Module

CEC 0x400A_C000 0x400A_CFFF 4 3 1 to 3 1 to 3 PCLKB Consumer Electronics

Control

CANFD 0x400B_0000 0x400C_FFFF 5 4 2 to 5 2 to 4 PCLKB CANFD Module

CTSU 0x400D_0000 0x400D_FFFF 4 3 1 to 4 1 to 3 PCLKB Capacitive Touch

Sensing Unit

PSCU 0x400E_0000 0x400E_0FFF 5 4 2 to 5 2 to 4 PCLKB Peripheral Security

Control Unit

AGTn 0x400E_8000 0x400E_8FFF 7 4 5 to 7 2 to 4 PCLKB Low Power

Asynchronous
General purpose
Timer n

TSN 0x400F_3000 0x400F_3FFF 5 4 2 to 5 2 to 4 PCLKB Temperature Sensor

CRC, DOC 0x4010_8000 0x4010_9FFF 5 4 2 to 5 2 to 4 PCLKA CRC Calculator, Data

Operation Circuit

USBHS 0x4011_1000 0x4011_1FFF (BWAIT+5)*2 (BWAIT+4)*2 (BWAIT+4)*2 (BWAIT+2) to PCLKA USB 2.0 High-Speed
(BWAIT +4)*2 Module

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RA6M5 Datasheet Appendix 3. I/O Registers

Table A3.2 Access cycles (2 of 3)

Number of access cycles

Address ICLK = PCLK ICLK > PCLK*1

Cycle
Peripherals From To Read Write Read Write Unit Related function

EDMAC0 0x4011_4000 0x4011_40FF 6 5 3 to 6 3 to 5 PCLKA DMA Controller for

the Ethernet Controller
Channel 0

ETHERC0 0x4011_4100 0x4011_4FFF 15 14 12 to 15 12 to 14 PCLKA Ethernet Controller

Channel 0

SCIn 0x4011_8000 0x4011_8FFF 5*3 4*3 2 to 5*3 2 to 4*3 PCLKA Serial Communication
Interface n

SPIn 0x4011_A000 0x4011_AFFF 5*4 4*4 2 to 5*4 2 to 4*4 PCLKA Serial Peripheral
Interface n

CANFD ECC 0x4012_F000 0x4012_FFFF 5 4 2 to 4 2 to 4 PCLKA CANFD ECC Module

SCE9 0x4016_1000 0x4016_1FFF 6 4 3 to 6 2 to 4 PCLKA Secure Cryptographic

Engine

GPT32n, GPT16n, 0x4016_9000 0x4016_9FFF 7 4 4 to 7 2 to 4 PCLKA General PWM 32-Bit

GPT_OPS Timer n, General
PWM 16-Bit Timer
n, Output Phase
Switching Controller

ADC12n, DAC12 0x4017_0000 0x4017_2FFF 5 4 2 to 5 2 to 4 PCLKA 12bit A/D Converter n,

12-bit D/A converter

QSPI 0x6400_0000 0x6400_000F 5 14 to *5 2 to 5 14 to *5 PCLKA Quad-SPI

QSPI 0x6400_0010 0x6400_0013 25 to *5 6 to *5 25 to *5 5 to *5 PCLKA Quad-SPI

QSPI 0x6400_0014 0x6400_0037 5 14 to *5 2 to 5 14 to *5 PCLKA Quad-SPI

QSPI 0x6400_0804 0x6400_0807 4 3 1 to 4 1 to 3 PCLKA Quad-SPI

Table A3.2 Access cycles (3 of 3)

Number of access cycles

Address ICLK = FCLK ICLK > FCLK*1

Cycle
Peripherals From To Read Write Read Write Unit Related function

FLAD, FACI 0x407F_C000 0x407F_EFFF 5 4 2 to 5 2 to 4 FCLK Data Flash, Flash

Application Command
Interface

Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the
maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.
Note 2. BWAIT is the number of waits (not cycles) described in the [Link] register.
Note 3. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table A3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in
Table A3.2.
Note 4. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table A3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table A3.2.
Note 5. The access cycles depend on the QSPI bus cycles.

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RA6M5 Datasheet Revision History

Revision History
Revision 1.10 — Mar 31, 2021
First edition, issued

Revision 1.20 — Dec 6, 2022

1. Overview:
● Fixed the ADC12 functional description in Table 1.9 Analog.
● Added Table 1.12 I/O ports to 1.1 Function Outline.
● Merged and fixed Figure 1.2 and Figure 1.3 Part numbering scheme.
● Added the row of PLBG0144KB-A to Table 1.13 and Table 1.14 Product list.
● Merged Table 1.13 and Table 1.14 Product list.
● Added the column of BGA 144-pin to Table 1.14 Function Comparison.
● Fixed the row of ADC12 in Table 1.14 Function Comparison.
● Added the row of I/O ports to Table 1.14 Function Comparison.
● Added Note 2 to Table 1.14 Function Comparison.
● Added Figure 1.6 Pin assignment for BGA 144-pin.
● Added the column of BGA 144-pin to Table 1.16 Pin list.
● Changed from SSISCK0_B to SSIBCK0_B in Table 1.16 Pin list.
2. Electrical Characteristics:
● Fixed Table 2.3 DC characteristics.
● Fixed Table 2.11 Thermal Resistance.
Appendix:
● Added Figure 2.2 BGA 176-pin to Appendix 2. Package Dimensions.
● Fixed Figure 2.4 BGA 144-pin in Appendix 2. Package Dimensions.

Revision 1.30 — Jul 28, 2023

Features:
● Added BGA 144-pin to the list of pins for Ta = -40℃ to +105℃.
● Removed BGA 144-pin from the list of pins for Ta = -40℃ to +85℃.
1. Overview:
● Updated Table1.13 Product list.
● Updated parts number in Table 1.14 Function Comparison.
2. Electrical Characteristics:
● Updated Table 2.11 Thermal Resistance.
● Updated Table 2.34 SD/MMC Host Interface signal timing.

Revision 1.40 —Mar 14, 2025

Features:
● Updated Operating Temperature and Packages.
1. Overview:
● Updated Table 1.13 I/O ports.
● Updated 1.3 Part Numbering.
● Updated Table 1.15 Function Comparison.
● Added Figure 1.8 Pin assignment for BGA 100-pin.
● Updated Table 1.17 Pin list.
2. Electrical Characteristics:
● Updated Table 2.4 I/O VIH, VIL.
● Updated Table 2.6 I/O VOH, VOL, and other characteristics.
● Updated Table 2.11 Thermal Resistance.
● Updated Table 2.31 IIC timing (1).
● Added 2.3.17 CEC Timing.
● Updated 2.4.2 USBHS Timing.
Appendix:
● Updated Appendix 1. Port States in Each Processing Mode.
● Added Figure A2.6 BGA 100-pin.

R01DS0366EJ0140 Rev.1.40 Page 121 of 123

Mar 14, 2025
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
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(Note1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
(Note2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(Rev.5.0-1 October 2020)

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