Computer Organization & Architecture 3-11 Basic Processing Unit In step 3 contents of MDR register are transferred to the instruction register (IR) of the processor. The step 1 through 3 constitute the instruction fetch phase. At the beginning of step 4, the instruction decoder interprets the contents of the IR. This enables the control circuitry to activate the control signals for steps 4 through 7, which constitute the execution phase. In step 4, the contents of register R, are transferred to register MAR by activating Ryoyt and MAR,, signals and Read signal is activated. In step 5, the contents of register R, are transferred to register Y by activating Ryout and Yj, signals. After receiving WMFC signal, the contents of specified location are available in MDR register. In step 6, MDRoyy select Y, Add and Z,,, signals are activated to perform addition of contents of register Y and the contents of MDR. The result is stored in the register Z. In step 7, the contents of register Z are transferred to register R, by activating Z. and Rjj, signals. The End signal causes a new instruction fetch cycle to begin by returning to step 1. 3.2.6 Branch Instruction The branch instruction loads the branch target address in PC so that PC will fetch the next instruction from the branch target address. The branch target address is usually obtained by adding the offset in the contents of PC. The offset is specified within the instruction. The control sequence for unconditional branch instruction is as follows : 1. PC yay MARiy, Read, Yin, SelectC, Add, Zin 2. Zouyy PCigy WMFC 3. MDRout Rin 4. Offset_field_Of_IR, yy SelectY, Add, Zi, 5: Zouy PCigy End The first three steps, step 1 through step 3 are same as in the previous example. They constitute the opcode fetch operation. In step 4 the contents of PC and the offset field of IR register are added and result is saved in register Z by activating corresponding signals. In step 5, the contents of register Z are transferred to PC by activating Zoy, and PC in signals. In case of conditional branch instruction the status of the condition code specified in the instruction is checked. If the status specified within the instruction matches with the current status of condition code the branch target address is loaded in the PC byComputer Organization & Architecture 3-12 Basic Processing Unit adding the offset specified in the instruction to the contents of PC otherwise processor fetches the next instruction in the sequence. 3.3 Multiple Bus Organization So far we have discussed the basic operations of processor using single bus architecture of the processor. However, because of single bus only one data word can be transferred over the bus in a clock cycle. This increases the steps required to complete the execution of the instruction. To reduce the number of steps needed to execute instructions, most commercial processors provide multiple internal paths that enable several transfer to take place in parallel. The Fig. 3.9 shows a three-bus structure of the processor. (See Fig. 3.9 on next page.) Here, three buses are used to connect registers and the ALU of the processor. In the figure all general purpose registers are shown by a single block called register file. The register file shown in Fig. 3.9 has three ports : one input port and two output ports. So it is possible to access data of three register in one clock cycle; the value can be loaded in one register from bus C and data from two register can be accessed to bus A and bus B, respectively. Buses A and B are used to transfer the source operands to the A and B inputs of the ALU. After performing arithmetic or logic operation result is transferred to the destination operand over bus C. To increment the contents of PC after execution of each instruction to fetch the next instruction, separate unit is provided. This unit is known as incrementer. Incrementer increments the contents of PC accordingly to the length of the instruction so that it can point to next instruction in the sequence. The incrementer eliminates the need of multiplexer connected at the A input of ALU. Let us consider the execution of instruction, Add Ry, Ry, Rj. This instruction adds the contents of registers R, and the contents of register R; and stores the result in R,. With three-bus organisation control steps required for execution of instruction Add Ry, R,, Ry are as follows : 1. PCoyy R = B, MAR,, Read, In cPC 2. WMFC 3. MDRgyp IRyy R = B 4. Roout Raourr Add, Rui End In step 1, the contents of PC are transferred to MAR through Bus B to start the Read operation and simultaneously PC is incremented to point the next instruction . In step 2, the processor waits for MFC. In step 3, the instruction code is transferred from MDR to IR register. At the beginning of step 4, the instruction decoder interprets the contents of the IR. This enables the control circuitry to activate the control signals for step 4, which constitute the execution phase.Computer Organization & Architecture 3-13 Basic Processing Unit Bus A Bus B Bus C Memory Memory address lines data lines Fig. 3.9 Three-bus organisation of processorComput Organization & Architecture 3-14 Basic Processing Unit In step 4, two operands from register R, and register R are made available at A and B inputs of ALU through BUS A and BUS B. These two inputs are added by activation of Add signal and result is stored in R, through Bus C. From the above example we can realise that by providing more data paths it is possible to reduce the number of clock cycles needed to execute an instruction, significantly. 3.4 Hardwired Control In the hardwired control, the control units use fixed logic circuits to interpret instructions and generate control signals from them. Fig. 3.10 shows the typical hardwired control unit. Here, the fixed logic circuit block includes combinational circuit that generates the required control outputs for decoding and encoding functions. By separating the decoding and encoding functions, we can draw more detail block diagram for hardwired control unit as shown in the Fig. 3.11. Control step counter | Fixed Logic Circuit Control signals Fig. 3.10 Typical hardwired control unit ‘The instruction decoder decodes the instruction loaded in the IR. If IR is an &-bit register then instruction decoder generates 2°, ic. 256 lines; one for each instruction. According to code in the IR, only one line amongst all output lines of decoder goes high ie., set to 1 and all other lines are set to 0. The step decoder provides a separate signal line for each step, or time slot, in a control sequence. The encoder gets in the input from instruction decoder, step decoder, external inputs and condition codes. It uses all these inputs to generate the individual control signals. After execution of each instruction end signal is generated which resets control step counter and make it ready for generation of control step for next instruction.Computer Organization & Architecture 3-15 Basic Processing Unit Control signals Fig. 3.11 Detail block diagram for hardwired control unit Let us see how the encoder generates signal for single bus processor organisation shown in Fig, 3.12 Yj,, The encoder circuit implements the following logic function to generate Yi. Yi, = Ty +15» ADD + T,- BRANCH +... BRANCH 1 % ADD BRANCH 1s v ‘ADD Tt Ty Yin Zout Generation of the Y,, control signal Generation of the Z.., control signal Fig. 3.12 Fig. 3.13Computer Organization & Architecture 3 - 16 Basic Processing Unit The Y;, signal is asserted during time interval T, for all instructions, during T; for an ADD instruction, during T, for an unconditional BRANCH instruction and so on. As another example, the logic function to generate Zu, signal can given by Zoy, = Tz + Ty: ADD + Ty- BRANCH + ... The Z,yy signal is asserted during time interval T, of all instructions, during T, for an ADD instruction, during T, for an unconditional branch instruction and so on. The Fig. 3.12 and 3.13 show the hardware implementation of logic functions for Yin and Zou, control signals. 3.4.1 Design Methods of Hardwired Control Unit There are four simplified and systematic methods for the design of hardwired controllers. * State-table Method : It is the standard algorithmic approach to sequential circuit design. * Delay-element Method : It is a heuristic method based on the use of clocked delay elements for control signal timing. + Sequence-counter Method : It uses counters for timing purposes. * PLA Method : It uses programmable logic array Let us consider the 2's complement multiplier control circuit for illustration of above designing methods. The hardwired control unit for 2’s complement multiplication is already introduced. Here, the same block diagram (Fig. 3.14) is redrawn with control signals. The operation controlled by each control signal is listed in Table 3.1.Computer Organization & Architecture 3-17 Basic Processing Unit Multipicand Clear A, Q_; and count No — Yes Fig. 3.18 Let us see the implementation of multiplier control unit directly from the flowchart shown in Fig. 3.16 by using the transformation rules. The Fig. 3.19 shows resultant circuit. (See Fig. 3.19 on next page). 3.4.1.3 Sequence Counter Method Fig. 3.20 (a) shows a control unit based on a sequence counter and Fig. 3.20 (b) (Gee Fig. 3.20 (a) and (b) on next page.) shows internal circuit of sequence counter. The sequence counter consists of modulo-k counter (counter which counts from 0 to k-1 states), 1/k decoder and input signals to control the operation of modulo-k counter. The output of the modulo-k counter is connected to the input of 1/k decoder. When the count enable input is connected to a clock source, the counter cycles continually through its k states, and decoder generates k pulse signals () on its output lines. These are called as phase signals. Consecutive pulses of phase signals are separated by one clock period, as shown in the Fig. 3.20 (b). Two additional input lines (begin and end) and a flip-flop are provided for turning the counter on and off. A pulse on the begin line causes the counter to begin cycling through its states by logically connecting the count enable signal to the clock source. A pulse on the end line disconnects the clock and resets the counter.Basic Processing Unit ‘Computer Organization & Architecture 3-23 & Qs BEGIN Fig. 3.19 Multiplier control unit using delay elementsComputer Organization & Architecture 3 - 24 Basic Processing Unit Logic diagram Begin End Modulo-k sequence Clock ‘counter Md % ‘Symbol Fig. 3.20 (b)Computer Organization & Architecture 3-25 Basic Processing Unit The phase signals () are used to activate some set of control lines in each microoperation of the instruction. As instruction changes, microoperations also change. For these changed microoperations, the phase signals must activate some other set of control lines. The set of control lines depend on certain control signals or condition variables applied to the control unit. To activate appropriate set of control lines, it is necessary to connect logic circuit to the modulo-k sequence counter, as shown in Fig. 3.20 (a). To get a clear idea now we design multiplier control unit using sequence counter. Look at the flowchart for 2's complement multiplication, shown in Fig. 3.21. (Gee Fig. 3.21 on next page). It is redrawn with identification of different phases in it. The phase 1 does initial settings. It does this in two steps : Step 1 (A < 0, Q4<0, COUNT < n and B « INBUS) and step 2 (Q < INBUS). Phase 2 is repeated n times and it also has two steps : Step 1 (A © A-Bor AW A+B) and Step 2 (Arithmetic shift A, Q,Q_, and COUNT « COUNT - 1). Phase 3 involves three steps : step 1 Step 1 (OUTBUS « A), step 2 (OUTBUS < Q) and step 3 (Activate END). In each step of particular phase, the corresponding phase signal is used to activate particular set of control lines, as shown in the Fig. 3.22. Begin signal sets the output of F/F, to logic 1, activating the phase 1. In phase 1 counter goes through steps 0 to 2 and activates $,, ¢ and $3 signals in sequence. This action activates control signals as shown in Table 3.3. Phase 1 Phase signel Activated control lines | Enabled AND gates | Cy and Cy 1 Resets F/F, and sets F/Fp Table 3.3 ‘The phase signal resets F/F, and sets F/F, activating phase 2. In phase 2, phase signals to are activated again to activate control signals as shown in Table 3.4. Activated control lines Enabled AND gates In case of subtraction : Cs, Cg, Cy and Cy In case of addition : Cs, Cy and Cy 4 5 Cy and Cy 7 6 Resets F/F2 and sets F/F3, if COUNT = 1 Table 3.4Computer Organization & Architecture 3-26 Basic Processing Unit Ao Step 1 Qr1—o Count —n PHASE 1 Bel Step 2 = INBUS % Step 2 PHASE 2 Step 2 OUTBUS + Q os 3 PHASE 3 Fig. 3.21 Flowchart for 2's complement multiplicationComputer Organization & Architecture 3-27 BEGIN Basic Processing Unit Fig. 3.22 Multiplier control unit using sequence counter The phase 2 is repeated until COUNT = 0. When COUNT signal goes high, phase signal resets F/F, and sets F/F activating phase 3. In phase 3, phase signals are activated again to activate control signals as shown in the table 3.5. [Phase 3 Phase signal Activated control lines Enabled AND gates Table 3.5Computer Organization & Architecture 3-28 Basic Processing Unit 3.4.1.4 PLA Method The control unit designed methods discussed so far are suitable only for small control units due to their size and complexity. In modern computer VLSI technology based circuitry is used for the design of control unit. One such structure, programmable logic array (PLA) is discussed in this section. A PLA consists of an array of AND gates followed by an array of OR gates, as shown in the Fig. 3.23. Programmable connections fy = Ky AHR + HE, f= KX AR Ey + Ky Fig. 3.24 Function structure of a PLA‘Computer Organization & Architecture 3-29 Basic Processing Unit Here, AND and OR arrays both can be programmed to implement combinational logic functions of several variables. Fig. 3.24 illustrates the functional structure of a PLA using a simple example. X;, X; and X are the input signals and f,, f, the combinations of the input signals are available as outputs. Using same logic, we can give instruction code, contents of control step counter, flags and condition codes as an input to the PLA and programmed AND and OR arrays to get outputs as control signals. This is illustrated in Fig. 3.25. Fig. 3.25 Control Unit implementation using PLA 3.4.2 A Complete Processor The Fig. 3.26 shows the block diagram of complete processor. This block diagram consists of instruction unit, integer unit, floating-point unit, instruction cache, data Fig. 3.26 Block diagram of a complete processorComputer Organization & Architecture 3-30 Basic Processing Unit cache, bus interface unit, main memory module and Input/Output module. The instruction unit fetches instructions from an instruction cache or from the main memory when the desired instructions are not available in the cache. The complete processor provides two processing units : Integer unit and floating-point unit. Integer unit to process integer data and floating-point to process floating-point data. These two units gets data from data cache. Use of separate caches for instructions and data is common practice in many processors today. Other processor use a common single cache for both instruction and data. The 80486 processor has 8-kbytes single cache for both instruction and data whereas the Pentium processor has two separate 8 kbytes caches for instruction and data. The processor provides bus interface unit to control the interface of processor to system bus, main memory module and input/output module. 3.5 Microprogrammed Control Every instruction in a processor is implemented by a sequence of one or more sets of concurrent microoperations. Each microoperation is associated with a specific set of control lines which, when activated, causes that microoperation to take place. Since the number of instructions and control lines is often in the hundreds, the complexity of hardwired control unit is very high. Thus, it is costly and difficult to design. Further more, the hardwired control unit is relatively inflexible because it is difficult to change the design, if one wishes to correct design error or modify the instruction set. Microprogramming is a method of control unit design in which the control signal selection and sequencing information is stored in a ROM or RAM called a control memory CM. The control signals to be activated at any time are specified by a microinstruction, which is fetched from CM in much similar way an instruction is fetched from main memory. Each microinstruction also explicitly or implicitly specifies the next microinstruction to be used, thereby providing the necessary information for sequencing. A sequence of one or more microoperations designed to control specific operation, such as addition, multiplication is called a microprogram. The microprograms for all instructions are stored in the control memory. The address where these microinstructions are stored in CM is generated by microprogram sequencer/microprogram controller. The microprogram sequencer generates the address for microinstruction according to the instruction stored in the IR. Fig. 3.27 shows the microprogrammed control unit. It consists of control memory, control address register, micro instruction register and microprogram sequencer.‘Computer Organization & Architecture 3-31 Basic Processing Unit Sequencer (starting and branch address Generator) ] Address ‘Control word (CW) Control signals Control signals to within CPU system bus Fig. 3.27 Microprogrammed contro! unit The components of control unit work together as follows : © The control address register (upc) holds the address of the next microinstruction to be read. Every time a new instruction is loaded into the IR, the output of the block labeled “starting address generator” is loaded into the pe. « When address is available in control address register, the sequencer issues READ command to the control memory. * After issue of READ command, the word from the addressed location is read into the microinstruction register. * The pe is then automatically incremented by the clock, causing successive microinstructions to be read from the control memory.Computer Organization & Architecture 3-32 Basic Processing Unit © The content of the micro instruction register generates control signals which are delivered to various parts of the processor in the correct sequence. Number of times the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action. In such situation, microprogrammed control use conditional branch microinstructions. In additions to the branch address, these instructions specify which of the external inputs, condition codes, or, possibly bits of the instruction register should be checked as a condition for branching to take place. Let us see the implementation of instruction Branch < 0, as shown in Fig. 3.28. When this instruction is loaded into IR, a branch microinstruction transfers control to the corresponding microroutine, which is assumed to start at location 45 in the control memory. This address is the output of the starting address generator block in Fig. 3.27. The microinstruction at location 45 tests the N bit of the condition codes. If this bit is equal to 0, a branch takes place to location 0 to fetch a new machine instruction. Otherwise, the microinstruction at location 46 is executed to put the branch target address into register Z. The microinstruction in location 47 loads this address into the PC. Address Microinstruction 0 PCout, MARin, Read, Yin, SelectC, Add, Zi, 1 Zout) PCin. WMFC 2 MDR op IRip 3 Branch to starting address of appropriate microroutine _ 45 If N=O, then branch to microinstruction 0 46 offset_field_of_IRays, Select’, Add, Zi, 47 Zou PCin, End Fig. 3.28 Microroutine for the instruction branch < 0 To support microprogram branching, the starting address and branch address generator block loads a new address into the ypc when a microinstruction instructs it to do so. To allow implementation of conditional branch, the external inputs, condition codes and the contents of IR are given to the starting address and branch address generator block. Let us see how the ppc is used at different situations. 1. When a new instruction is loaded into the IR, the ppc is loaded with the starting address of the microroutine for that instruction. 2. When a Branch microinstruction is encountered and the branch condition is satisfied, the ypc is loaded with the branch address. 3. When the End instruction is encountered, the upc is loaded with the address of the first control word (CW) in the microroutine for the instruction fetch cycle, ile. address 0.Computer Organization & Architecture 3-33 Basic Processing Unit 4. In any other situation, the upc is incremented every time a new microinstruction is fetched from the control memory. Advantages of Microprogrammed Control * It simplifies the design of control unit. Thus it is both, cheaper and less error prone to implement. * Control functions are implemented in software rather than hardware. © The design process is orderly and systematic. * More flexible, can be changed to accommodate new system specifications or to correct the design errors quickly and cheaply. * Complex function such as floating point arithmetic can be realised efficiently. Disadvantages of Microprogrammed Control * A microprogrammed control unit is somewhat slower than the hardwired control unit, because time is required to access the microinstructions from cM. © The flexibility is achieved at some extra hardware cost due to the control memory and its access circuitry. Besides these disadvantages, the microprogramming is the dominant technique for implementing control units. mm> Example 3.1: Write a combined micro routine that can implement that BGT (Branch if > 0), BPL (Branch if plus), and BR (Branch Unconditionally) instructions. The branch conditions, for the BGT and BPL instructions are Z + (N XOR V) = 0 and N = 0, respectively. What is the total number of micro instructions required ? How many micro instructions are needed if a separate micro routine is used for each machine instruction ? Solution : For bus organisation, we write microroutine for the implementation of BGT (Branch if > 0), BPL (Branch if plus) and BR (Branch unconditionally) instructions as follows. Combine Microroutine Address Microinstruction 0 PC yp, MAR, Read, Yip. SelectC, Add, Zn 1 Zou PCy, WMFC 2 MOR out Rin According to opcode in IR branch to starting address of appropriate microroutine.Computer Organization & Architecture 3 - 36 Basic Processing Unit 3. A source for data transfers must be unique which means that it should not be possible to get the contents of two different registers on to the bus at the same time. 4. Read and write signals to the memory can’t be activated simultaneously. This suggests the possibility of grouping the control signals so that all the signals that are mutually exclusive are placed in the same group. Thus a group can specify one microinstruction at a time. So with this suggestions 39 control signals can be grouped in 8 different groups. No Transfer PCour MDRour Riour Roour Rsour Ryour Sfour Gs, (4 Bits) : ALU Functions | G, (2 Bits) : RDWR Control Signals 0000 ADD 00 No Action 0001 SUB 01 Read 16 ALU Functions 10 Write 1111 XOR Gg (1 Bit) : A Register Gy (1 Bit) : Carry 0 - Carry in to ALU = 0 1- Cary in to ALU = 1 Gg (1 bit) : OperationComputer Organization & Architecture 3-37 Basic Processing Unit The total number of grouping bits are 18. Therefore, we minimized 39 bits microinstruction to 18 bit microinstruction. Grouping of control signals result in relatively small increase in the required hardware as it becomes necessary to use decoding circuits to translate the bit patterns of each group into actual control signals. Since the number of bits required is less for microinstruction, less space is required for microinstructions for the instruction. 3.5.1.2 Techniques of Grouping of Control Signals The grouping of control signals can be done either by using technique called vertical organisation or by using technique called horizontal organisation. Highly encoded scheme that use compact codes to specify only a small number of control functions in each microinstruction are referred to as a vertical organisation. On the other hand, the minimally encoded scheme, in which resources can be controlled with a single instruction, is called a horizontal organisation. The Table 3.6 shows the comparison between horizontal and vertical organisation. |_ Short formats. Ability to express a high degree | Limited ability to express parallel of parallelism. microoperations. 3. Little encoding of the control | Considerable encoding of the information. control information. Useful when higher operating | Slower operating speeds. speed is desired. Table 3.6 The advantages and disadvantages of horizontal and vertical organisations can be summarized as follows : 1. The horizontal organisation approach is suitable when operating speed of computer is a critical factor and where the machine structure allows parallel usage of a number of resources. 2. Vertical approach results in slower operations speed but less bits are required in the microinstruction. 3. In vertical approach the significant factor is the reduced requirement for the parallel hardware required to handle the execution of microinstructions.Computer Organization & Architecture 3-38 Basic Processing Unit 3.5.2 Microinstruction Sequencing The task of microprogram sequencing is done by microprogram sequencer. There are two important factors that must be considered while designing the microprogram sequencer : * The size of the microinstruction and © The address generation time The size of the microinstruction should be minimum so that the size of control memory required to store microinstructions is also less. This reduces the cost of control memory. With less address generation time, microinstructions can be executed in less time, resulting better throughout. During execution of a microprogram, the address of the next microinstruction to be executed has three sources : Determined by instruction register Next sequential Address «¢ Branch Out of these three address sources, first occurs only once per instruction cycle. The second source is most commonly used. However, if we store separate microinstructions for each machine instruction, there will be large number of microinstructions. As a result, large space in CM is required to store these microinstructions. We know that, machine instructions involve several addressing modes and there can be many instructions and addressing mode combinations. A separate microinstructions for each of these combinations would produce considerable duplication of common microinstructions. We want to organize the microprograms such that they share as many microinstructions as possible. This requires many branch microinstructions, both unconditional and conditional to transfer control amongs the various microinstructions. Thus it is important to design compact, time-efficient techniques for microinstruction branching. Let us see how microinstructions can be shared using microinstruction branching. Consider instruction ADD R,;<, Rast» The instruction adds the source operand to the contents of register Ry, and places the sum in Rys, the destination register. Let us assume that the source operand can be specified in the following addressing modes : Indexed, autoincrement, autodecrement, register indirect and register direct. We now use this instruction in conjunction with the CPU structure shown in Fig. 3.30 to demonstrate a possible microprogrammed implementation. Fig. 3.31 shows a flowchart of a microprogram for the ADD R,,., Rag instruction. Each box in the flowchart corresponds to a microinstruction that controls the transfers and operations indicated within the box. The microinstruction is located at the address indicated by the numberComputer Organization & Architecture 3 - 39 Basic Processing Unit CPU bus Fig. 3.30 Single bus organisation of processor above the upper right-hand corner of the box. During the execution of the microinstruction, the branching takes place at point A. The branching address is determined by the addressing mode used in the instruction. At point B, it is necessary to choose between actions required by direct and indirect addressing modes. If the indirect mode is specified in the instruction, then the microinstruction in location 170 is performed to fetch the operand from the memory. If the direct mode is specified, this fetch must be bypassed by branching immediately to location 171. The remaining microoperations required to complete execution of instruction are same and hence shared by the instructions having operand with different addressing modes. From the above discussion we can say that branching allows. sharing of icroi ions for different microprograms and it reduces the size of control memory.Computer Organization & Architecture 3-40 Basic Processing Unit Indexed Autoincrement Autodecrement Register indirect, BRANCH (170) OR (171); WMFC Fig. 3.31 Flowchart of a microprogram for the ADD (Rgrc}*, Ryst instructionComputer Organization & Architecture 3-41 Basic Processing Unit 3.5.3 Techniques for Modification or Generation of Branch Addresses Bit-ORing In this technique, the branch address is determined by ORing particular bit or bits with the current address of the microinstruction. For example, if the current address is 170 and the branch address is 172 then the branch address can be generated by ORing 02 (bit 1), with the current address. Using Condition Variables In this technique the condition variables are used to modify the contents of the CM address register directly, thus eliminating whole or in part the need for branch addresses in microinstructions. For example, let the condition variable CY indicate occurrance of CY=1 and no carry when CY = 0. Suppose that we want to execute a SKIP_ON_CARRY microinstruction. This can be done by logically connecting CY to the count enable input of upc at on appropriate point in the microinstruction cycle. This allows the overflow condition to increment upc an extra time, thus performing the desired skip operation. Wide-Branch Addressing Generating branch addresses becomes more difficult as the number of branches increases. In such situations Programmable Logic Array can be used to generate the required branch addresses. This simple and inexpensive way of generating branch addresses is known as wide-branch addressing. Here, the opcode of a machine instruction is translated into the starting address of the corresponding micro-routine. This is achieved by connecting the opcode bits of the instruction register as inputs to the PLA, which acts as a decoder. The output of the PLA is the address of the desired microroutine. 3.5.4 Examples ‘mp Example 3.2: For a single bus organisation of CPU, write a microprogram for instruction. Add (Ryp)+, Rage Solution : Let us examine the path needed for the flowchart in 3.31 to execute the instruction Add(R,,.)+, Rast In this instruction the source operand is accessed in the autoincrement mode and the R,,. and Ryg are general purpose registers in the processor. We assume that the processor has 16 registers that can be used for addressing purpose, each specified using a 4bit code. We also assume that the instruction has a 3-bit field, (bits 8-10) used to specify the addressing mode for the source operand, as shown in the Fig. 3.32. Bit patterns 11,1001 and 00 located in bits 10 and 9 denote the indexed, autodecrement, autoincrement and register modes respectively. For each of theseComputer Organization & Architecture 3 - 42, Basic Processing Unit modes bit-8 is used to specify the indirect version. For example, 100 in the mode field specifies the direct version of the autodecrement mode, whereas 101 specifies the indirect version. ‘As a part of execution, first the opcode and mode fields are decoded to determine that an R,,. or Ry register is involved. The decoded output is then used to gate the contents of the R,,, or Rus fields in the IR into a second decoder, which produces the gating signals for the actual registers Ry to Rys. [= f TT] 11 10 a7 43 0 Fig. 3.32 Contents of IR The flowchart of a microprogram for the ADD Rye Rye instruction in Fig. 3.31 is drawn by combining the microroutines for all possible values of the mode field, resulting in a structure that requires many branch points. The instruction Add (R,.)+, Rag: requires two branch microinstructions. In each branch microinstruction, the expression in brackets indicates the branch address that is to be loaded into the upc and how this address is modified using the bit-ORing scheme. For example, the branch instruction at location 123 modifies the branch address 170 to 171 by ORing the bit-8 in the IR with bit upc0 to change the addressing mode from indirect to direct, as shown in Fig. 3.33. a a ee SP) feted Tedd Te fet f= ee Fab 1 TRO = 0 : Direct Fig. 3.33 The address for branch microinstruction at location 003 is generated as shown in Fig. 3.34.Computer Organization & Architecture 3 - 43 Basic Processing Unit Bits Modified by bit-ORing a o7 6 75 4 3% 2 4 0 Fixed Bits R10. IR —— from — instruction decoder A¥omncrement Fig. 3.34 Bit ORing for branch microinstruction at location 003 The Table 37 gives the microinstruction sequence for the execution of Add (Ry.)+, Rage instruction. PCout, MARin. Read, Yin, SelectC, Add, Zin Zouty PCig, MWFC MDRout- 'Rin upc +(10f},from instruction decoder uBranch je [Riva]. wpcse[ Ro] { me}{al Le. MPC5.4.3 (010), R scouts MARjn, Read, SelectC, Add, Zip Zoutr Rercin Branch {HPC (170),from instruction decoder peg IRs), WMFC MDRout- Yin Restouts SelectY, Add, Zin, Zoutr Rastours End Table 3.7 Microinstruction for Add (Ry,c)*, RastComputer Organization & Architecture 3-44 Basic Processing Unit tm) Example 3.3 : For a single bus organisation of CPU draw flowchart of a°microprogram for instruction Add (Ryy.)+, Rage Solution : Flowchart 000 MAR = [PC]; Read; Z<— [PC]+1 001 Fig. 3.35Computer Organization & Architecture 3-45 Basic Processing Unit ump Example 3.4 : For a single bus organisation of data paths inside the CPU, write a microprogram of micro-instructions and draw chart of a microprogram for the following instruction. MOV (Reyc)+, Ryct- Ragi uses direct and Rg,. autoincrement addressing. Solution : Flowchart MAR [PC]; Read; Z-[PC] +1 001 PC 2; WMFC. 002 IR =—[MOR} 003 BRANCH (121) i 321 MAR [Rg]; Read Z="KRol * 1 122 123 BRANCH (271) y__271 Cénd) Fig. 3.36 = 000 | PC. MAR», Read, Yin, SelectC, Add, Zi, 001 | Zoyy PCjq, MWFC MOR ue [Rin pc <-(101),from instruction decoder rane (on [R09]. wpe [Re] [ ateComputer Organization & Architecture 3-46 Basic Processing Unit R sroouts MARjn, Read, SelectC, Add, Zin Zout» Rercin Branch {upc <-(270),from instruction decoder pce —iRe}, WMFC MOR out, Restins End wm Example 3.5 : For a single bus organisation of CPU draw a flowchart and write microinstructions for instruction ADD (Ree), Rag Solution : Flowchart 000 MAR +— [PC]; Read; Z+— [PC] +1 001 Fig. 3.37Computer Organization & Architecture 3 - 47 Basic Processing Unit Microinstructions [| Poy» MARjn, Read, Yin, SelectC, Add, Zin Zoutr PCiq, MWFC MDRout Rip Branch{ upc +-(10f}from instruction decoder ne <[!Rios ]. wees [R10] -[ spinel Le. Upes.a3 (004, Rsreout MARjq, Read HBranch {upc (170), from instruction decoder pcp +-iRe}, WMFC Branch {upc +-(170),from_ instruction decoder upc) IRs}, WMFC MOR gut Yin Rastout, SelectY, Add, Zp Zoutr Rastiny End Table 3.8 Microinstruction for Add (Ry,), Rast tm Example 3.6: For a single bus organisation of CPU draw a flowchart and write microinstructions for instruction ADD-(Reye), Rig Solution : Flowchart : See on next page. PCout MARin, Read, Yin, Select, Add, Zin Zouts PCjq, MWFC MDRout- 'Rin pBranch{ upc —-(104),from instruction decoder lie €[!Riog ]. upcs [R10] { Re] [Re] Le. ppcs,4.3 (100), R srcout, Select, Sub, ZinComputer Organization & Architecture 3-48 Basic Processing Unit MARin. Rerciny Zou, Read nBranch {upc (170), from instruction decoder pC) 0), BPL (Branch if plus), and BR (Branch unconditionally) instructions. The branch conditions, for the BGT and BPL instructions are Z + (N XOR V) = 0 and N = 0, respectively. What is the total number of micro instructions required ? How many micro instructions are needed if a separate micro routine is used {for each machine instruction ? {1.T. Oct/Nov.-2002] Define microinstruction. [CSE Apri/May-2003] advantages and disadvan ith April/May-2003, LT. No Dec.-2003) Write a microprogram for ADD Reyer Rast instruction. What is the necessity of branching ? What are the different branching techniques used in microprogrammed control unit ? Explain various branching techniques used in microprogrammed control unit. Draw and explain the microprogrammed control unit with next address generation. What is the necessity of next address generation field ? Discuss the organization of a microprogrammed control unit. How are branches implemented here ? % ame iL T-Apwil¥tay-2003) Compare hardwired control unit and microprogrammed control unit. ‘What is nanoprogramming ?