LLVM 23.0.0git
SPIRVInstructionSelector.cpp
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1//===- SPIRVInstructionSelector.cpp ------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the targeting of the InstructionSelector class for
10// SPIRV.
11// TODO: This should be generated by TableGen.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/SPIRVBaseInfo.h"
16#include "MCTargetDesc/SPIRVMCTargetDesc.h"
17#include "SPIRV.h"
18#include "SPIRVGlobalRegistry.h"
19#include "SPIRVInstrInfo.h"
20#include "SPIRVRegisterInfo.h"
21#include "SPIRVTargetMachine.h"
22#include "SPIRVUtils.h"
23#include "llvm/ADT/APFloat.h"
24#include "llvm/ADT/StringExtras.h"
25#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
26#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
27#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/Register.h"
31#include "llvm/CodeGen/TargetOpcodes.h"
32#include "llvm/IR/IntrinsicsSPIRV.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35
36#define DEBUG_TYPE "spirv-isel"
37
38using namespace llvm;
39namespace CL = SPIRV::OpenCLExtInst;
40namespace GL = SPIRV::GLSLExtInst;
41
42using ExtInstList =
43 std::vector<std::pair<SPIRV::InstructionSet::InstructionSet, uint32_t>>;
44
45namespace {
46
47struct ImageOperands {
48 std::optional<Register> Bias;
49 std::optional<Register> Offset;
50 std::optional<Register> MinLod;
51 std::optional<Register> GradX;
52 std::optional<Register> GradY;
53 std::optional<Register> Lod;
54 std::optional<Register> Compare;
55};
56
57llvm::SPIRV::SelectionControl::SelectionControl
58getSelectionOperandForImm(int Imm) {
59 if (Imm == 2)
60 return SPIRV::SelectionControl::Flatten;
61 if (Imm == 1)
62 return SPIRV::SelectionControl::DontFlatten;
63 if (Imm == 0)
64 return SPIRV::SelectionControl::None;
65 llvm_unreachable("Invalid immediate");
66}
67
68#define GET_GLOBALISEL_PREDICATE_BITSET
69#include "SPIRVGenGlobalISel.inc"
70#undef GET_GLOBALISEL_PREDICATE_BITSET
71
72class SPIRVInstructionSelector : public InstructionSelector {
73 const SPIRVSubtarget &STI;
74 const SPIRVInstrInfo &TII;
75 const SPIRVRegisterInfo &TRI;
76 const RegisterBankInfo &RBI;
77 SPIRVGlobalRegistry &GR;
78 MachineRegisterInfo *MRI;
79 MachineFunction *HasVRegsReset = nullptr;
80
81 /// We need to keep track of the number we give to anonymous global values to
82 /// generate the same name every time when this is needed.
83 mutable DenseMap<const GlobalValue *, unsigned> UnnamedGlobalIDs;
84 SmallPtrSet<MachineInstr *, 8> DeadMIs;
85
86public:
87 SPIRVInstructionSelector(const SPIRVTargetMachine &TM,
88 const SPIRVSubtarget &ST,
89 const RegisterBankInfo &RBI);
90 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
91 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
92 BlockFrequencyInfo *BFI) override;
93 // Common selection code. Instruction-specific selection occurs in spvSelect.
94 bool select(MachineInstr &I) override;
95 static const char *getName() { return DEBUG_TYPE; }
96
97#define GET_GLOBALISEL_PREDICATES_DECL
98#include "SPIRVGenGlobalISel.inc"
99#undef GET_GLOBALISEL_PREDICATES_DECL
100
101#define GET_GLOBALISEL_TEMPORARIES_DECL
102#include "SPIRVGenGlobalISel.inc"
103#undef GET_GLOBALISEL_TEMPORARIES_DECL
104
105private:
106 void resetVRegsType(MachineFunction &MF);
107 void removeDeadInstruction(MachineInstr &MI) const;
108 void removeOpNamesForDeadMI(MachineInstr &MI) const;
109
110 // tblgen-erated 'select' implementation, used as the initial selector for
111 // the patterns that don't require complex C++.
112 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
113
114 // All instruction-specific selection that didn't happen in "select()".
115 // Is basically a large Switch/Case delegating to all other select method.
116 bool spvSelect(Register ResVReg, SPIRVTypeInst ResType,
117 MachineInstr &I) const;
118
119 bool selectFirstBitHigh(Register ResVReg, SPIRVTypeInst ResType,
120 MachineInstr &I, bool IsSigned) const;
121
122 bool selectFirstBitLow(Register ResVReg, SPIRVTypeInst ResType,
123 MachineInstr &I) const;
124
125 bool selectFirstBitSet16(Register ResVReg, SPIRVTypeInst ResType,
126 MachineInstr &I, unsigned ExtendOpcode,
127 unsigned BitSetOpcode) const;
128
129 bool selectFirstBitSet32(Register ResVReg, SPIRVTypeInst ResType,
130 MachineInstr &I, Register SrcReg,
131 unsigned BitSetOpcode) const;
132
133 bool selectFirstBitSet64(Register ResVReg, SPIRVTypeInst ResType,
134 MachineInstr &I, Register SrcReg,
135 unsigned BitSetOpcode, bool SwapPrimarySide) const;
136
137 bool selectFirstBitSet64Overflow(Register ResVReg, SPIRVTypeInst ResType,
138 MachineInstr &I, Register SrcReg,
139 unsigned BitSetOpcode,
140 bool SwapPrimarySide) const;
141
142 bool selectGlobalValue(Register ResVReg, MachineInstr &I,
143 const MachineInstr *Init = nullptr) const;
144
145 bool selectOpWithSrcs(Register ResVReg, SPIRVTypeInst ResType,
146 MachineInstr &I, std::vector<Register> SrcRegs,
147 unsigned Opcode) const;
148
149 bool selectUnOp(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
150 unsigned Opcode) const;
151
152 bool selectBitcast(Register ResVReg, SPIRVTypeInst ResType,
153 MachineInstr &I) const;
154
155 bool selectLoad(Register ResVReg, SPIRVTypeInst ResType,
156 MachineInstr &I) const;
157 bool selectStore(MachineInstr &I) const;
158
159 bool selectStackSave(Register ResVReg, SPIRVTypeInst ResType,
160 MachineInstr &I) const;
161 bool selectStackRestore(MachineInstr &I) const;
162
163 bool selectMemOperation(Register ResVReg, MachineInstr &I) const;
164 Register getOrCreateMemSetGlobal(MachineInstr &I) const;
165 bool selectCopyMemory(MachineInstr &I, Register SrcReg) const;
166 bool selectCopyMemorySized(MachineInstr &I, Register SrcReg) const;
167
168 bool selectAtomicRMW(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
169 unsigned NewOpcode, unsigned NegateOpcode = 0) const;
170
171 bool selectAtomicCmpXchg(Register ResVReg, SPIRVTypeInst ResType,
172 MachineInstr &I) const;
173
174 bool selectFence(MachineInstr &I) const;
175
176 bool selectAddrSpaceCast(Register ResVReg, SPIRVTypeInst ResType,
177 MachineInstr &I) const;
178
179 bool selectAnyOrAll(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
180 unsigned OpType) const;
181
182 bool selectAll(Register ResVReg, SPIRVTypeInst ResType,
183 MachineInstr &I) const;
184
185 bool selectAny(Register ResVReg, SPIRVTypeInst ResType,
186 MachineInstr &I) const;
187
188 bool selectBitreverse(Register ResVReg, SPIRVTypeInst ResType,
189 MachineInstr &I) const;
190
191 bool selectBuildVector(Register ResVReg, SPIRVTypeInst ResType,
192 MachineInstr &I) const;
193 bool selectSplatVector(Register ResVReg, SPIRVTypeInst ResType,
194 MachineInstr &I) const;
195
196 bool selectCmp(Register ResVReg, SPIRVTypeInst ResType,
197 unsigned comparisonOpcode, MachineInstr &I) const;
198 bool selectDiscard(Register ResVReg, SPIRVTypeInst ResType,
199 MachineInstr &I) const;
200
201 bool selectICmp(Register ResVReg, SPIRVTypeInst ResType,
202 MachineInstr &I) const;
203 bool selectFCmp(Register ResVReg, SPIRVTypeInst ResType,
204 MachineInstr &I) const;
205
206 bool selectSign(Register ResVReg, SPIRVTypeInst ResType,
207 MachineInstr &I) const;
208
209 bool selectFloatDot(Register ResVReg, SPIRVTypeInst ResType,
210 MachineInstr &I) const;
211
212 bool selectOverflowArith(Register ResVReg, SPIRVTypeInst ResType,
213 MachineInstr &I, unsigned Opcode) const;
214 bool selectDebugTrap(Register ResVReg, SPIRVTypeInst ResType,
215 MachineInstr &I) const;
216
217 bool selectIntegerDot(Register ResVReg, SPIRVTypeInst ResType,
218 MachineInstr &I, bool Signed) const;
219
220 bool selectIntegerDotExpansion(Register ResVReg, SPIRVTypeInst ResType,
221 MachineInstr &I) const;
222
223 bool selectOpIsInf(Register ResVReg, SPIRVTypeInst ResType,
224 MachineInstr &I) const;
225
226 bool selectOpIsNan(Register ResVReg, SPIRVTypeInst ResType,
227 MachineInstr &I) const;
228
229 template <bool Signed>
230 bool selectDot4AddPacked(Register ResVReg, SPIRVTypeInst ResType,
231 MachineInstr &I) const;
232 template <bool Signed>
233 bool selectDot4AddPackedExpansion(Register ResVReg, SPIRVTypeInst ResType,
234 MachineInstr &I) const;
235
236 bool selectWavePrefixBitCount(Register ResVReg, SPIRVTypeInst ResType,
237 MachineInstr &I) const;
238
239 template <typename PickOpcodeFn>
240 bool selectWaveReduce(Register ResVReg, SPIRVTypeInst ResType,
241 MachineInstr &I, bool IsUnsigned,
242 PickOpcodeFn &&PickOpcode) const;
243
244 bool selectWaveReduceMax(Register ResVReg, SPIRVTypeInst ResType,
245 MachineInstr &I, bool IsUnsigned) const;
246
247 bool selectWaveReduceMin(Register ResVReg, SPIRVTypeInst ResType,
248 MachineInstr &I, bool IsUnsigned) const;
249
250 bool selectWaveReduceSum(Register ResVReg, SPIRVTypeInst ResType,
251 MachineInstr &I) const;
252
253 template <typename PickOpcodeFn>
254 bool selectWaveExclusiveScan(Register ResVReg, SPIRVTypeInst ResType,
255 MachineInstr &I, bool IsUnsigned,
256 PickOpcodeFn &&PickOpcode) const;
257
258 bool selectWaveExclusiveScanSum(Register ResVReg, SPIRVTypeInst ResType,
259 MachineInstr &I) const;
260
261 bool selectWaveExclusiveScanProduct(Register ResVReg, SPIRVTypeInst ResType,
262 MachineInstr &I) const;
263
264 bool selectConst(Register ResVReg, SPIRVTypeInst ResType,
265 MachineInstr &I) const;
266
267 bool selectSelect(Register ResVReg, SPIRVTypeInst ResType,
268 MachineInstr &I) const;
269 bool selectBoolToInt(Register ResVReg, SPIRVTypeInst ResType,
270 Register BooleanVReg, MachineInstr &InsertAt,
271 bool IsSigned) const;
272 bool selectIToF(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
273 bool IsSigned, unsigned Opcode) const;
274 bool selectExt(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
275 bool IsSigned) const;
276
277 bool selectTrunc(Register ResVReg, SPIRVTypeInst ResType,
278 MachineInstr &I) const;
279
280 bool selectSUCmp(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
281 bool IsSigned) const;
282
283 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
284 SPIRVTypeInst intTy, SPIRVTypeInst boolTy) const;
285
286 bool selectOpUndef(Register ResVReg, SPIRVTypeInst ResType,
287 MachineInstr &I) const;
288 bool selectFreeze(Register ResVReg, SPIRVTypeInst ResType,
289 MachineInstr &I) const;
290 bool selectIntrinsic(Register ResVReg, SPIRVTypeInst ResType,
291 MachineInstr &I) const;
292 bool selectExtractVal(Register ResVReg, SPIRVTypeInst ResType,
293 MachineInstr &I) const;
294 bool selectInsertVal(Register ResVReg, SPIRVTypeInst ResType,
295 MachineInstr &I) const;
296 bool selectExtractElt(Register ResVReg, SPIRVTypeInst ResType,
297 MachineInstr &I) const;
298 bool selectInsertElt(Register ResVReg, SPIRVTypeInst ResType,
299 MachineInstr &I) const;
300 bool selectGEP(Register ResVReg, SPIRVTypeInst ResType,
301 MachineInstr &I) const;
302
303 bool selectFrameIndex(Register ResVReg, SPIRVTypeInst ResType,
304 MachineInstr &I) const;
305 bool selectAllocaArray(Register ResVReg, SPIRVTypeInst ResType,
306 MachineInstr &I) const;
307
308 bool selectBranch(MachineInstr &I) const;
309 bool selectBranchCond(MachineInstr &I) const;
310
311 bool selectPhi(Register ResVReg, MachineInstr &I) const;
312
313 bool selectExtInst(Register ResVReg, SPIRVTypeInst RestType, MachineInstr &I,
314 GL::GLSLExtInst GLInst, bool setMIFlags = true,
315 bool useMISrc = true,
316 ArrayRef<Register> SrcRegs = {}) const;
317 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
318 CL::OpenCLExtInst CLInst, bool setMIFlags = true,
319 bool useMISrc = true,
320 ArrayRef<Register> SrcRegs = {}) const;
321 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
322 CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst,
323 bool setMIFlags = true, bool useMISrc = true,
324 ArrayRef<Register> SrcRegs = {}) const;
325 bool selectExtInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
326 const ExtInstList &ExtInsts, bool setMIFlags = true,
327 bool useMISrc = true,
328 ArrayRef<Register> SrcRegs = {}) const;
329
330 bool selectLog10(Register ResVReg, SPIRVTypeInst ResType,
331 MachineInstr &I) const;
332
333 bool selectSaturate(Register ResVReg, SPIRVTypeInst ResType,
334 MachineInstr &I) const;
335
336 bool selectWaveOpInst(Register ResVReg, SPIRVTypeInst ResType,
337 MachineInstr &I, unsigned Opcode) const;
338
339 bool selectWaveActiveCountBits(Register ResVReg, SPIRVTypeInst ResType,
340 MachineInstr &I) const;
341
342 bool selectWaveActiveAllEqual(Register ResVReg, SPIRVTypeInst ResType,
343 MachineInstr &I) const;
344
345 bool selectUnmergeValues(MachineInstr &I) const;
346
347 bool selectHandleFromBinding(Register &ResVReg, SPIRVTypeInst ResType,
348 MachineInstr &I) const;
349
350 bool selectCounterHandleFromBinding(Register &ResVReg, SPIRVTypeInst ResType,
351 MachineInstr &I) const;
352
353 bool selectReadImageIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
354 MachineInstr &I) const;
355 bool selectSampleBasicIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
356 MachineInstr &I) const;
357 bool selectSampleBiasIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
358 MachineInstr &I) const;
359 bool selectSampleGradIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
360 MachineInstr &I) const;
361 bool selectSampleLevelIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
362 MachineInstr &I) const;
363 bool selectSampleCmpIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
364 MachineInstr &I) const;
365 bool selectSampleCmpLevelZeroIntrinsic(Register &ResVReg,
366 SPIRVTypeInst ResType,
367 MachineInstr &I) const;
368 bool selectGatherIntrinsic(Register &ResVReg, SPIRVTypeInst ResType,
369 MachineInstr &I) const;
370 bool selectImageWriteIntrinsic(MachineInstr &I) const;
371 bool selectResourceGetPointer(Register &ResVReg, SPIRVTypeInst ResType,
372 MachineInstr &I) const;
373 bool selectPushConstantGetPointer(Register &ResVReg, SPIRVTypeInst ResType,
374 MachineInstr &I) const;
375 bool selectResourceNonUniformIndex(Register &ResVReg, SPIRVTypeInst ResType,
376 MachineInstr &I) const;
377 bool selectModf(Register ResVReg, SPIRVTypeInst ResType,
378 MachineInstr &I) const;
379 bool selectUpdateCounter(Register &ResVReg, SPIRVTypeInst ResType,
380 MachineInstr &I) const;
381 bool selectFrexp(Register ResVReg, SPIRVTypeInst ResType,
382 MachineInstr &I) const;
383 bool selectSincos(Register ResVReg, SPIRVTypeInst ResType,
384 MachineInstr &I) const;
385 bool selectExp10(Register ResVReg, SPIRVTypeInst ResType,
386 MachineInstr &I) const;
387 bool selectDerivativeInst(Register ResVReg, SPIRVTypeInst ResType,
388 MachineInstr &I, const unsigned DPdOpCode) const;
389 // Utilities
390 Register buildI32Constant(uint32_t Val, MachineInstr &I,
391 SPIRVTypeInst ResType = nullptr) const;
392
393 Register buildZerosVal(SPIRVTypeInst ResType, MachineInstr &I) const;
394 bool isScalarOrVectorIntConstantZero(Register Reg) const;
395 Register buildZerosValF(SPIRVTypeInst ResType, MachineInstr &I) const;
396 Register buildOnesVal(bool AllOnes, SPIRVTypeInst ResType,
397 MachineInstr &I) const;
398 Register buildOnesValF(SPIRVTypeInst ResType, MachineInstr &I) const;
399
400 bool wrapIntoSpecConstantOp(MachineInstr &I,
401 SmallVector<Register> &CompositeArgs) const;
402
403 Register getUcharPtrTypeReg(MachineInstr &I,
404 SPIRV::StorageClass::StorageClass SC) const;
405 MachineInstrBuilder buildSpecConstantOp(MachineInstr &I, Register Dest,
406 Register Src, Register DestType,
407 uint32_t Opcode) const;
408 MachineInstrBuilder buildConstGenericPtr(MachineInstr &I, Register SrcPtr,
409 SPIRVTypeInst SrcPtrTy) const;
410 Register buildPointerToResource(SPIRVTypeInst ResType,
411 SPIRV::StorageClass::StorageClass SC,
412 uint32_t Set, uint32_t Binding,
413 uint32_t ArraySize, Register IndexReg,
414 StringRef Name,
415 MachineIRBuilder MIRBuilder) const;
416 SPIRVTypeInst widenTypeToVec4(SPIRVTypeInst Type, MachineInstr &I) const;
417 bool extractSubvector(Register &ResVReg, SPIRVTypeInst ResType,
418 Register &ReadReg, MachineInstr &InsertionPoint) const;
419 bool generateImageReadOrFetch(Register &ResVReg, SPIRVTypeInst ResType,
420 Register ImageReg, Register IdxReg,
421 DebugLoc Loc, MachineInstr &Pos) const;
422 bool generateSampleImage(Register ResVReg, SPIRVTypeInst ResType,
423 Register ImageReg, Register SamplerReg,
424 Register CoordinateReg, const ImageOperands &ImOps,
425 DebugLoc Loc, MachineInstr &I) const;
426 bool BuildCOPY(Register DestReg, Register SrcReg, MachineInstr &I) const;
427 bool loadVec3BuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
428 Register ResVReg, SPIRVTypeInst ResType,
429 MachineInstr &I) const;
430 bool loadBuiltinInputID(SPIRV::BuiltIn::BuiltIn BuiltInValue,
431 Register ResVReg, SPIRVTypeInst ResType,
432 MachineInstr &I) const;
433 bool loadHandleBeforePosition(Register &HandleReg, SPIRVTypeInst ResType,
434 GIntrinsic &HandleDef, MachineInstr &Pos) const;
435 void decorateUsesAsNonUniform(Register &NonUniformReg) const;
436 void errorIfInstrOutsideShader(MachineInstr &I) const;
437};
438
439bool sampledTypeIsSignedInteger(const llvm::Type *HandleType) {
440 const TargetExtType *TET = cast<TargetExtType>(HandleType);
441 if (TET->getTargetExtName() == "spirv.Image") {
442 return false;
443 }
444 assert(TET->getTargetExtName() == "spirv.SignedImage");
445 return TET->getTypeParameter(0)->isIntegerTy();
446}
447} // end anonymous namespace
448
449#define GET_GLOBALISEL_IMPL
450#include "SPIRVGenGlobalISel.inc"
451#undef GET_GLOBALISEL_IMPL
452
453SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM,
454 const SPIRVSubtarget &ST,
455 const RegisterBankInfo &RBI)
456 : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()),
457 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()),
458 MRI(nullptr),
459#define GET_GLOBALISEL_PREDICATES_INIT
460#include "SPIRVGenGlobalISel.inc"
461#undef GET_GLOBALISEL_PREDICATES_INIT
462#define GET_GLOBALISEL_TEMPORARIES_INIT
463#include "SPIRVGenGlobalISel.inc"
464#undef GET_GLOBALISEL_TEMPORARIES_INIT
465{
466}
467
468void SPIRVInstructionSelector::setupMF(MachineFunction &MF,
469 GISelValueTracking *VT,
470 CodeGenCoverage *CoverageInfo,
471 ProfileSummaryInfo *PSI,
472 BlockFrequencyInfo *BFI) {
473 MRI = &MF.getRegInfo();
474 GR.setCurrentFunc(MF);
475 InstructionSelector::setupMF(MF, VT, CoverageInfo, PSI, BFI);
476}
477
478// Ensure that register classes correspond to pattern matching rules.
479void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
480 if (HasVRegsReset == &MF)
481 return;
482 HasVRegsReset = &MF;
483
484 MachineRegisterInfo &MRI = MF.getRegInfo();
485 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
486 Register Reg = Register::index2VirtReg(I);
487 LLT RegType = MRI.getType(Reg);
488 if (RegType.isScalar())
489 MRI.setType(Reg, LLT::scalar(64));
490 else if (RegType.isPointer())
491 MRI.setType(Reg, LLT::pointer(0, 64));
492 else if (RegType.isVector())
493 MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(64)));
494 }
495 for (const auto &MBB : MF) {
496 for (const auto &MI : MBB) {
497 if (isPreISelGenericOpcode(MI.getOpcode()))
498 GR.erase(&MI);
499 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
500 continue;
501
502 Register DstReg = MI.getOperand(0).getReg();
503 LLT DstType = MRI.getType(DstReg);
504 Register SrcReg = MI.getOperand(1).getReg();
505 LLT SrcType = MRI.getType(SrcReg);
506 if (DstType != SrcType)
507 MRI.setType(DstReg, MRI.getType(SrcReg));
508
509 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
510 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
511 if (DstRC != SrcRC && SrcRC)
512 MRI.setRegClass(DstReg, SrcRC);
513 }
514 }
515}
516
517// Return true if the MachineInstr represents a constant register
518static bool isConstReg(MachineRegisterInfo *MRI, MachineInstr *OpDef) {
519
520 SmallVector<MachineInstr *> Stack = {OpDef};
521 SmallPtrSet<MachineInstr *, 4> Visited;
522
523 while (!Stack.empty()) {
524 MachineInstr *MI = Stack.pop_back_val();
525 MI = passCopy(MI, MRI);
526 if (!Visited.insert(MI).second)
527 continue;
528 switch (MI->getOpcode()) {
529 case TargetOpcode::G_INTRINSIC:
530 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
531 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
532 if (cast<GIntrinsic>(*OpDef).getIntrinsicID() !=
533 Intrinsic::spv_const_composite)
534 return false;
535 continue;
536 case TargetOpcode::G_BUILD_VECTOR:
537 case TargetOpcode::G_SPLAT_VECTOR:
538 for (unsigned i = OpDef->getNumExplicitDefs();
539 i < OpDef->getNumOperands(); i++) {
540 if (!OpDef->getOperand(i).isReg())
541 continue;
542 MachineInstr *OpNestedDef =
543 MRI->getVRegDef(OpDef->getOperand(i).getReg());
544 Stack.push_back(OpNestedDef);
545 }
546 continue;
547 case TargetOpcode::G_CONSTANT:
548 case TargetOpcode::G_FCONSTANT:
549 case TargetOpcode::G_IMPLICIT_DEF:
550 case SPIRV::OpConstantTrue:
551 case SPIRV::OpConstantFalse:
552 case SPIRV::OpConstantI:
553 case SPIRV::OpConstantF:
554 case SPIRV::OpConstantComposite:
555 case SPIRV::OpConstantCompositeContinuedINTEL:
556 case SPIRV::OpConstantSampler:
557 case SPIRV::OpConstantNull:
558 case SPIRV::OpUndef:
559 case SPIRV::OpConstantFunctionPointerINTEL:
560 continue;
561 default:
562 return false;
563 }
564 }
565 return true;
566}
567
568// Return true if the virtual register represents a constant
569static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) {
570 if (MachineInstr *OpDef = MRI->getVRegDef(OpReg))
571 return isConstReg(MRI, OpDef);
572 return false;
573}
574
575// TODO(168736): We should make this either a flag in tabelgen
576// or reduce our dependence on the global registry, so we can remove this
577// function. It can easily be missed when new intrinsics are added.
578
579// Most SPIR-V intrinsics are considered to have side-effects in their tablegen
580// definition because they are referenced in the global registry. This is a list
581// of intrinsics that have no side effects other than their references in the
582// global registry.
583static bool intrinsicHasSideEffects(Intrinsic::ID ID) {
584 switch (ID) {
585 // This is not an exhaustive list and may need to be updated.
586 case Intrinsic::spv_all:
587 case Intrinsic::spv_alloca:
588 case Intrinsic::spv_any:
589 case Intrinsic::spv_bitcast:
590 case Intrinsic::spv_const_composite:
591 case Intrinsic::spv_cross:
592 case Intrinsic::spv_degrees:
593 case Intrinsic::spv_distance:
594 case Intrinsic::spv_extractelt:
595 case Intrinsic::spv_extractv:
596 case Intrinsic::spv_faceforward:
597 case Intrinsic::spv_fdot:
598 case Intrinsic::spv_firstbitlow:
599 case Intrinsic::spv_firstbitshigh:
600 case Intrinsic::spv_firstbituhigh:
601 case Intrinsic::spv_frac:
602 case Intrinsic::spv_gep:
603 case Intrinsic::spv_global_offset:
604 case Intrinsic::spv_global_size:
605 case Intrinsic::spv_group_id:
606 case Intrinsic::spv_insertelt:
607 case Intrinsic::spv_insertv:
608 case Intrinsic::spv_isinf:
609 case Intrinsic::spv_isnan:
610 case Intrinsic::spv_lerp:
611 case Intrinsic::spv_length:
612 case Intrinsic::spv_normalize:
613 case Intrinsic::spv_num_subgroups:
614 case Intrinsic::spv_num_workgroups:
615 case Intrinsic::spv_ptrcast:
616 case Intrinsic::spv_radians:
617 case Intrinsic::spv_reflect:
618 case Intrinsic::spv_refract:
619 case Intrinsic::spv_resource_getpointer:
620 case Intrinsic::spv_resource_handlefrombinding:
621 case Intrinsic::spv_resource_handlefromimplicitbinding:
622 case Intrinsic::spv_resource_nonuniformindex:
623 case Intrinsic::spv_resource_sample:
624 case Intrinsic::spv_rsqrt:
625 case Intrinsic::spv_saturate:
626 case Intrinsic::spv_sdot:
627 case Intrinsic::spv_sign:
628 case Intrinsic::spv_smoothstep:
629 case Intrinsic::spv_step:
630 case Intrinsic::spv_subgroup_id:
631 case Intrinsic::spv_subgroup_local_invocation_id:
632 case Intrinsic::spv_subgroup_max_size:
633 case Intrinsic::spv_subgroup_size:
634 case Intrinsic::spv_thread_id:
635 case Intrinsic::spv_thread_id_in_group:
636 case Intrinsic::spv_udot:
637 case Intrinsic::spv_undef:
638 case Intrinsic::spv_value_md:
639 case Intrinsic::spv_workgroup_size:
640 return false;
641 default:
642 return true;
643 }
644}
645
646// TODO(168736): We should make this either a flag in tabelgen
647// or reduce our dependence on the global registry, so we can remove this
648// function. It can easily be missed when new intrinsics are added.
649static bool isOpcodeWithNoSideEffects(unsigned Opcode) {
650 switch (Opcode) {
651 case SPIRV::OpTypeVoid:
652 case SPIRV::OpTypeBool:
653 case SPIRV::OpTypeInt:
654 case SPIRV::OpTypeFloat:
655 case SPIRV::OpTypeVector:
656 case SPIRV::OpTypeMatrix:
657 case SPIRV::OpTypeImage:
658 case SPIRV::OpTypeSampler:
659 case SPIRV::OpTypeSampledImage:
660 case SPIRV::OpTypeArray:
661 case SPIRV::OpTypeRuntimeArray:
662 case SPIRV::OpTypeStruct:
663 case SPIRV::OpTypeOpaque:
664 case SPIRV::OpTypePointer:
665 case SPIRV::OpTypeFunction:
666 case SPIRV::OpTypeEvent:
667 case SPIRV::OpTypeDeviceEvent:
668 case SPIRV::OpTypeReserveId:
669 case SPIRV::OpTypeQueue:
670 case SPIRV::OpTypePipe:
671 case SPIRV::OpTypeForwardPointer:
672 case SPIRV::OpTypePipeStorage:
673 case SPIRV::OpTypeNamedBarrier:
674 case SPIRV::OpTypeAccelerationStructureNV:
675 case SPIRV::OpTypeCooperativeMatrixNV:
676 case SPIRV::OpTypeCooperativeMatrixKHR:
677 return true;
678 default:
679 return false;
680 }
681}
682
683bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI) {
684 // If there are no definitions, then assume there is some other
685 // side-effect that makes this instruction live.
686 if (MI.getNumDefs() == 0)
687 return false;
688
689 for (const auto &MO : MI.all_defs()) {
690 Register Reg = MO.getReg();
691 if (Reg.isPhysical()) {
692 LLVM_DEBUG(dbgs() << "Not dead: def of physical register " << Reg);
693 return false;
694 }
695 for (const auto &UseMI : MRI.use_nodbg_instructions(Reg)) {
696 if (UseMI.getOpcode() != SPIRV::OpName) {
697 LLVM_DEBUG(dbgs() << "Not dead: def " << MO << " has use in " << UseMI);
698 return false;
699 }
700 }
701 }
702
703 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE || MI.isFakeUse() ||
704 MI.isLifetimeMarker()) {
705 LLVM_DEBUG(
706 dbgs()
707 << "Not dead: Opcode is LOCAL_ESCAPE, fake use, or lifetime marker.\n");
708 return false;
709 }
710 if (MI.isPHI()) {
711 LLVM_DEBUG(dbgs() << "Dead: Phi instruction with no uses.\n");
712 return true;
713 }
714
715 // It is possible that the only side effect is that the instruction is
716 // referenced in the global registry. If that is the only side effect, the
717 // intrinsic is dead.
718 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
719 MI.getOpcode() == TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
720 const auto &Intr = cast<GIntrinsic>(MI);
721 if (!intrinsicHasSideEffects(Intr.getIntrinsicID())) {
722 LLVM_DEBUG(dbgs() << "Dead: Intrinsic with no real side effects.\n");
723 return true;
724 }
725 }
726
727 if (MI.mayStore() || MI.isCall() ||
728 (MI.mayLoad() && MI.hasOrderedMemoryRef()) || MI.isPosition() ||
729 MI.isDebugInstr() || MI.isTerminator() || MI.isJumpTableDebugInfo()) {
730 LLVM_DEBUG(dbgs() << "Not dead: instruction has side effects.\n");
731 return false;
732 }
733
734 if (isPreISelGenericOpcode(MI.getOpcode())) {
735 // TODO: Is there a generic way to check if the opcode has side effects?
736 LLVM_DEBUG(dbgs() << "Dead: Generic opcode with no uses.\n");
737 return true;
738 }
739
740 if (isOpcodeWithNoSideEffects(MI.getOpcode())) {
741 LLVM_DEBUG(dbgs() << "Dead: known opcode with no side effects\n");
742 return true;
743 }
744
745 return false;
746}
747
748void SPIRVInstructionSelector::removeOpNamesForDeadMI(MachineInstr &MI) const {
749 // Delete the OpName that uses the result if there is one.
750 for (const auto &MO : MI.all_defs()) {
751 Register Reg = MO.getReg();
752 if (Reg.isPhysical())
753 continue;
754 SmallVector<MachineInstr *, 4> UselessOpNames;
755 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
756 assert(UseMI.getOpcode() == SPIRV::OpName &&
757 "There is still a use of the dead function.");
758 UselessOpNames.push_back(&UseMI);
759 }
760 for (MachineInstr *OpNameMI : UselessOpNames) {
761 GR.invalidateMachineInstr(OpNameMI);
762 OpNameMI->eraseFromParent();
763 }
764 }
765}
766
767void SPIRVInstructionSelector::removeDeadInstruction(MachineInstr &MI) const {
768 salvageDebugInfo(*MRI, MI);
769 GR.invalidateMachineInstr(&MI);
770 removeOpNamesForDeadMI(MI);
771 MI.eraseFromParent();
772}
773
774bool SPIRVInstructionSelector::select(MachineInstr &I) {
775 resetVRegsType(*I.getParent()->getParent());
776
777 assert(I.getParent() && "Instruction should be in a basic block!");
778 assert(I.getParent()->getParent() && "Instruction should be in a function!");
779
780 LLVM_DEBUG(dbgs() << "Checking if instruction is dead: " << I;);
781 if (isDead(I, *MRI)) {
782 LLVM_DEBUG(dbgs() << "Instruction is dead.\n");
783 removeDeadInstruction(I);
784 return true;
785 }
786
787 Register Opcode = I.getOpcode();
788 // If it's not a GMIR instruction, we've selected it already.
789 if (!isPreISelGenericOpcode(Opcode)) {
790 if (Opcode == SPIRV::ASSIGN_TYPE) { // These pseudos aren't needed any more.
791 Register DstReg = I.getOperand(0).getReg();
792 Register SrcReg = I.getOperand(1).getReg();
793 auto *Def = MRI->getVRegDef(SrcReg);
794 if (isTypeFoldingSupported(Def->getOpcode()) &&
795 Def->getOpcode() != TargetOpcode::G_CONSTANT &&
796 Def->getOpcode() != TargetOpcode::G_FCONSTANT) {
797 if (Def->getOpcode() == TargetOpcode::G_SELECT) {
798 Register SelectDstReg = Def->getOperand(0).getReg();
799 bool SuccessToSelectSelect [[maybe_unused]] = selectSelect(
800 SelectDstReg, GR.getSPIRVTypeForVReg(SelectDstReg), *Def);
801 assert(SuccessToSelectSelect);
802 GR.invalidateMachineInstr(Def);
803 Def->eraseFromParent();
804 MRI->replaceRegWith(DstReg, SelectDstReg);
805 GR.invalidateMachineInstr(&I);
806 I.eraseFromParent();
807 return true;
808 }
809
810 bool Res = selectImpl(I, *CoverageInfo);
811 LLVM_DEBUG({
812 if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
813 dbgs() << "Unexpected pattern in ASSIGN_TYPE.\nInstruction: ";
814 I.print(dbgs());
815 }
816 });
817 assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
818 if (Res) {
819 if (!isTriviallyDead(*Def, *MRI) && isDead(*Def, *MRI))
820 DeadMIs.insert(Def);
821 return Res;
822 }
823 }
824 MRI->setRegClass(SrcReg, MRI->getRegClass(DstReg));
825 MRI->replaceRegWith(SrcReg, DstReg);
826 GR.invalidateMachineInstr(&I);
827 I.eraseFromParent();
828 return true;
829 } else if (I.getNumDefs() == 1) {
830 // Make all vregs 64 bits (for SPIR-V IDs).
831 MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));
832 }
833 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
834 return true;
835 }
836
837 if (DeadMIs.contains(&I)) {
838 // if the instruction has been already made dead by folding it away
839 // erase it
840 LLVM_DEBUG(dbgs() << "Instruction is folded and dead.\n");
841 removeDeadInstruction(I);
842 DeadMIs.erase(&I);
843 return true;
844 }
845
846 if (I.getNumOperands() != I.getNumExplicitOperands()) {
847 LLVM_DEBUG(errs() << "Generic instr has unexpected implicit operands\n");
848 return false;
849 }
850
851 // Common code for getting return reg+type, and removing selected instr
852 // from parent occurs here. Instr-specific selection happens in spvSelect().
853 bool HasDefs = I.getNumDefs() > 0;
854 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
855 SPIRVTypeInst ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
856 assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
857 I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
858 if (spvSelect(ResVReg, ResType, I)) {
859 if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs).
860 for (unsigned i = 0; i < I.getNumDefs(); ++i)
861 MRI->setType(I.getOperand(i).getReg(), LLT::scalar(64));
862 GR.invalidateMachineInstr(&I);
863 I.eraseFromParent();
864 return true;
865 }
866 return false;
867}
868
869static bool mayApplyGenericSelection(unsigned Opcode) {
870 switch (Opcode) {
871 case TargetOpcode::G_CONSTANT:
872 case TargetOpcode::G_FCONSTANT:
873 return false;
874 case TargetOpcode::G_SADDO:
875 case TargetOpcode::G_SSUBO:
876 return true;
877 }
878 return isTypeFoldingSupported(Opcode);
879}
880
881bool SPIRVInstructionSelector::BuildCOPY(Register DestReg, Register SrcReg,
882 MachineInstr &I) const {
883 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DestReg);
884 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg);
885 if (DstRC != SrcRC && SrcRC)
886 MRI->setRegClass(DestReg, SrcRC);
887 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY))
888 .addDef(DestReg)
889 .addUse(SrcReg)
890 .constrainAllUses(TII, TRI, RBI);
891 return true;
892}
893
894bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
895 SPIRVTypeInst ResType,
896 MachineInstr &I) const {
897 const unsigned Opcode = I.getOpcode();
898 if (mayApplyGenericSelection(Opcode))
899 return selectImpl(I, *CoverageInfo);
900 switch (Opcode) {
901 case TargetOpcode::G_CONSTANT:
902 case TargetOpcode::G_FCONSTANT:
903 return selectConst(ResVReg, ResType, I);
904 case TargetOpcode::G_GLOBAL_VALUE:
905 return selectGlobalValue(ResVReg, I);
906 case TargetOpcode::G_IMPLICIT_DEF:
907 return selectOpUndef(ResVReg, ResType, I);
908 case TargetOpcode::G_FREEZE:
909 return selectFreeze(ResVReg, ResType, I);
910
911 case TargetOpcode::G_INTRINSIC:
912 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
913 case TargetOpcode::G_INTRINSIC_CONVERGENT:
914 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
915 return selectIntrinsic(ResVReg, ResType, I);
916 case TargetOpcode::G_BITREVERSE:
917 return selectBitreverse(ResVReg, ResType, I);
918
919 case TargetOpcode::G_BUILD_VECTOR:
920 return selectBuildVector(ResVReg, ResType, I);
921 case TargetOpcode::G_SPLAT_VECTOR:
922 return selectSplatVector(ResVReg, ResType, I);
923
924 case TargetOpcode::G_SHUFFLE_VECTOR: {
925 MachineBasicBlock &BB = *I.getParent();
926 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle))
927 .addDef(ResVReg)
928 .addUse(GR.getSPIRVTypeID(ResType))
929 .addUse(I.getOperand(1).getReg())
930 .addUse(I.getOperand(2).getReg());
931 for (auto V : I.getOperand(3).getShuffleMask())
932 MIB.addImm(V);
933 MIB.constrainAllUses(TII, TRI, RBI);
934 return true;
935 }
936 case TargetOpcode::G_MEMMOVE:
937 case TargetOpcode::G_MEMCPY:
938 case TargetOpcode::G_MEMSET:
939 return selectMemOperation(ResVReg, I);
940
941 case TargetOpcode::G_ICMP:
942 return selectICmp(ResVReg, ResType, I);
943 case TargetOpcode::G_FCMP:
944 return selectFCmp(ResVReg, ResType, I);
945
946 case TargetOpcode::G_FRAME_INDEX:
947 return selectFrameIndex(ResVReg, ResType, I);
948
949 case TargetOpcode::G_LOAD:
950 return selectLoad(ResVReg, ResType, I);
951 case TargetOpcode::G_STORE:
952 return selectStore(I);
953
954 case TargetOpcode::G_BR:
955 return selectBranch(I);
956 case TargetOpcode::G_BRCOND:
957 return selectBranchCond(I);
958
959 case TargetOpcode::G_PHI:
960 return selectPhi(ResVReg, I);
961
962 case TargetOpcode::G_FPTOSI:
963 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
964 case TargetOpcode::G_FPTOUI:
965 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
966
967 case TargetOpcode::G_FPTOSI_SAT:
968 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
969 case TargetOpcode::G_FPTOUI_SAT:
970 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
971
972 case TargetOpcode::G_SITOFP:
973 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF);
974 case TargetOpcode::G_UITOFP:
975 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF);
976
977 case TargetOpcode::G_CTPOP:
978 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount);
979 case TargetOpcode::G_SMIN:
980 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin);
981 case TargetOpcode::G_UMIN:
982 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin);
983
984 case TargetOpcode::G_SMAX:
985 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax);
986 case TargetOpcode::G_UMAX:
987 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax);
988
989 case TargetOpcode::G_SCMP:
990 return selectSUCmp(ResVReg, ResType, I, true);
991 case TargetOpcode::G_UCMP:
992 return selectSUCmp(ResVReg, ResType, I, false);
993 case TargetOpcode::G_LROUND:
994 case TargetOpcode::G_LLROUND: {
995 Register regForLround =
996 MRI->createVirtualRegister(MRI->getRegClass(ResVReg), "lround");
997 MRI->setRegClass(regForLround, &SPIRV::iIDRegClass);
998 GR.assignSPIRVTypeToVReg(GR.getSPIRVTypeForVReg(I.getOperand(1).getReg()),
999 regForLround, *(I.getParent()->getParent()));
1000 selectExtInst(regForLround, GR.getSPIRVTypeForVReg(regForLround), I,
1001 CL::round, GL::Round, /* setMIFlags */ false);
1002 MachineBasicBlock &BB = *I.getParent();
1003 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConvertFToS))
1004 .addDef(ResVReg)
1005 .addUse(GR.getSPIRVTypeID(ResType))
1006 .addUse(regForLround);
1007 MIB.constrainAllUses(TII, TRI, RBI);
1008 return true;
1009 }
1010 case TargetOpcode::G_STRICT_FMA:
1011 case TargetOpcode::G_FMA: {
1012 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_fma)) {
1013 MachineBasicBlock &BB = *I.getParent();
1014 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpFmaKHR))
1015 .addDef(ResVReg)
1016 .addUse(GR.getSPIRVTypeID(ResType))
1017 .addUse(I.getOperand(1).getReg())
1018 .addUse(I.getOperand(2).getReg())
1019 .addUse(I.getOperand(3).getReg())
1020 .setMIFlags(I.getFlags());
1021 MIB.constrainAllUses(TII, TRI, RBI);
1022 return true;
1023 }
1024 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
1025 }
1026
1027 case TargetOpcode::G_STRICT_FLDEXP:
1028 return selectExtInst(ResVReg, ResType, I, CL::ldexp);
1029
1030 case TargetOpcode::G_FPOW:
1031 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow);
1032 case TargetOpcode::G_FPOWI:
1033 return selectExtInst(ResVReg, ResType, I, CL::pown);
1034
1035 case TargetOpcode::G_FEXP:
1036 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp);
1037 case TargetOpcode::G_FEXP2:
1038 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2);
1039 case TargetOpcode::G_FEXP10:
1040 return selectExp10(ResVReg, ResType, I);
1041
1042 case TargetOpcode::G_FMODF:
1043 return selectModf(ResVReg, ResType, I);
1044 case TargetOpcode::G_FSINCOS:
1045 return selectSincos(ResVReg, ResType, I);
1046
1047 case TargetOpcode::G_FLOG:
1048 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log);
1049 case TargetOpcode::G_FLOG2:
1050 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2);
1051 case TargetOpcode::G_FLOG10:
1052 return selectLog10(ResVReg, ResType, I);
1053
1054 case TargetOpcode::G_FABS:
1055 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs);
1056 case TargetOpcode::G_ABS:
1057 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs);
1058
1059 case TargetOpcode::G_FMINNUM:
1060 case TargetOpcode::G_FMINIMUM:
1061 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin);
1062 case TargetOpcode::G_FMAXNUM:
1063 case TargetOpcode::G_FMAXIMUM:
1064 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax);
1065
1066 case TargetOpcode::G_FCOPYSIGN:
1067 return selectExtInst(ResVReg, ResType, I, CL::copysign);
1068
1069 case TargetOpcode::G_FCEIL:
1070 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil);
1071 case TargetOpcode::G_FFLOOR:
1072 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor);
1073
1074 case TargetOpcode::G_FCOS:
1075 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos);
1076 case TargetOpcode::G_FSIN:
1077 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin);
1078 case TargetOpcode::G_FTAN:
1079 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan);
1080 case TargetOpcode::G_FACOS:
1081 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos);
1082 case TargetOpcode::G_FASIN:
1083 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin);
1084 case TargetOpcode::G_FATAN:
1085 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan);
1086 case TargetOpcode::G_FATAN2:
1087 return selectExtInst(ResVReg, ResType, I, CL::atan2, GL::Atan2);
1088 case TargetOpcode::G_FCOSH:
1089 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh);
1090 case TargetOpcode::G_FSINH:
1091 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh);
1092 case TargetOpcode::G_FTANH:
1093 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh);
1094
1095 case TargetOpcode::G_STRICT_FSQRT:
1096 case TargetOpcode::G_FSQRT:
1097 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt);
1098
1099 case TargetOpcode::G_CTTZ:
1100 case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1101 return selectExtInst(ResVReg, ResType, I, CL::ctz);
1102 case TargetOpcode::G_CTLZ:
1103 case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1104 return selectExtInst(ResVReg, ResType, I, CL::clz);
1105
1106 case TargetOpcode::G_INTRINSIC_ROUND:
1107 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round);
1108 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
1109 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
1110 case TargetOpcode::G_INTRINSIC_TRUNC:
1111 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc);
1112 case TargetOpcode::G_FRINT:
1113 case TargetOpcode::G_FNEARBYINT:
1114 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
1115
1116 case TargetOpcode::G_SMULH:
1117 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi);
1118 case TargetOpcode::G_UMULH:
1119 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi);
1120
1121 case TargetOpcode::G_SADDSAT:
1122 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat);
1123 case TargetOpcode::G_UADDSAT:
1124 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat);
1125 case TargetOpcode::G_SSUBSAT:
1126 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat);
1127 case TargetOpcode::G_USUBSAT:
1128 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat);
1129
1130 case TargetOpcode::G_FFREXP:
1131 return selectFrexp(ResVReg, ResType, I);
1132
1133 case TargetOpcode::G_UADDO:
1134 return selectOverflowArith(ResVReg, ResType, I,
1135 ResType->getOpcode() == SPIRV::OpTypeVector
1136 ? SPIRV::OpIAddCarryV
1137 : SPIRV::OpIAddCarryS);
1138 case TargetOpcode::G_USUBO:
1139 return selectOverflowArith(ResVReg, ResType, I,
1140 ResType->getOpcode() == SPIRV::OpTypeVector
1141 ? SPIRV::OpISubBorrowV
1142 : SPIRV::OpISubBorrowS);
1143 case TargetOpcode::G_UMULO:
1144 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpUMulExtended);
1145 case TargetOpcode::G_SMULO:
1146 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpSMulExtended);
1147
1148 case TargetOpcode::G_SEXT:
1149 return selectExt(ResVReg, ResType, I, true);
1150 case TargetOpcode::G_ANYEXT:
1151 case TargetOpcode::G_ZEXT:
1152 return selectExt(ResVReg, ResType, I, false);
1153 case TargetOpcode::G_TRUNC:
1154 return selectTrunc(ResVReg, ResType, I);
1155 case TargetOpcode::G_FPTRUNC:
1156 case TargetOpcode::G_FPEXT:
1157 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert);
1158
1159 case TargetOpcode::G_PTRTOINT:
1160 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU);
1161 case TargetOpcode::G_INTTOPTR:
1162 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr);
1163 case TargetOpcode::G_BITCAST:
1164 return selectBitcast(ResVReg, ResType, I);
1165 case TargetOpcode::G_ADDRSPACE_CAST:
1166 return selectAddrSpaceCast(ResVReg, ResType, I);
1167 case TargetOpcode::G_PTR_ADD: {
1168 // Currently, we get G_PTR_ADD only applied to global variables.
1169 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg());
1170 Register GV = I.getOperand(1).getReg();
1171 MachineRegisterInfo::def_instr_iterator II = MRI->def_instr_begin(GV);
1172 (void)II;
1173 assert(((*II).getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
1174 (*II).getOpcode() == TargetOpcode::COPY ||
1175 (*II).getOpcode() == SPIRV::OpVariable) &&
1176 getImm(I.getOperand(2), MRI));
1177 // It may be the initialization of a global variable.
1178 bool IsGVInit = false;
1179 for (MachineRegisterInfo::use_instr_iterator
1180 UseIt = MRI->use_instr_begin(I.getOperand(0).getReg()),
1181 UseEnd = MRI->use_instr_end();
1182 UseIt != UseEnd; UseIt = std::next(UseIt)) {
1183 if ((*UseIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
1184 (*UseIt).getOpcode() == SPIRV::OpSpecConstantOp ||
1185 (*UseIt).getOpcode() == SPIRV::OpVariable) {
1186 IsGVInit = true;
1187 break;
1188 }
1189 }
1190 MachineBasicBlock &BB = *I.getParent();
1191 if (!IsGVInit) {
1192 SPIRVTypeInst GVType = GR.getSPIRVTypeForVReg(GV);
1193 SPIRVTypeInst GVPointeeType = GR.getPointeeType(GVType);
1194 SPIRVTypeInst ResPointeeType = GR.getPointeeType(ResType);
1195 if (GVPointeeType && ResPointeeType && GVPointeeType != ResPointeeType) {
1196 // Build a new virtual register that is associated with the required
1197 // data type.
1198 Register NewVReg = MRI->createGenericVirtualRegister(MRI->getType(GV));
1199 MRI->setRegClass(NewVReg, MRI->getRegClass(GV));
1200 // Having a correctly typed base we are ready to build the actually
1201 // required GEP. It may not be a constant though, because all Operands
1202 // of OpSpecConstantOp is to originate from other const instructions,
1203 // and only the AccessChain named opcodes accept a global OpVariable
1204 // instruction. We can't use an AccessChain opcode because of the type
1205 // mismatch between result and base types.
1206 if (!GR.isBitcastCompatible(ResType, GVType))
1207 report_fatal_error(
1208 "incompatible result and operand types in a bitcast");
1209 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
1210 MachineInstrBuilder MIB =
1211 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitcast))
1212 .addDef(NewVReg)
1213 .addUse(ResTypeReg)
1214 .addUse(GV);
1215 MIB.constrainAllUses(TII, TRI, RBI);
1216 BuildMI(BB, I, I.getDebugLoc(),
1217 TII.get(STI.isLogicalSPIRV() ? SPIRV::OpInBoundsAccessChain
1218 : SPIRV::OpInBoundsPtrAccessChain))
1219 .addDef(ResVReg)
1220 .addUse(ResTypeReg)
1221 .addUse(NewVReg)
1222 .addUse(I.getOperand(2).getReg())
1223 .constrainAllUses(TII, TRI, RBI);
1224 } else {
1225 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp))
1226 .addDef(ResVReg)
1227 .addUse(GR.getSPIRVTypeID(ResType))
1228 .addImm(
1229 static_cast<uint32_t>(SPIRV::Opcode::InBoundsPtrAccessChain))
1230 .addUse(GV)
1231 .addUse(I.getOperand(2).getReg())
1232 .constrainAllUses(TII, TRI, RBI);
1233 }
1234 return true;
1235 }
1236 // It's possible to translate G_PTR_ADD to OpSpecConstantOp: either to
1237 // initialize a global variable with a constant expression (e.g., the test
1238 // case opencl/basic/progvar_prog_scope_init.ll), or for another use case
1239 Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I);
1240 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp))
1241 .addDef(ResVReg)
1242 .addUse(GR.getSPIRVTypeID(ResType))
1243 .addImm(static_cast<uint32_t>(
1244 SPIRV::Opcode::InBoundsPtrAccessChain))
1245 .addUse(GV)
1246 .addUse(Idx)
1247 .addUse(I.getOperand(2).getReg());
1248 MIB.constrainAllUses(TII, TRI, RBI);
1249 return true;
1250 }
1251
1252 case TargetOpcode::G_ATOMICRMW_OR:
1253 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr);
1254 case TargetOpcode::G_ATOMICRMW_ADD:
1255 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd);
1256 case TargetOpcode::G_ATOMICRMW_AND:
1257 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd);
1258 case TargetOpcode::G_ATOMICRMW_MAX:
1259 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax);
1260 case TargetOpcode::G_ATOMICRMW_MIN:
1261 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin);
1262 case TargetOpcode::G_ATOMICRMW_SUB:
1263 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub);
1264 case TargetOpcode::G_ATOMICRMW_XOR:
1265 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor);
1266 case TargetOpcode::G_ATOMICRMW_UMAX:
1267 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax);
1268 case TargetOpcode::G_ATOMICRMW_UMIN:
1269 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin);
1270 case TargetOpcode::G_ATOMICRMW_XCHG:
1271 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange);
1272 case TargetOpcode::G_ATOMIC_CMPXCHG:
1273 return selectAtomicCmpXchg(ResVReg, ResType, I);
1274
1275 case TargetOpcode::G_ATOMICRMW_FADD:
1276 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT);
1277 case TargetOpcode::G_ATOMICRMW_FSUB:
1278 // Translate G_ATOMICRMW_FSUB to OpAtomicFAddEXT with negative value operand
1279 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT,
1280 ResType->getOpcode() == SPIRV::OpTypeVector
1281 ? SPIRV::OpFNegateV
1282 : SPIRV::OpFNegate);
1283 case TargetOpcode::G_ATOMICRMW_FMIN:
1284 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT);
1285 case TargetOpcode::G_ATOMICRMW_FMAX:
1286 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT);
1287
1288 case TargetOpcode::G_FENCE:
1289 return selectFence(I);
1290
1291 case TargetOpcode::G_STACKSAVE:
1292 return selectStackSave(ResVReg, ResType, I);
1293 case TargetOpcode::G_STACKRESTORE:
1294 return selectStackRestore(I);
1295
1296 case TargetOpcode::G_UNMERGE_VALUES:
1297 return selectUnmergeValues(I);
1298
1299 // Discard gen opcodes for intrinsics which we do not expect to actually
1300 // represent code after lowering or intrinsics which are not implemented but
1301 // should not crash when found in a customer's LLVM IR input.
1302 case TargetOpcode::G_TRAP:
1303 case TargetOpcode::G_UBSANTRAP:
1304 case TargetOpcode::DBG_LABEL:
1305 return true;
1306 case TargetOpcode::G_DEBUGTRAP:
1307 return selectDebugTrap(ResVReg, ResType, I);
1308
1309 default:
1310 return false;
1311 }
1312}
1313
1314bool SPIRVInstructionSelector::selectDebugTrap(Register ResVReg,
1315 SPIRVTypeInst ResType,
1316 MachineInstr &I) const {
1317 unsigned Opcode = SPIRV::OpNop;
1318 MachineBasicBlock &BB = *I.getParent();
1319 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
1320 .constrainAllUses(TII, TRI, RBI);
1321 return true;
1322}
1323
1324bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1325 SPIRVTypeInst ResType,
1326 MachineInstr &I,
1327 GL::GLSLExtInst GLInst,
1328 bool setMIFlags, bool useMISrc,
1329 ArrayRef<Register> SrcRegs) const {
1330 if (!STI.canUseExtInstSet(
1331 SPIRV::InstructionSet::InstructionSet::GLSL_std_450)) {
1332 std::string DiagMsg;
1333 raw_string_ostream OS(DiagMsg);
1334 I.print(OS, true, false, false, false);
1335 DiagMsg += " is only supported with the GLSL extended instruction set.\n";
1336 report_fatal_error(DiagMsg.c_str(), false);
1337 }
1338 return selectExtInst(ResVReg, ResType, I,
1339 {{SPIRV::InstructionSet::GLSL_std_450, GLInst}},
1340 setMIFlags, useMISrc, SrcRegs);
1341}
1342
1343bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1344 SPIRVTypeInst ResType,
1345 MachineInstr &I,
1346 CL::OpenCLExtInst CLInst,
1347 bool setMIFlags, bool useMISrc,
1348 ArrayRef<Register> SrcRegs) const {
1349 return selectExtInst(ResVReg, ResType, I,
1350 {{SPIRV::InstructionSet::OpenCL_std, CLInst}},
1351 setMIFlags, useMISrc, SrcRegs);
1352}
1353
1354bool SPIRVInstructionSelector::selectExtInst(
1355 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
1356 CL::OpenCLExtInst CLInst, GL::GLSLExtInst GLInst, bool setMIFlags,
1357 bool useMISrc, ArrayRef<Register> SrcRegs) const {
1358 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst},
1359 {SPIRV::InstructionSet::GLSL_std_450, GLInst}};
1360 return selectExtInst(ResVReg, ResType, I, ExtInsts, setMIFlags, useMISrc,
1361 SrcRegs);
1362}
1363
1364bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
1365 SPIRVTypeInst ResType,
1366 MachineInstr &I,
1367 const ExtInstList &Insts,
1368 bool setMIFlags, bool useMISrc,
1369 ArrayRef<Register> SrcRegs) const {
1370
1371 for (const auto &[InstructionSet, Opcode] : Insts) {
1372 if (!STI.canUseExtInstSet(InstructionSet))
1373 continue;
1374 MachineBasicBlock &BB = *I.getParent();
1375 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1376 .addDef(ResVReg)
1377 .addUse(GR.getSPIRVTypeID(ResType))
1378 .addImm(static_cast<uint32_t>(InstructionSet))
1379 .addImm(Opcode);
1380 if (setMIFlags)
1381 MIB.setMIFlags(I.getFlags());
1382 if (useMISrc) {
1383 const unsigned NumOps = I.getNumOperands();
1384 unsigned Index = 1;
1385 if (Index < NumOps &&
1386 I.getOperand(Index).getType() ==
1387 MachineOperand::MachineOperandType::MO_IntrinsicID)
1388 Index = 2;
1389 for (; Index < NumOps; ++Index)
1390 MIB.add(I.getOperand(Index));
1391 } else {
1392 for (Register SReg : SrcRegs) {
1393 MIB.addUse(SReg);
1394 }
1395 }
1396 MIB.constrainAllUses(TII, TRI, RBI);
1397 return true;
1398 }
1399 return false;
1400}
1401
1402bool SPIRVInstructionSelector::selectFrexp(Register ResVReg,
1403 SPIRVTypeInst ResType,
1404 MachineInstr &I) const {
1405 ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CL::frexp},
1406 {SPIRV::InstructionSet::GLSL_std_450, GL::Frexp}};
1407 for (const auto &Ex : ExtInsts) {
1408 SPIRV::InstructionSet::InstructionSet Set = Ex.first;
1409 uint32_t Opcode = Ex.second;
1410 if (!STI.canUseExtInstSet(Set))
1411 continue;
1412
1413 MachineIRBuilder MIRBuilder(I);
1414 SPIRVTypeInst PointeeTy = GR.getSPIRVTypeForVReg(I.getOperand(1).getReg());
1415 const SPIRVTypeInst PointerType = GR.getOrCreateSPIRVPointerType(
1416 PointeeTy, MIRBuilder, SPIRV::StorageClass::Function);
1417 Register PointerVReg =
1418 createVirtualRegister(PointerType, &GR, MRI, MRI->getMF());
1419
1420 auto It = getOpVariableMBBIt(I);
1421 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
1422 .addDef(PointerVReg)
1423 .addUse(GR.getSPIRVTypeID(PointerType))
1424 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
1425 .constrainAllUses(TII, TRI, RBI);
1426
1427 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1428 .addDef(ResVReg)
1429 .addUse(GR.getSPIRVTypeID(ResType))
1430 .addImm(static_cast<uint32_t>(Ex.first))
1431 .addImm(Opcode)
1432 .add(I.getOperand(2))
1433 .addUse(PointerVReg)
1434 .constrainAllUses(TII, TRI, RBI);
1435
1436 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1437 .addDef(I.getOperand(1).getReg())
1438 .addUse(GR.getSPIRVTypeID(PointeeTy))
1439 .addUse(PointerVReg)
1440 .constrainAllUses(TII, TRI, RBI);
1441 return true;
1442 }
1443 return false;
1444}
1445
1446bool SPIRVInstructionSelector::selectSincos(Register ResVReg,
1447 SPIRVTypeInst ResType,
1448 MachineInstr &I) const {
1449 Register CosResVReg = I.getOperand(1).getReg();
1450 unsigned SrcIdx = I.getNumExplicitDefs();
1451 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
1452
1453 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
1454 // OpenCL.std sincos(x, cosval*) -> returns sin(x), writes cos(x) to ptr.
1455 MachineIRBuilder MIRBuilder(I);
1456 const SPIRVTypeInst PointerType = GR.getOrCreateSPIRVPointerType(
1457 ResType, MIRBuilder, SPIRV::StorageClass::Function);
1458 Register PointerVReg =
1459 createVirtualRegister(PointerType, &GR, MRI, MRI->getMF());
1460
1461 auto It = getOpVariableMBBIt(I);
1462 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
1463 .addDef(PointerVReg)
1464 .addUse(GR.getSPIRVTypeID(PointerType))
1465 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
1466 .constrainAllUses(TII, TRI, RBI);
1467 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1468 .addDef(ResVReg)
1469 .addUse(ResTypeReg)
1470 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
1471 .addImm(CL::sincos)
1472 .add(I.getOperand(SrcIdx))
1473 .addUse(PointerVReg)
1474 .constrainAllUses(TII, TRI, RBI);
1475 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1476 .addDef(CosResVReg)
1477 .addUse(ResTypeReg)
1478 .addUse(PointerVReg)
1479 .constrainAllUses(TII, TRI, RBI);
1480 return true;
1481 } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
1482 // GLSL.std.450 has no combined sincos; emit separate Sin and Cos.
1483 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1484 .addDef(ResVReg)
1485 .addUse(ResTypeReg)
1486 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1487 .addImm(GL::Sin)
1488 .add(I.getOperand(SrcIdx))
1489 .constrainAllUses(TII, TRI, RBI);
1490 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1491 .addDef(CosResVReg)
1492 .addUse(ResTypeReg)
1493 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1494 .addImm(GL::Cos)
1495 .add(I.getOperand(SrcIdx))
1496 .constrainAllUses(TII, TRI, RBI);
1497 return true;
1498 }
1499 return false;
1500}
1501
1502bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
1503 SPIRVTypeInst ResType,
1504 MachineInstr &I,
1505 std::vector<Register> Srcs,
1506 unsigned Opcode) const {
1507 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
1508 .addDef(ResVReg)
1509 .addUse(GR.getSPIRVTypeID(ResType));
1510 for (Register SReg : Srcs) {
1511 MIB.addUse(SReg);
1512 }
1513 MIB.constrainAllUses(TII, TRI, RBI);
1514 return true;
1515}
1516
1517bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
1518 SPIRVTypeInst ResType,
1519 MachineInstr &I,
1520 unsigned Opcode) const {
1521 if (STI.isPhysicalSPIRV() && I.getOperand(1).isReg()) {
1522 Register SrcReg = I.getOperand(1).getReg();
1523 bool IsGV = false;
1524 for (MachineRegisterInfo::def_instr_iterator DefIt =
1525 MRI->def_instr_begin(SrcReg);
1526 DefIt != MRI->def_instr_end(); DefIt = std::next(DefIt)) {
1527 unsigned DefOpCode = DefIt->getOpcode();
1528 if (DefOpCode == SPIRV::ASSIGN_TYPE || DefOpCode == TargetOpcode::COPY) {
1529 // We need special handling to look through the type assignment or the
1530 // COPY pseudo-op and see if this is a constant or a global.
1531 if (auto *VRD = getVRegDef(*MRI, DefIt->getOperand(1).getReg()))
1532 DefOpCode = VRD->getOpcode();
1533 }
1534 if (DefOpCode == TargetOpcode::G_GLOBAL_VALUE ||
1535 DefOpCode == TargetOpcode::G_CONSTANT ||
1536 DefOpCode == SPIRV::OpVariable || DefOpCode == SPIRV::OpConstantI) {
1537 IsGV = true;
1538 break;
1539 }
1540 }
1541 if (IsGV) {
1542 uint32_t SpecOpcode = 0;
1543 switch (Opcode) {
1544 case SPIRV::OpConvertPtrToU:
1545 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertPtrToU);
1546 break;
1547 case SPIRV::OpConvertUToPtr:
1548 SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::ConvertUToPtr);
1549 break;
1550 }
1551 if (SpecOpcode) {
1552 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1553 TII.get(SPIRV::OpSpecConstantOp))
1554 .addDef(ResVReg)
1555 .addUse(GR.getSPIRVTypeID(ResType))
1556 .addImm(SpecOpcode)
1557 .addUse(SrcReg)
1558 .constrainAllUses(TII, TRI, RBI);
1559 return true;
1560 }
1561 }
1562 }
1563 return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()},
1564 Opcode);
1565}
1566
1567bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
1568 SPIRVTypeInst ResType,
1569 MachineInstr &I) const {
1570 Register OpReg = I.getOperand(1).getReg();
1571 SPIRVTypeInst OpType =
1572 OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr;
1573 if (!GR.isBitcastCompatible(ResType, OpType))
1574 report_fatal_error("incompatible result and operand types in a bitcast");
1575 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast);
1576}
1577
1578static void addMemoryOperands(MachineMemOperand *MemOp,
1579 MachineInstrBuilder &MIB,
1580 MachineIRBuilder &MIRBuilder,
1581 SPIRVGlobalRegistry &GR) {
1582 const SPIRVSubtarget *ST =
1583 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
1584 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
1585 if (MemOp->isVolatile())
1586 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
1587 if (MemOp->isNonTemporal())
1588 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal);
1589 // Aligned memory operand requires the Kernel capability.
1590 if (!ST->isShader() && MemOp->getAlign().value())
1591 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned);
1592
1593 [[maybe_unused]] MachineInstr *AliasList = nullptr;
1594 [[maybe_unused]] MachineInstr *NoAliasList = nullptr;
1595 if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
1596 if (auto *MD = MemOp->getAAInfo().Scope) {
1597 AliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1598 if (AliasList)
1599 SpvMemOp |=
1600 static_cast<uint32_t>(SPIRV::MemoryOperand::AliasScopeINTELMask);
1601 }
1602 if (auto *MD = MemOp->getAAInfo().NoAlias) {
1603 NoAliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1604 if (NoAliasList)
1605 SpvMemOp |=
1606 static_cast<uint32_t>(SPIRV::MemoryOperand::NoAliasINTELMask);
1607 }
1608 }
1609
1610 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) {
1611 MIB.addImm(SpvMemOp);
1612 if (SpvMemOp & static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned))
1613 MIB.addImm(MemOp->getAlign().value());
1614 if (AliasList)
1615 MIB.addUse(AliasList->getOperand(0).getReg());
1616 if (NoAliasList)
1617 MIB.addUse(NoAliasList->getOperand(0).getReg());
1618 }
1619}
1620
1621static void addMemoryOperands(uint64_t Flags, MachineInstrBuilder &MIB) {
1622 uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
1623 if (Flags & MachineMemOperand::Flags::MOVolatile)
1624 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
1625 if (Flags & MachineMemOperand::Flags::MONonTemporal)
1626 SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Nontemporal);
1627
1628 if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None))
1629 MIB.addImm(SpvMemOp);
1630}
1631
1632bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
1633 SPIRVTypeInst ResType,
1634 MachineInstr &I) const {
1635 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0;
1636 Register Ptr = I.getOperand(1 + OpOffset).getReg();
1637
1638 auto *PtrDef = getVRegDef(*MRI, Ptr);
1639 auto *IntPtrDef = dyn_cast<GIntrinsic>(PtrDef);
1640 if (IntPtrDef &&
1641 IntPtrDef->getIntrinsicID() == Intrinsic::spv_resource_getpointer) {
1642 Register HandleReg = IntPtrDef->getOperand(2).getReg();
1643 SPIRVTypeInst HandleType = GR.getSPIRVTypeForVReg(HandleReg);
1644 if (HandleType->getOpcode() == SPIRV::OpTypeImage) {
1645 Register NewHandleReg =
1646 MRI->createVirtualRegister(MRI->getRegClass(HandleReg));
1647 auto *HandleDef = cast<GIntrinsic>(getVRegDef(*MRI, HandleReg));
1648 if (!loadHandleBeforePosition(NewHandleReg, HandleType, *HandleDef, I)) {
1649 return false;
1650 }
1651
1652 Register IdxReg = IntPtrDef->getOperand(3).getReg();
1653 return generateImageReadOrFetch(ResVReg, ResType, NewHandleReg, IdxReg,
1654 I.getDebugLoc(), I);
1655 }
1656 }
1657
1658 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
1659 .addDef(ResVReg)
1660 .addUse(GR.getSPIRVTypeID(ResType))
1661 .addUse(Ptr);
1662 if (!I.getNumMemOperands()) {
1663 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
1664 I.getOpcode() ==
1665 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
1666 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
1667 } else {
1668 MachineIRBuilder MIRBuilder(I);
1669 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1670 }
1671 MIB.constrainAllUses(TII, TRI, RBI);
1672 return true;
1673}
1674
1675bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
1676 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0;
1677 Register StoreVal = I.getOperand(0 + OpOffset).getReg();
1678 Register Ptr = I.getOperand(1 + OpOffset).getReg();
1679
1680 auto *PtrDef = getVRegDef(*MRI, Ptr);
1681 auto *IntPtrDef = dyn_cast<GIntrinsic>(PtrDef);
1682 if (IntPtrDef &&
1683 IntPtrDef->getIntrinsicID() == Intrinsic::spv_resource_getpointer) {
1684 Register HandleReg = IntPtrDef->getOperand(2).getReg();
1685 Register NewHandleReg =
1686 MRI->createVirtualRegister(MRI->getRegClass(HandleReg));
1687 auto *HandleDef = cast<GIntrinsic>(getVRegDef(*MRI, HandleReg));
1688 SPIRVTypeInst HandleType = GR.getSPIRVTypeForVReg(HandleReg);
1689 if (!loadHandleBeforePosition(NewHandleReg, HandleType, *HandleDef, I)) {
1690 return false;
1691 }
1692
1693 Register IdxReg = IntPtrDef->getOperand(3).getReg();
1694 if (HandleType->getOpcode() == SPIRV::OpTypeImage) {
1695 auto BMI = BuildMI(*I.getParent(), I, I.getDebugLoc(),
1696 TII.get(SPIRV::OpImageWrite))
1697 .addUse(NewHandleReg)
1698 .addUse(IdxReg)
1699 .addUse(StoreVal);
1700
1701 const llvm::Type *LLVMHandleType = GR.getTypeForSPIRVType(HandleType);
1702 if (sampledTypeIsSignedInteger(LLVMHandleType))
1703 BMI.addImm(0x1000); // SignExtend
1704
1705 BMI.constrainAllUses(TII, TRI, RBI);
1706 return true;
1707 }
1708 }
1709
1710 MachineBasicBlock &BB = *I.getParent();
1711 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpStore))
1712 .addUse(Ptr)
1713 .addUse(StoreVal);
1714 if (!I.getNumMemOperands()) {
1715 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
1716 I.getOpcode() ==
1717 TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
1718 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
1719 } else {
1720 MachineIRBuilder MIRBuilder(I);
1721 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1722 }
1723 MIB.constrainAllUses(TII, TRI, RBI);
1724 return true;
1725}
1726
1727bool SPIRVInstructionSelector::selectStackSave(Register ResVReg,
1728 SPIRVTypeInst ResType,
1729 MachineInstr &I) const {
1730 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array))
1731 report_fatal_error(
1732 "llvm.stacksave intrinsic: this instruction requires the following "
1733 "SPIR-V extension: SPV_INTEL_variable_length_array",
1734 false);
1735 MachineBasicBlock &BB = *I.getParent();
1736 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL))
1737 .addDef(ResVReg)
1738 .addUse(GR.getSPIRVTypeID(ResType))
1739 .constrainAllUses(TII, TRI, RBI);
1740 return true;
1741}
1742
1743bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const {
1744 if (!STI.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array))
1745 report_fatal_error(
1746 "llvm.stackrestore intrinsic: this instruction requires the following "
1747 "SPIR-V extension: SPV_INTEL_variable_length_array",
1748 false);
1749 if (!I.getOperand(0).isReg())
1750 return false;
1751 MachineBasicBlock &BB = *I.getParent();
1752 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL))
1753 .addUse(I.getOperand(0).getReg())
1754 .constrainAllUses(TII, TRI, RBI);
1755 return true;
1756}
1757
1758Register
1759SPIRVInstructionSelector::getOrCreateMemSetGlobal(MachineInstr &I) const {
1760 MachineIRBuilder MIRBuilder(I);
1761 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg());
1762
1763 // TODO: check if we have such GV, add init, use buildGlobalVariable.
1764 unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI);
1765 Function &CurFunction = GR.CurMF->getFunction();
1766 Type *LLVMArrTy =
1767 ArrayType::get(IntegerType::get(CurFunction.getContext(), 8), Num);
1768 GlobalVariable *GV = new GlobalVariable(*CurFunction.getParent(), LLVMArrTy,
1769 true, GlobalValue::InternalLinkage,
1770 Constant::getNullValue(LLVMArrTy));
1771
1772 Type *ValTy = Type::getInt8Ty(I.getMF()->getFunction().getContext());
1773 Type *ArrTy = ArrayType::get(ValTy, Num);
1774 SPIRVTypeInst VarTy = GR.getOrCreateSPIRVPointerType(
1775 ArrTy, MIRBuilder, SPIRV::StorageClass::UniformConstant);
1776
1777 SPIRVTypeInst SpvArrTy = GR.getOrCreateSPIRVType(
1778 ArrTy, MIRBuilder, SPIRV::AccessQualifier::None, false);
1779
1780 unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI);
1781 Register Const = GR.getOrCreateConstIntArray(Val, Num, I, SpvArrTy, TII);
1782
1783 Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
1784 auto MIBVar =
1785 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable))
1786 .addDef(VarReg)
1787 .addUse(GR.getSPIRVTypeID(VarTy))
1788 .addImm(SPIRV::StorageClass::UniformConstant)
1789 .addUse(Const);
1790 MIBVar.constrainAllUses(TII, TRI, RBI);
1791
1792 GR.add(GV, MIBVar);
1793 GR.addGlobalObject(GV, GR.CurMF, VarReg);
1794
1795 buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {});
1796 return VarReg;
1797}
1798
1799bool SPIRVInstructionSelector::selectCopyMemory(MachineInstr &I,
1800 Register SrcReg) const {
1801 MachineBasicBlock &BB = *I.getParent();
1802 Register DstReg = I.getOperand(0).getReg();
1803 SPIRVTypeInst DstTy = GR.getSPIRVTypeForVReg(DstReg);
1804 SPIRVTypeInst SrcTy = GR.getSPIRVTypeForVReg(SrcReg);
1805 if (GR.getPointeeType(DstTy) != GR.getPointeeType(SrcTy))
1806 report_fatal_error("OpCopyMemory requires operands to have the same type");
1807 uint64_t CopySize = getIConstVal(I.getOperand(2).getReg(), MRI);
1808 SPIRVTypeInst PointeeTy = GR.getPointeeType(DstTy);
1809 const Type *LLVMPointeeTy = GR.getTypeForSPIRVType(PointeeTy);
1810 if (!LLVMPointeeTy)
1811 report_fatal_error(
1812 "Unable to determine pointee type size for OpCopyMemory");
1813 const DataLayout &DL = I.getMF()->getFunction().getDataLayout();
1814 if (CopySize != DL.getTypeStoreSize(const_cast<Type *>(LLVMPointeeTy)))
1815 report_fatal_error(
1816 "OpCopyMemory requires the size to match the pointee type size");
1817 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemory))
1818 .addUse(DstReg)
1819 .addUse(SrcReg);
1820 if (I.getNumMemOperands()) {
1821 MachineIRBuilder MIRBuilder(I);
1822 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1823 }
1824 MIB.constrainAllUses(TII, TRI, RBI);
1825 return true;
1826}
1827
1828bool SPIRVInstructionSelector::selectCopyMemorySized(MachineInstr &I,
1829 Register SrcReg) const {
1830 MachineBasicBlock &BB = *I.getParent();
1831 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized))
1832 .addUse(I.getOperand(0).getReg())
1833 .addUse(SrcReg)
1834 .addUse(I.getOperand(2).getReg());
1835 if (I.getNumMemOperands()) {
1836 MachineIRBuilder MIRBuilder(I);
1837 addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
1838 }
1839 MIB.constrainAllUses(TII, TRI, RBI);
1840 return true;
1841}
1842
1843bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
1844 MachineInstr &I) const {
1845 Register SrcReg = I.getOperand(1).getReg();
1846 if (I.getOpcode() == TargetOpcode::G_MEMSET) {
1847 Register VarReg = getOrCreateMemSetGlobal(I);
1848 if (!VarReg.isValid())
1849 return false;
1850 Type *ValTy = Type::getInt8Ty(I.getMF()->getFunction().getContext());
1851 SPIRVTypeInst SourceTy = GR.getOrCreateSPIRVPointerType(
1852 ValTy, I, SPIRV::StorageClass::UniformConstant);
1853 SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
1854 if (!selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast))
1855 return false;
1856 }
1857 if (STI.isLogicalSPIRV()) {
1858 if (!selectCopyMemory(I, SrcReg))
1859 return false;
1860 } else {
1861 if (!selectCopyMemorySized(I, SrcReg))
1862 return false;
1863 }
1864 if (ResVReg.isValid() && ResVReg != I.getOperand(0).getReg())
1865 if (!BuildCOPY(ResVReg, I.getOperand(0).getReg(), I))
1866 return false;
1867 return true;
1868}
1869
1870bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
1871 SPIRVTypeInst ResType,
1872 MachineInstr &I,
1873 unsigned NewOpcode,
1874 unsigned NegateOpcode) const {
1875 assert(I.hasOneMemOperand());
1876 const MachineMemOperand *MemOp = *I.memoperands_begin();
1877 uint32_t Scope = static_cast<uint32_t>(getMemScope(
1878 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID()));
1879 Register ScopeReg = buildI32Constant(Scope, I);
1880
1881 Register Ptr = I.getOperand(1).getReg();
1882 // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll
1883 // auto ScSem =
1884 // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr));
1885 AtomicOrdering AO = MemOp->getSuccessOrdering();
1886 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO));
1887 Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I);
1888
1889 Register ValueReg = I.getOperand(2).getReg();
1890 if (NegateOpcode != 0) {
1891 // Translation with negative value operand is requested
1892 Register TmpReg = createVirtualRegister(ResType, &GR, MRI, MRI->getMF());
1893 if (!selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode))
1894 return false;
1895 ValueReg = TmpReg;
1896 }
1897
1898 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode))
1899 .addDef(ResVReg)
1900 .addUse(GR.getSPIRVTypeID(ResType))
1901 .addUse(Ptr)
1902 .addUse(ScopeReg)
1903 .addUse(MemSemReg)
1904 .addUse(ValueReg)
1905 .constrainAllUses(TII, TRI, RBI);
1906 return true;
1907}
1908
1909bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const {
1910 unsigned ArgI = I.getNumOperands() - 1;
1911 Register SrcReg =
1912 I.getOperand(ArgI).isReg() ? I.getOperand(ArgI).getReg() : Register(0);
1913 SPIRVTypeInst SrcType =
1914 SrcReg.isValid() ? GR.getSPIRVTypeForVReg(SrcReg) : nullptr;
1915 if (!SrcType || SrcType->getOpcode() != SPIRV::OpTypeVector)
1916 report_fatal_error(
1917 "cannot select G_UNMERGE_VALUES with a non-vector argument");
1918
1919 SPIRVTypeInst ScalarType =
1920 GR.getSPIRVTypeForVReg(SrcType->getOperand(1).getReg());
1921 MachineBasicBlock &BB = *I.getParent();
1922 unsigned CurrentIndex = 0;
1923 for (unsigned i = 0; i < I.getNumDefs(); ++i) {
1924 Register ResVReg = I.getOperand(i).getReg();
1925 SPIRVTypeInst ResType = GR.getSPIRVTypeForVReg(ResVReg);
1926 if (!ResType) {
1927 LLT ResLLT = MRI->getType(ResVReg);
1928 assert(ResLLT.isValid());
1929 if (ResLLT.isVector()) {
1930 ResType = GR.getOrCreateSPIRVVectorType(
1931 ScalarType, ResLLT.getNumElements(), I, TII);
1932 } else {
1933 ResType = ScalarType;
1934 }
1935 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
1936 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
1937 }
1938
1939 if (ResType->getOpcode() == SPIRV::OpTypeVector) {
1940 Register UndefReg = GR.getOrCreateUndef(I, SrcType, TII);
1941 auto MIB =
1942 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle))
1943 .addDef(ResVReg)
1944 .addUse(GR.getSPIRVTypeID(ResType))
1945 .addUse(SrcReg)
1946 .addUse(UndefReg);
1947 unsigned NumElements = GR.getScalarOrVectorComponentCount(ResType);
1948 for (unsigned j = 0; j < NumElements; ++j) {
1949 MIB.addImm(CurrentIndex + j);
1950 }
1951 CurrentIndex += NumElements;
1952 MIB.constrainAllUses(TII, TRI, RBI);
1953 } else {
1954 auto MIB =
1955 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
1956 .addDef(ResVReg)
1957 .addUse(GR.getSPIRVTypeID(ResType))
1958 .addUse(SrcReg)
1959 .addImm(CurrentIndex);
1960 CurrentIndex++;
1961 MIB.constrainAllUses(TII, TRI, RBI);
1962 }
1963 }
1964 return true;
1965}
1966
1967bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const {
1968 AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm());
1969 uint32_t MemSem = static_cast<uint32_t>(getMemSemantics(AO));
1970 Register MemSemReg = buildI32Constant(MemSem, I);
1971 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm());
1972 uint32_t Scope = static_cast<uint32_t>(
1973 getMemScope(GR.CurMF->getFunction().getContext(), Ord));
1974 Register ScopeReg = buildI32Constant(Scope, I);
1975 MachineBasicBlock &BB = *I.getParent();
1976 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier))
1977 .addUse(ScopeReg)
1978 .addUse(MemSemReg)
1979 .constrainAllUses(TII, TRI, RBI);
1980 return true;
1981}
1982
1983bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg,
1984 SPIRVTypeInst ResType,
1985 MachineInstr &I,
1986 unsigned Opcode) const {
1987 Type *ResTy = nullptr;
1988 StringRef ResName;
1989 if (!GR.findValueAttrs(&I, ResTy, ResName))
1990 report_fatal_error(
1991 "Not enough info to select the arithmetic with overflow instruction");
1992 if (!ResTy || !ResTy->isStructTy())
1993 report_fatal_error("Expect struct type result for the arithmetic "
1994 "with overflow instruction");
1995 // "Result Type must be from OpTypeStruct. The struct must have two members,
1996 // and the two members must be the same type."
1997 Type *ResElemTy = cast<StructType>(ResTy)->getElementType(0);
1998 ResTy = StructType::get(ResElemTy, ResElemTy);
1999 // Build SPIR-V types and constant(s) if needed.
2000 MachineIRBuilder MIRBuilder(I);
2001 SPIRVTypeInst StructType = GR.getOrCreateSPIRVType(
2002 ResTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
2003 assert(I.getNumDefs() > 1 && "Not enought operands");
2004 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
2005 unsigned N = GR.getScalarOrVectorComponentCount(ResType);
2006 if (N > 1)
2007 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
2008 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
2009 Register ZeroReg = buildZerosVal(ResType, I);
2010 // A new virtual register to store the result struct.
2011 Register StructVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
2012 MRI->setRegClass(StructVReg, &SPIRV::IDRegClass);
2013 // Build the result name if needed.
2014 if (ResName.size() > 0)
2015 buildOpName(StructVReg, ResName, MIRBuilder);
2016 // Build the arithmetic with overflow instruction.
2017 MachineBasicBlock &BB = *I.getParent();
2018 auto MIB =
2019 BuildMI(BB, MIRBuilder.getInsertPt(), I.getDebugLoc(), TII.get(Opcode))
2020 .addDef(StructVReg)
2021 .addUse(GR.getSPIRVTypeID(StructType));
2022 for (unsigned i = I.getNumDefs(); i < I.getNumOperands(); ++i)
2023 MIB.addUse(I.getOperand(i).getReg());
2024 MIB.constrainAllUses(TII, TRI, RBI);
2025 // Build instructions to extract fields of the instruction's result.
2026 // A new virtual register to store the higher part of the result struct.
2027 Register HigherVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
2028 MRI->setRegClass(HigherVReg, &SPIRV::iIDRegClass);
2029 for (unsigned i = 0; i < I.getNumDefs(); ++i) {
2030 auto MIB =
2031 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2032 .addDef(i == 1 ? HigherVReg : I.getOperand(i).getReg())
2033 .addUse(GR.getSPIRVTypeID(ResType))
2034 .addUse(StructVReg)
2035 .addImm(i);
2036 MIB.constrainAllUses(TII, TRI, RBI);
2037 }
2038 // Build boolean value from the higher part.
2039 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual))
2040 .addDef(I.getOperand(1).getReg())
2041 .addUse(BoolTypeReg)
2042 .addUse(HigherVReg)
2043 .addUse(ZeroReg)
2044 .constrainAllUses(TII, TRI, RBI);
2045 return true;
2046}
2047
2048bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
2049 SPIRVTypeInst ResType,
2050 MachineInstr &I) const {
2051 Register ScopeReg;
2052 Register MemSemEqReg;
2053 Register MemSemNeqReg;
2054 Register Ptr = I.getOperand(2).getReg();
2055 if (!isa<GIntrinsic>(I)) {
2056 assert(I.hasOneMemOperand());
2057 const MachineMemOperand *MemOp = *I.memoperands_begin();
2058 unsigned Scope = static_cast<uint32_t>(getMemScope(
2059 GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID()));
2060 ScopeReg = buildI32Constant(Scope, I);
2061
2062 unsigned ScSem = static_cast<uint32_t>(
2063 getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)));
2064 AtomicOrdering AO = MemOp->getSuccessOrdering();
2065 unsigned MemSemEq = static_cast<uint32_t>(getMemSemantics(AO)) | ScSem;
2066 Register MemSemEqReg = buildI32Constant(MemSemEq, I);
2067 AtomicOrdering FO = MemOp->getFailureOrdering();
2068 unsigned MemSemNeq = static_cast<uint32_t>(getMemSemantics(FO)) | ScSem;
2069 if (MemSemEq == MemSemNeq)
2070 MemSemNeqReg = MemSemEqReg;
2071 else {
2072 MemSemNeqReg = buildI32Constant(MemSemEq, I);
2073 }
2074 } else {
2075 ScopeReg = I.getOperand(5).getReg();
2076 MemSemEqReg = I.getOperand(6).getReg();
2077 MemSemNeqReg = I.getOperand(7).getReg();
2078 }
2079
2080 Register Cmp = I.getOperand(3).getReg();
2081 Register Val = I.getOperand(4).getReg();
2082 SPIRVTypeInst SpvValTy = GR.getSPIRVTypeForVReg(Val);
2083 Register ACmpRes = createVirtualRegister(SpvValTy, &GR, MRI, *I.getMF());
2084 const DebugLoc &DL = I.getDebugLoc();
2085 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange))
2086 .addDef(ACmpRes)
2087 .addUse(GR.getSPIRVTypeID(SpvValTy))
2088 .addUse(Ptr)
2089 .addUse(ScopeReg)
2090 .addUse(MemSemEqReg)
2091 .addUse(MemSemNeqReg)
2092 .addUse(Val)
2093 .addUse(Cmp)
2094 .constrainAllUses(TII, TRI, RBI);
2095 SPIRVTypeInst BoolTy = GR.getOrCreateSPIRVBoolType(I, TII);
2096 Register CmpSuccReg = createVirtualRegister(BoolTy, &GR, MRI, *I.getMF());
2097 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual))
2098 .addDef(CmpSuccReg)
2099 .addUse(GR.getSPIRVTypeID(BoolTy))
2100 .addUse(ACmpRes)
2101 .addUse(Cmp)
2102 .constrainAllUses(TII, TRI, RBI);
2103 Register TmpReg = createVirtualRegister(ResType, &GR, MRI, *I.getMF());
2104 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
2105 .addDef(TmpReg)
2106 .addUse(GR.getSPIRVTypeID(ResType))
2107 .addUse(ACmpRes)
2108 .addUse(GR.getOrCreateUndef(I, ResType, TII))
2109 .addImm(0)
2110 .constrainAllUses(TII, TRI, RBI);
2111 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
2112 .addDef(ResVReg)
2113 .addUse(GR.getSPIRVTypeID(ResType))
2114 .addUse(CmpSuccReg)
2115 .addUse(TmpReg)
2116 .addImm(1)
2117 .constrainAllUses(TII, TRI, RBI);
2118 return true;
2119}
2120
2121static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC) {
2122 switch (SC) {
2123 case SPIRV::StorageClass::DeviceOnlyINTEL:
2124 case SPIRV::StorageClass::HostOnlyINTEL:
2125 return true;
2126 default:
2127 return false;
2128 }
2129}
2130
2131// Returns true ResVReg is referred only from global vars and OpName's.
2132static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg) {
2133 bool IsGRef = false;
2134 bool IsAllowedRefs =
2135 llvm::all_of(MRI->use_instructions(ResVReg), [&IsGRef](auto const &It) {
2136 unsigned Opcode = It.getOpcode();
2137 if (Opcode == SPIRV::OpConstantComposite ||
2138 Opcode == SPIRV::OpVariable ||
2139 isSpvIntrinsic(It, Intrinsic::spv_init_global))
2140 return IsGRef = true;
2141 return Opcode == SPIRV::OpName;
2142 });
2143 return IsAllowedRefs && IsGRef;
2144}
2145
2146Register SPIRVInstructionSelector::getUcharPtrTypeReg(
2147 MachineInstr &I, SPIRV::StorageClass::StorageClass SC) const {
2148 return GR.getSPIRVTypeID(GR.getOrCreateSPIRVPointerType(
2149 Type::getInt8Ty(I.getMF()->getFunction().getContext()), I, SC));
2150}
2151
2152MachineInstrBuilder
2153SPIRVInstructionSelector::buildSpecConstantOp(MachineInstr &I, Register Dest,
2154 Register Src, Register DestType,
2155 uint32_t Opcode) const {
2156 return BuildMI(*I.getParent(), I, I.getDebugLoc(),
2157 TII.get(SPIRV::OpSpecConstantOp))
2158 .addDef(Dest)
2159 .addUse(DestType)
2160 .addImm(Opcode)
2161 .addUse(Src);
2162}
2163
2164MachineInstrBuilder
2165SPIRVInstructionSelector::buildConstGenericPtr(MachineInstr &I, Register SrcPtr,
2166 SPIRVTypeInst SrcPtrTy) const {
2167 SPIRVTypeInst GenericPtrTy =
2168 GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
2169 Register Tmp = MRI->createVirtualRegister(&SPIRV::pIDRegClass);
2170 MRI->setType(Tmp, LLT::pointer(storageClassToAddressSpace(
2171 SPIRV::StorageClass::Generic),
2172 GR.getPointerSize()));
2173 MachineFunction *MF = I.getParent()->getParent();
2174 GR.assignSPIRVTypeToVReg(GenericPtrTy, Tmp, *MF);
2175 MachineInstrBuilder MIB = buildSpecConstantOp(
2176 I, Tmp, SrcPtr, GR.getSPIRVTypeID(GenericPtrTy),
2177 static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric));
2178 GR.add(MIB.getInstr(), MIB);
2179 return MIB;
2180}
2181
2182// In SPIR-V address space casting can only happen to and from the Generic
2183// storage class. We can also only cast Workgroup, CrossWorkgroup, or Function
2184// pointers to and from Generic pointers. As such, we can convert e.g. from
2185// Workgroup to Function by going via a Generic pointer as an intermediary. All
2186// other combinations can only be done by a bitcast, and are probably not safe.
2187bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
2188 SPIRVTypeInst ResType,
2189 MachineInstr &I) const {
2190 MachineBasicBlock &BB = *I.getParent();
2191 const DebugLoc &DL = I.getDebugLoc();
2192
2193 Register SrcPtr = I.getOperand(1).getReg();
2194 SPIRVTypeInst SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr);
2195
2196 // don't generate a cast for a null that may be represented by OpTypeInt
2197 if (SrcPtrTy->getOpcode() != SPIRV::OpTypePointer ||
2198 ResType->getOpcode() != SPIRV::OpTypePointer)
2199 return BuildCOPY(ResVReg, SrcPtr, I);
2200
2201 SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtrTy);
2202 SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResType);
2203
2204 if (isASCastInGVar(MRI, ResVReg)) {
2205 // AddrSpaceCast uses within OpVariable and OpConstantComposite instructions
2206 // are expressed by OpSpecConstantOp with an Opcode.
2207 // TODO: maybe insert a check whether the Kernel capability was declared and
2208 // so PtrCastToGeneric/GenericCastToPtr are available.
2209 unsigned SpecOpcode =
2210 DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC)
2211 ? static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric)
2212 : (SrcSC == SPIRV::StorageClass::Generic &&
2213 isGenericCastablePtr(DstSC)
2214 ? static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr)
2215 : 0);
2216 // TODO: OpConstantComposite expects i8*, so we are forced to forget a
2217 // correct value of ResType and use general i8* instead. Maybe this should
2218 // be addressed in the emit-intrinsic step to infer a correct
2219 // OpConstantComposite type.
2220 if (SpecOpcode) {
2221 buildSpecConstantOp(I, ResVReg, SrcPtr, getUcharPtrTypeReg(I, DstSC),
2222 SpecOpcode)
2223 .constrainAllUses(TII, TRI, RBI);
2224 } else if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
2225 MachineInstrBuilder MIB = buildConstGenericPtr(I, SrcPtr, SrcPtrTy);
2226 MIB.constrainAllUses(TII, TRI, RBI);
2227 buildSpecConstantOp(
2228 I, ResVReg, MIB->getOperand(0).getReg(), getUcharPtrTypeReg(I, DstSC),
2229 static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
2230 .constrainAllUses(TII, TRI, RBI);
2231 }
2232 return true;
2233 }
2234
2235 // don't generate a cast between identical storage classes
2236 if (SrcSC == DstSC)
2237 return BuildCOPY(ResVReg, SrcPtr, I);
2238
2239 if ((SrcSC == SPIRV::StorageClass::Function &&
2240 DstSC == SPIRV::StorageClass::Private) ||
2241 (DstSC == SPIRV::StorageClass::Function &&
2242 SrcSC == SPIRV::StorageClass::Private))
2243 return BuildCOPY(ResVReg, SrcPtr, I);
2244
2245 // Casting from an eligible pointer to Generic.
2246 if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC))
2247 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
2248 // Casting from Generic to an eligible pointer.
2249 if (SrcSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(DstSC))
2250 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
2251 // Casting between 2 eligible pointers using Generic as an intermediary.
2252 if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
2253 SPIRVTypeInst GenericPtrTy =
2254 GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
2255 Register Tmp = createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
2256 BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric))
2257 .addDef(Tmp)
2258 .addUse(GR.getSPIRVTypeID(GenericPtrTy))
2259 .addUse(SrcPtr)
2260 .constrainAllUses(TII, TRI, RBI);
2261 BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr))
2262 .addDef(ResVReg)
2263 .addUse(GR.getSPIRVTypeID(ResType))
2264 .addUse(Tmp)
2265 .constrainAllUses(TII, TRI, RBI);
2266 return true;
2267 }
2268
2269 // Check if instructions from the SPV_INTEL_usm_storage_classes extension may
2270 // be applied
2271 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::CrossWorkgroup)
2272 return selectUnOp(ResVReg, ResType, I,
2273 SPIRV::OpPtrCastToCrossWorkgroupINTEL);
2274 if (SrcSC == SPIRV::StorageClass::CrossWorkgroup && isUSMStorageClass(DstSC))
2275 return selectUnOp(ResVReg, ResType, I,
2276 SPIRV::OpCrossWorkgroupCastToPtrINTEL);
2277 if (isUSMStorageClass(SrcSC) && DstSC == SPIRV::StorageClass::Generic)
2278 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
2279 if (SrcSC == SPIRV::StorageClass::Generic && isUSMStorageClass(DstSC))
2280 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
2281
2282 // Bitcast for pointers requires that the address spaces must match
2283 return false;
2284}
2285
2286static unsigned getFCmpOpcode(unsigned PredNum) {
2287 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2288 switch (Pred) {
2289 case CmpInst::FCMP_OEQ:
2290 return SPIRV::OpFOrdEqual;
2291 case CmpInst::FCMP_OGE:
2292 return SPIRV::OpFOrdGreaterThanEqual;
2293 case CmpInst::FCMP_OGT:
2294 return SPIRV::OpFOrdGreaterThan;
2295 case CmpInst::FCMP_OLE:
2296 return SPIRV::OpFOrdLessThanEqual;
2297 case CmpInst::FCMP_OLT:
2298 return SPIRV::OpFOrdLessThan;
2299 case CmpInst::FCMP_ONE:
2300 return SPIRV::OpFOrdNotEqual;
2301 case CmpInst::FCMP_ORD:
2302 return SPIRV::OpOrdered;
2303 case CmpInst::FCMP_UEQ:
2304 return SPIRV::OpFUnordEqual;
2305 case CmpInst::FCMP_UGE:
2306 return SPIRV::OpFUnordGreaterThanEqual;
2307 case CmpInst::FCMP_UGT:
2308 return SPIRV::OpFUnordGreaterThan;
2309 case CmpInst::FCMP_ULE:
2310 return SPIRV::OpFUnordLessThanEqual;
2311 case CmpInst::FCMP_ULT:
2312 return SPIRV::OpFUnordLessThan;
2313 case CmpInst::FCMP_UNE:
2314 return SPIRV::OpFUnordNotEqual;
2315 case CmpInst::FCMP_UNO:
2316 return SPIRV::OpUnordered;
2317 default:
2318 llvm_unreachable("Unknown predicate type for FCmp");
2319 }
2320}
2321
2322static unsigned getICmpOpcode(unsigned PredNum) {
2323 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2324 switch (Pred) {
2325 case CmpInst::ICMP_EQ:
2326 return SPIRV::OpIEqual;
2327 case CmpInst::ICMP_NE:
2328 return SPIRV::OpINotEqual;
2329 case CmpInst::ICMP_SGE:
2330 return SPIRV::OpSGreaterThanEqual;
2331 case CmpInst::ICMP_SGT:
2332 return SPIRV::OpSGreaterThan;
2333 case CmpInst::ICMP_SLE:
2334 return SPIRV::OpSLessThanEqual;
2335 case CmpInst::ICMP_SLT:
2336 return SPIRV::OpSLessThan;
2337 case CmpInst::ICMP_UGE:
2338 return SPIRV::OpUGreaterThanEqual;
2339 case CmpInst::ICMP_UGT:
2340 return SPIRV::OpUGreaterThan;
2341 case CmpInst::ICMP_ULE:
2342 return SPIRV::OpULessThanEqual;
2343 case CmpInst::ICMP_ULT:
2344 return SPIRV::OpULessThan;
2345 default:
2346 llvm_unreachable("Unknown predicate type for ICmp");
2347 }
2348}
2349
2350static unsigned getPtrCmpOpcode(unsigned Pred) {
2351 switch (static_cast<CmpInst::Predicate>(Pred)) {
2352 case CmpInst::ICMP_EQ:
2353 return SPIRV::OpPtrEqual;
2354 case CmpInst::ICMP_NE:
2355 return SPIRV::OpPtrNotEqual;
2356 default:
2357 llvm_unreachable("Unknown predicate type for pointer comparison");
2358 }
2359}
2360
2361// Return the logical operation, or abort if none exists.
2362static unsigned getBoolCmpOpcode(unsigned PredNum) {
2363 auto Pred = static_cast<CmpInst::Predicate>(PredNum);
2364 switch (Pred) {
2365 case CmpInst::ICMP_EQ:
2366 return SPIRV::OpLogicalEqual;
2367 case CmpInst::ICMP_NE:
2368 return SPIRV::OpLogicalNotEqual;
2369 default:
2370 llvm_unreachable("Unknown predicate type for Bool comparison");
2371 }
2372}
2373
2374static APFloat getZeroFP(const Type *LLVMFloatTy) {
2375 if (!LLVMFloatTy)
2376 return APFloat::getZero(APFloat::IEEEsingle());
2377 switch (LLVMFloatTy->getScalarType()->getTypeID()) {
2378 case Type::HalfTyID:
2379 return APFloat::getZero(APFloat::IEEEhalf());
2380 default:
2381 case Type::FloatTyID:
2382 return APFloat::getZero(APFloat::IEEEsingle());
2383 case Type::DoubleTyID:
2384 return APFloat::getZero(APFloat::IEEEdouble());
2385 }
2386}
2387
2388static APFloat getOneFP(const Type *LLVMFloatTy) {
2389 if (!LLVMFloatTy)
2390 return APFloat::getOne(APFloat::IEEEsingle());
2391 switch (LLVMFloatTy->getScalarType()->getTypeID()) {
2392 case Type::HalfTyID:
2393 return APFloat::getOne(APFloat::IEEEhalf());
2394 default:
2395 case Type::FloatTyID:
2396 return APFloat::getOne(APFloat::IEEEsingle());
2397 case Type::DoubleTyID:
2398 return APFloat::getOne(APFloat::IEEEdouble());
2399 }
2400}
2401
2402bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
2403 SPIRVTypeInst ResType,
2404 MachineInstr &I,
2405 unsigned OpAnyOrAll) const {
2406 assert(I.getNumOperands() == 3);
2407 assert(I.getOperand(2).isReg());
2408 MachineBasicBlock &BB = *I.getParent();
2409 Register InputRegister = I.getOperand(2).getReg();
2410 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2411
2412 if (!InputType)
2413 report_fatal_error("Input Type could not be determined.");
2414
2415 bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool);
2416 bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector;
2417 if (IsBoolTy && !IsVectorTy) {
2418 assert(ResVReg == I.getOperand(0).getReg());
2419 return BuildCOPY(ResVReg, InputRegister, I);
2420 }
2421
2422 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2423 unsigned SpirvNotEqualId =
2424 IsFloatTy ? SPIRV::OpFOrdNotEqual : SPIRV::OpINotEqual;
2425 SPIRVTypeInst SpvBoolScalarTy = GR.getOrCreateSPIRVBoolType(I, TII);
2426 SPIRVTypeInst SpvBoolTy = SpvBoolScalarTy;
2427 Register NotEqualReg = ResVReg;
2428
2429 if (IsVectorTy) {
2430 NotEqualReg =
2431 IsBoolTy ? InputRegister
2432 : createVirtualRegister(SpvBoolTy, &GR, MRI, MRI->getMF());
2433 const unsigned NumElts = InputType->getOperand(2).getImm();
2434 SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII);
2435 }
2436
2437 if (!IsBoolTy) {
2438 Register ConstZeroReg =
2439 IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I);
2440
2441 BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId))
2442 .addDef(NotEqualReg)
2443 .addUse(GR.getSPIRVTypeID(SpvBoolTy))
2444 .addUse(InputRegister)
2445 .addUse(ConstZeroReg)
2446 .constrainAllUses(TII, TRI, RBI);
2447 }
2448
2449 if (IsVectorTy)
2450 BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll))
2451 .addDef(ResVReg)
2452 .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy))
2453 .addUse(NotEqualReg)
2454 .constrainAllUses(TII, TRI, RBI);
2455 return true;
2456}
2457
2458bool SPIRVInstructionSelector::selectAll(Register ResVReg,
2459 SPIRVTypeInst ResType,
2460 MachineInstr &I) const {
2461 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll);
2462}
2463
2464bool SPIRVInstructionSelector::selectAny(Register ResVReg,
2465 SPIRVTypeInst ResType,
2466 MachineInstr &I) const {
2467 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
2468}
2469
2470// Select the OpDot instruction for the given float dot
2471bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg,
2472 SPIRVTypeInst ResType,
2473 MachineInstr &I) const {
2474 assert(I.getNumOperands() == 4);
2475 assert(I.getOperand(2).isReg());
2476 assert(I.getOperand(3).isReg());
2477
2478 [[maybe_unused]] SPIRVTypeInst VecType =
2479 GR.getSPIRVTypeForVReg(I.getOperand(2).getReg());
2480
2481 assert(VecType->getOpcode() == SPIRV::OpTypeVector &&
2482 GR.getScalarOrVectorComponentCount(VecType) > 1 &&
2483 "dot product requires a vector of at least 2 components");
2484
2485 [[maybe_unused]] SPIRVTypeInst EltType =
2486 GR.getSPIRVTypeForVReg(VecType->getOperand(1).getReg());
2487
2488 assert(EltType->getOpcode() == SPIRV::OpTypeFloat);
2489
2490 MachineBasicBlock &BB = *I.getParent();
2491 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpDot))
2492 .addDef(ResVReg)
2493 .addUse(GR.getSPIRVTypeID(ResType))
2494 .addUse(I.getOperand(2).getReg())
2495 .addUse(I.getOperand(3).getReg())
2496 .constrainAllUses(TII, TRI, RBI);
2497 return true;
2498}
2499
2500bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg,
2501 SPIRVTypeInst ResType,
2502 MachineInstr &I,
2503 bool Signed) const {
2504 assert(I.getNumOperands() == 4);
2505 assert(I.getOperand(2).isReg());
2506 assert(I.getOperand(3).isReg());
2507 MachineBasicBlock &BB = *I.getParent();
2508
2509 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot;
2510 BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
2511 .addDef(ResVReg)
2512 .addUse(GR.getSPIRVTypeID(ResType))
2513 .addUse(I.getOperand(2).getReg())
2514 .addUse(I.getOperand(3).getReg())
2515 .constrainAllUses(TII, TRI, RBI);
2516 return true;
2517}
2518
2519// Since pre-1.6 SPIRV has no integer dot implementation,
2520// expand by piecewise multiplying and adding the results
2521bool SPIRVInstructionSelector::selectIntegerDotExpansion(
2522 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2523 assert(I.getNumOperands() == 4);
2524 assert(I.getOperand(2).isReg());
2525 assert(I.getOperand(3).isReg());
2526 MachineBasicBlock &BB = *I.getParent();
2527
2528 // Multiply the vectors, then sum the results
2529 Register Vec0 = I.getOperand(2).getReg();
2530 Register Vec1 = I.getOperand(3).getReg();
2531 Register TmpVec = MRI->createVirtualRegister(GR.getRegClass(ResType));
2532 SPIRVTypeInst VecType = GR.getSPIRVTypeForVReg(Vec0);
2533
2534 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulV))
2535 .addDef(TmpVec)
2536 .addUse(GR.getSPIRVTypeID(VecType))
2537 .addUse(Vec0)
2538 .addUse(Vec1)
2539 .constrainAllUses(TII, TRI, RBI);
2540
2541 assert(VecType->getOpcode() == SPIRV::OpTypeVector &&
2542 GR.getScalarOrVectorComponentCount(VecType) > 1 &&
2543 "dot product requires a vector of at least 2 components");
2544
2545 Register Res = MRI->createVirtualRegister(GR.getRegClass(ResType));
2546 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2547 .addDef(Res)
2548 .addUse(GR.getSPIRVTypeID(ResType))
2549 .addUse(TmpVec)
2550 .addImm(0)
2551 .constrainAllUses(TII, TRI, RBI);
2552
2553 for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) {
2554 Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType));
2555
2556 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
2557 .addDef(Elt)
2558 .addUse(GR.getSPIRVTypeID(ResType))
2559 .addUse(TmpVec)
2560 .addImm(i)
2561 .constrainAllUses(TII, TRI, RBI);
2562
2563 Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1
2564 ? MRI->createVirtualRegister(GR.getRegClass(ResType))
2565 : ResVReg;
2566
2567 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2568 .addDef(Sum)
2569 .addUse(GR.getSPIRVTypeID(ResType))
2570 .addUse(Res)
2571 .addUse(Elt)
2572 .constrainAllUses(TII, TRI, RBI);
2573 Res = Sum;
2574 }
2575
2576 return true;
2577}
2578
2579bool SPIRVInstructionSelector::selectOpIsInf(Register ResVReg,
2580 SPIRVTypeInst ResType,
2581 MachineInstr &I) const {
2582 MachineBasicBlock &BB = *I.getParent();
2583 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsInf))
2584 .addDef(ResVReg)
2585 .addUse(GR.getSPIRVTypeID(ResType))
2586 .addUse(I.getOperand(2).getReg())
2587 .constrainAllUses(TII, TRI, RBI);
2588 return true;
2589}
2590
2591bool SPIRVInstructionSelector::selectOpIsNan(Register ResVReg,
2592 SPIRVTypeInst ResType,
2593 MachineInstr &I) const {
2594 MachineBasicBlock &BB = *I.getParent();
2595 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsNan))
2596 .addDef(ResVReg)
2597 .addUse(GR.getSPIRVTypeID(ResType))
2598 .addUse(I.getOperand(2).getReg())
2599 .constrainAllUses(TII, TRI, RBI);
2600 return true;
2601}
2602
2603template <bool Signed>
2604bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg,
2605 SPIRVTypeInst ResType,
2606 MachineInstr &I) const {
2607 assert(I.getNumOperands() == 5);
2608 assert(I.getOperand(2).isReg());
2609 assert(I.getOperand(3).isReg());
2610 assert(I.getOperand(4).isReg());
2611 MachineBasicBlock &BB = *I.getParent();
2612
2613 Register Acc = I.getOperand(2).getReg();
2614 Register X = I.getOperand(3).getReg();
2615 Register Y = I.getOperand(4).getReg();
2616
2617 auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot;
2618 Register Dot = MRI->createVirtualRegister(GR.getRegClass(ResType));
2619 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
2620 .addDef(Dot)
2621 .addUse(GR.getSPIRVTypeID(ResType))
2622 .addUse(X)
2623 .addUse(Y);
2624 MIB.addImm(SPIRV::BuiltIn::PackedVectorFormat4x8Bit);
2625 MIB.constrainAllUses(TII, TRI, RBI);
2626
2627 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2628 .addDef(ResVReg)
2629 .addUse(GR.getSPIRVTypeID(ResType))
2630 .addUse(Dot)
2631 .addUse(Acc)
2632 .constrainAllUses(TII, TRI, RBI);
2633 return true;
2634}
2635
2636// Since pre-1.6 SPIRV has no DotProductInput4x8BitPacked implementation,
2637// extract the elements of the packed inputs, multiply them and add the result
2638// to the accumulator.
2639template <bool Signed>
2640bool SPIRVInstructionSelector::selectDot4AddPackedExpansion(
2641 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2642 assert(I.getNumOperands() == 5);
2643 assert(I.getOperand(2).isReg());
2644 assert(I.getOperand(3).isReg());
2645 assert(I.getOperand(4).isReg());
2646 MachineBasicBlock &BB = *I.getParent();
2647
2648 Register Acc = I.getOperand(2).getReg();
2649 Register X = I.getOperand(3).getReg();
2650 Register Y = I.getOperand(4).getReg();
2651
2652 SPIRVTypeInst EltType = GR.getOrCreateSPIRVIntegerType(8, I, TII);
2653 auto ExtractOp =
2654 Signed ? SPIRV::OpBitFieldSExtract : SPIRV::OpBitFieldUExtract;
2655
2656 bool ZeroAsNull = !STI.isShader();
2657 // Extract the i8 element, multiply and add it to the accumulator
2658 for (unsigned i = 0; i < 4; i++) {
2659 // A[i]
2660 Register AElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2661 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2662 .addDef(AElt)
2663 .addUse(GR.getSPIRVTypeID(ResType))
2664 .addUse(X)
2665 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull))
2666 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2667 .constrainAllUses(TII, TRI, RBI);
2668
2669 // B[i]
2670 Register BElt = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2671 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2672 .addDef(BElt)
2673 .addUse(GR.getSPIRVTypeID(ResType))
2674 .addUse(Y)
2675 .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull))
2676 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2677 .constrainAllUses(TII, TRI, RBI);
2678
2679 // A[i] * B[i]
2680 Register Mul = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2681 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS))
2682 .addDef(Mul)
2683 .addUse(GR.getSPIRVTypeID(ResType))
2684 .addUse(AElt)
2685 .addUse(BElt)
2686 .constrainAllUses(TII, TRI, RBI);
2687
2688 // Discard 24 highest-bits so that stored i32 register is i8 equivalent
2689 Register MaskMul = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2690 BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp))
2691 .addDef(MaskMul)
2692 .addUse(GR.getSPIRVTypeID(ResType))
2693 .addUse(Mul)
2694 .addUse(GR.getOrCreateConstInt(0, I, EltType, TII, ZeroAsNull))
2695 .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull))
2696 .constrainAllUses(TII, TRI, RBI);
2697
2698 // Acc = Acc + A[i] * B[i]
2699 Register Sum =
2700 i < 3 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg;
2701 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
2702 .addDef(Sum)
2703 .addUse(GR.getSPIRVTypeID(ResType))
2704 .addUse(Acc)
2705 .addUse(MaskMul)
2706 .constrainAllUses(TII, TRI, RBI);
2707
2708 Acc = Sum;
2709 }
2710
2711 return true;
2712}
2713
2714/// Transform saturate(x) to clamp(x, 0.0f, 1.0f) as SPIRV
2715/// does not have a saturate builtin.
2716bool SPIRVInstructionSelector::selectSaturate(Register ResVReg,
2717 SPIRVTypeInst ResType,
2718 MachineInstr &I) const {
2719 assert(I.getNumOperands() == 3);
2720 assert(I.getOperand(2).isReg());
2721 MachineBasicBlock &BB = *I.getParent();
2722 Register VZero = buildZerosValF(ResType, I);
2723 Register VOne = buildOnesValF(ResType, I);
2724
2725 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
2726 .addDef(ResVReg)
2727 .addUse(GR.getSPIRVTypeID(ResType))
2728 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2729 .addImm(GL::FClamp)
2730 .addUse(I.getOperand(2).getReg())
2731 .addUse(VZero)
2732 .addUse(VOne)
2733 .constrainAllUses(TII, TRI, RBI);
2734 return true;
2735}
2736
2737bool SPIRVInstructionSelector::selectSign(Register ResVReg,
2738 SPIRVTypeInst ResType,
2739 MachineInstr &I) const {
2740 assert(I.getNumOperands() == 3);
2741 assert(I.getOperand(2).isReg());
2742 MachineBasicBlock &BB = *I.getParent();
2743 Register InputRegister = I.getOperand(2).getReg();
2744 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2745 auto &DL = I.getDebugLoc();
2746
2747 if (!InputType)
2748 report_fatal_error("Input Type could not be determined.");
2749
2750 bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2751
2752 unsigned SignBitWidth = GR.getScalarOrVectorBitWidth(InputType);
2753 unsigned ResBitWidth = GR.getScalarOrVectorBitWidth(ResType);
2754
2755 bool NeedsConversion = IsFloatTy || SignBitWidth != ResBitWidth;
2756
2757 auto SignOpcode = IsFloatTy ? GL::FSign : GL::SSign;
2758 Register SignReg = NeedsConversion
2759 ? MRI->createVirtualRegister(&SPIRV::IDRegClass)
2760 : ResVReg;
2761
2762 BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst))
2763 .addDef(SignReg)
2764 .addUse(GR.getSPIRVTypeID(InputType))
2765 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2766 .addImm(SignOpcode)
2767 .addUse(InputRegister)
2768 .constrainAllUses(TII, TRI, RBI);
2769
2770 if (NeedsConversion) {
2771 auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert;
2772 BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode))
2773 .addDef(ResVReg)
2774 .addUse(GR.getSPIRVTypeID(ResType))
2775 .addUse(SignReg)
2776 .constrainAllUses(TII, TRI, RBI);
2777 }
2778
2779 return true;
2780}
2781
2782bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
2783 SPIRVTypeInst ResType,
2784 MachineInstr &I,
2785 unsigned Opcode) const {
2786 MachineBasicBlock &BB = *I.getParent();
2787 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2788
2789 auto BMI = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2790 .addDef(ResVReg)
2791 .addUse(GR.getSPIRVTypeID(ResType))
2792 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I,
2793 IntTy, TII, !STI.isShader()));
2794
2795 for (unsigned J = 2; J < I.getNumOperands(); J++) {
2796 BMI.addUse(I.getOperand(J).getReg());
2797 }
2798
2799 BMI.constrainAllUses(TII, TRI, RBI);
2800 return true;
2801}
2802
2803bool SPIRVInstructionSelector::selectWaveActiveCountBits(
2804 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
2805
2806 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2807 SPIRVTypeInst BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII);
2808 Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType));
2809 if (!selectWaveOpInst(BallotReg, BallotType, I,
2810 SPIRV::OpGroupNonUniformBallot))
2811 return false;
2812
2813 MachineBasicBlock &BB = *I.getParent();
2814 BuildMI(BB, I, I.getDebugLoc(),
2815 TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2816 .addDef(ResVReg)
2817 .addUse(GR.getSPIRVTypeID(ResType))
2818 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
2819 !STI.isShader()))
2820 .addImm(SPIRV::GroupOperation::Reduce)
2821 .addUse(BallotReg)
2822 .constrainAllUses(TII, TRI, RBI);
2823
2824 return true;
2825}
2826
2827unsigned getVectorSizeOrOne(SPIRVTypeInst Type) {
2828
2829 if (Type->getOpcode() != SPIRV::OpTypeVector)
2830 return 1;
2831
2832 // Operand(2) is the vector size
2833 return Type->getOperand(2).getImm();
2834}
2835
2836bool SPIRVInstructionSelector::selectWaveActiveAllEqual(Register ResVReg,
2837 SPIRVTypeInst ResType,
2838 MachineInstr &I) const {
2839 MachineBasicBlock &BB = *I.getParent();
2840 const DebugLoc &DL = I.getDebugLoc();
2841
2842 // Input to the intrinsic
2843 Register InputReg = I.getOperand(2).getReg();
2844 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputReg);
2845
2846 // Determine if input is vector
2847 unsigned NumElems = getVectorSizeOrOne(InputType);
2848 bool IsVector = NumElems > 1;
2849
2850 // Determine element types
2851 SPIRVTypeInst ElemInputType = InputType;
2852 SPIRVTypeInst ElemBoolType = ResType;
2853 if (IsVector) {
2854 ElemInputType = GR.getSPIRVTypeForVReg(InputType->getOperand(1).getReg());
2855 ElemBoolType = GR.getSPIRVTypeForVReg(ResType->getOperand(1).getReg());
2856 }
2857
2858 // Subgroup scope constant
2859 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2860 Register ScopeConst = GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy,
2861 TII, !STI.isShader());
2862
2863 // Scalar case
2864 if (!IsVector) {
2865 return selectWaveOpInst(ResVReg, ElemBoolType, I,
2866 SPIRV::OpGroupNonUniformAllEqual);
2867 }
2868
2869 // Vector case
2870 SmallVector<Register, 4> ElementResults;
2871 ElementResults.reserve(NumElems);
2872
2873 for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
2874 // Extract element
2875 Register ElemInput = InputReg;
2876 Register Extracted =
2877 MRI->createVirtualRegister(GR.getRegClass(ElemInputType));
2878
2879 BuildMI(BB, I, DL, TII.get(SPIRV::OpCompositeExtract))
2880 .addDef(Extracted)
2881 .addUse(GR.getSPIRVTypeID(ElemInputType))
2882 .addUse(InputReg)
2883 .addImm(Idx)
2884 .constrainAllUses(TII, TRI, RBI);
2885
2886 ElemInput = Extracted;
2887
2888 // Emit per-element AllEqual
2889 Register ElemResult =
2890 MRI->createVirtualRegister(GR.getRegClass(ElemBoolType));
2891
2892 BuildMI(BB, I, DL, TII.get(SPIRV::OpGroupNonUniformAllEqual))
2893 .addDef(ElemResult)
2894 .addUse(GR.getSPIRVTypeID(ElemBoolType))
2895 .addUse(ScopeConst)
2896 .addUse(ElemInput)
2897 .constrainAllUses(TII, TRI, RBI);
2898
2899 ElementResults.push_back(ElemResult);
2900 }
2901
2902 // Reconstruct vector<bool>
2903 auto MIB = BuildMI(BB, I, DL, TII.get(SPIRV::OpCompositeConstruct))
2904 .addDef(ResVReg)
2905 .addUse(GR.getSPIRVTypeID(ResType));
2906 for (Register R : ElementResults)
2907 MIB.addUse(R);
2908
2909 MIB.constrainAllUses(TII, TRI, RBI);
2910
2911 return true;
2912}
2913
2914bool SPIRVInstructionSelector::selectWavePrefixBitCount(Register ResVReg,
2915 SPIRVTypeInst ResType,
2916 MachineInstr &I) const {
2917
2918 assert(I.getNumOperands() == 3);
2919
2920 auto Op = I.getOperand(2);
2921 assert(Op.isReg());
2922
2923 MachineBasicBlock &BB = *I.getParent();
2924 DebugLoc DL = I.getDebugLoc();
2925
2926 Register InputRegister = Op.getReg();
2927 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
2928
2929 if (!InputType)
2930 report_fatal_error("Input Type could not be determined.");
2931
2932 if (InputType->getOpcode() != SPIRV::OpTypeBool)
2933 report_fatal_error("WavePrefixBitCount requires boolean input");
2934
2935 // Types
2936 SPIRVTypeInst Int32Ty = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2937
2938 // Ballot result type: vector<uint32>
2939 // Match DXC: %v4uint for Subgroup size
2940 SPIRVTypeInst BallotTy = GR.getOrCreateSPIRVVectorType(Int32Ty, 4, I, TII);
2941
2942 // Create a vreg for the ballot result
2943 Register BallotVReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
2944
2945 // 1. OpGroupNonUniformBallot
2946 BuildMI(BB, I, DL, TII.get(SPIRV::OpGroupNonUniformBallot))
2947 .addDef(BallotVReg)
2948 .addUse(GR.getSPIRVTypeID(BallotTy))
2949 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, Int32Ty, TII))
2950 .addUse(InputRegister)
2951 .constrainAllUses(TII, TRI, RBI);
2952
2953 // 2. OpGroupNonUniformBallotBitCount
2954 BuildMI(BB, I, DL, TII.get(SPIRV::OpGroupNonUniformBallotBitCount))
2955 .addDef(ResVReg)
2956 .addUse(GR.getSPIRVTypeID(ResType))
2957 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, Int32Ty, TII))
2958 .addImm(SPIRV::GroupOperation::ExclusiveScan)
2959 .addUse(BallotVReg)
2960 .constrainAllUses(TII, TRI, RBI);
2961
2962 return true;
2963}
2964
2965bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
2966 SPIRVTypeInst ResType,
2967 MachineInstr &I,
2968 bool IsUnsigned) const {
2969 return selectWaveReduce(
2970 ResVReg, ResType, I, IsUnsigned,
2971 [&](Register InputRegister, bool IsUnsigned) {
2972 const bool IsFloatTy =
2973 GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2974 const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMax
2975 : SPIRV::OpGroupNonUniformSMax;
2976 return IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntOp;
2977 });
2978}
2979
2980bool SPIRVInstructionSelector::selectWaveReduceMin(Register ResVReg,
2981 SPIRVTypeInst ResType,
2982 MachineInstr &I,
2983 bool IsUnsigned) const {
2984 return selectWaveReduce(
2985 ResVReg, ResType, I, IsUnsigned,
2986 [&](Register InputRegister, bool IsUnsigned) {
2987 const bool IsFloatTy =
2988 GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2989 const auto IntOp = IsUnsigned ? SPIRV::OpGroupNonUniformUMin
2990 : SPIRV::OpGroupNonUniformSMin;
2991 return IsFloatTy ? SPIRV::OpGroupNonUniformFMin : IntOp;
2992 });
2993}
2994
2995bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
2996 SPIRVTypeInst ResType,
2997 MachineInstr &I) const {
2998 return selectWaveReduce(ResVReg, ResType, I, /*IsUnsigned*/ false,
2999 [&](Register InputRegister, bool IsUnsigned) {
3000 bool IsFloatTy = GR.isScalarOrVectorOfType(
3001 InputRegister, SPIRV::OpTypeFloat);
3002 return IsFloatTy ? SPIRV::OpGroupNonUniformFAdd
3003 : SPIRV::OpGroupNonUniformIAdd;
3004 });
3005}
3006
3007template <typename PickOpcodeFn>
3008bool SPIRVInstructionSelector::selectWaveReduce(
3009 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned,
3010 PickOpcodeFn &&PickOpcode) const {
3011 assert(I.getNumOperands() == 3);
3012 assert(I.getOperand(2).isReg());
3013 MachineBasicBlock &BB = *I.getParent();
3014 Register InputRegister = I.getOperand(2).getReg();
3015 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
3016
3017 if (!InputType)
3018 report_fatal_error("Input Type could not be determined.");
3019
3020 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
3021 const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned);
3022 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3023 .addDef(ResVReg)
3024 .addUse(GR.getSPIRVTypeID(ResType))
3025 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
3026 !STI.isShader()))
3027 .addImm(SPIRV::GroupOperation::Reduce)
3028 .addUse(I.getOperand(2).getReg())
3029 .constrainAllUses(TII, TRI, RBI);
3030 return true;
3031}
3032
3033bool SPIRVInstructionSelector::selectWaveExclusiveScanSum(
3034 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
3035 return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false,
3036 [&](Register InputRegister, bool IsUnsigned) {
3037 bool IsFloatTy = GR.isScalarOrVectorOfType(
3038 InputRegister, SPIRV::OpTypeFloat);
3039 return IsFloatTy
3040 ? SPIRV::OpGroupNonUniformFAdd
3041 : SPIRV::OpGroupNonUniformIAdd;
3042 });
3043}
3044
3045bool SPIRVInstructionSelector::selectWaveExclusiveScanProduct(
3046 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
3047 return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false,
3048 [&](Register InputRegister, bool IsUnsigned) {
3049 bool IsFloatTy = GR.isScalarOrVectorOfType(
3050 InputRegister, SPIRV::OpTypeFloat);
3051 return IsFloatTy
3052 ? SPIRV::OpGroupNonUniformFMul
3053 : SPIRV::OpGroupNonUniformIMul;
3054 });
3055}
3056
3057template <typename PickOpcodeFn>
3058bool SPIRVInstructionSelector::selectWaveExclusiveScan(
3059 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned,
3060 PickOpcodeFn &&PickOpcode) const {
3061 assert(I.getNumOperands() == 3);
3062 assert(I.getOperand(2).isReg());
3063 MachineBasicBlock &BB = *I.getParent();
3064 Register InputRegister = I.getOperand(2).getReg();
3065 SPIRVTypeInst InputType = GR.getSPIRVTypeForVReg(InputRegister);
3066
3067 if (!InputType)
3068 report_fatal_error("Input Type could not be determined.");
3069
3070 SPIRVTypeInst IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
3071 const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned);
3072 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3073 .addDef(ResVReg)
3074 .addUse(GR.getSPIRVTypeID(ResType))
3075 .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII,
3076 !STI.isShader()))
3077 .addImm(SPIRV::GroupOperation::ExclusiveScan)
3078 .addUse(I.getOperand(2).getReg())
3079 .constrainAllUses(TII, TRI, RBI);
3080 return true;
3081}
3082
3083bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
3084 SPIRVTypeInst ResType,
3085 MachineInstr &I) const {
3086 MachineBasicBlock &BB = *I.getParent();
3087 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse))
3088 .addDef(ResVReg)
3089 .addUse(GR.getSPIRVTypeID(ResType))
3090 .addUse(I.getOperand(1).getReg())
3091 .constrainAllUses(TII, TRI, RBI);
3092 return true;
3093}
3094
3095bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
3096 SPIRVTypeInst ResType,
3097 MachineInstr &I) const {
3098 // There is no way to implement `freeze` correctly without support on SPIR-V
3099 // standard side, but we may at least address a simple (static) case when
3100 // undef/poison value presence is obvious. The main benefit of even
3101 // incomplete `freeze` support is preventing of translation from crashing due
3102 // to lack of support on legalization and instruction selection steps.
3103 if (!I.getOperand(0).isReg() || !I.getOperand(1).isReg())
3104 return false;
3105 Register OpReg = I.getOperand(1).getReg();
3106 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) {
3107 if (Def->getOpcode() == TargetOpcode::COPY)
3108 Def = MRI->getVRegDef(Def->getOperand(1).getReg());
3109 Register Reg;
3110 switch (Def->getOpcode()) {
3111 case SPIRV::ASSIGN_TYPE:
3112 if (MachineInstr *AssignToDef =
3113 MRI->getVRegDef(Def->getOperand(1).getReg())) {
3114 if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
3115 Reg = Def->getOperand(2).getReg();
3116 }
3117 break;
3118 case SPIRV::OpUndef:
3119 Reg = Def->getOperand(1).getReg();
3120 break;
3121 }
3122 unsigned DestOpCode;
3123 if (Reg.isValid()) {
3124 DestOpCode = SPIRV::OpConstantNull;
3125 } else {
3126 DestOpCode = TargetOpcode::COPY;
3127 Reg = OpReg;
3128 }
3129 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode))
3130 .addDef(I.getOperand(0).getReg())
3131 .addUse(Reg)
3132 .constrainAllUses(TII, TRI, RBI);
3133 return true;
3134 }
3135 return false;
3136}
3137
3138bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg,
3139 SPIRVTypeInst ResType,
3140 MachineInstr &I) const {
3141 unsigned N = 0;
3142 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3143 N = GR.getScalarOrVectorComponentCount(ResType);
3144 else if (ResType->getOpcode() == SPIRV::OpTypeArray)
3145 N = getArrayComponentCount(MRI, ResType);
3146 else
3147 report_fatal_error("Cannot select G_BUILD_VECTOR with a non-vector result");
3148 if (I.getNumExplicitOperands() - I.getNumExplicitDefs() != N)
3149 report_fatal_error("G_BUILD_VECTOR and the result type are inconsistent");
3150
3151 // check if we may construct a constant vector
3152 bool IsConst = true;
3153 for (unsigned i = I.getNumExplicitDefs();
3154 i < I.getNumExplicitOperands() && IsConst; ++i)
3155 if (!isConstReg(MRI, I.getOperand(i).getReg()))
3156 IsConst = false;
3157
3158 if (!IsConst && N < 2)
3159 report_fatal_error(
3160 "There must be at least two constituent operands in a vector");
3161
3162 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3163 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3164 TII.get(IsConst ? SPIRV::OpConstantComposite
3165 : SPIRV::OpCompositeConstruct))
3166 .addDef(ResVReg)
3167 .addUse(GR.getSPIRVTypeID(ResType));
3168 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i)
3169 MIB.addUse(I.getOperand(i).getReg());
3170 MIB.constrainAllUses(TII, TRI, RBI);
3171 return true;
3172}
3173
3174bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
3175 SPIRVTypeInst ResType,
3176 MachineInstr &I) const {
3177 unsigned N = 0;
3178 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3179 N = GR.getScalarOrVectorComponentCount(ResType);
3180 else if (ResType->getOpcode() == SPIRV::OpTypeArray)
3181 N = getArrayComponentCount(MRI, ResType);
3182 else
3183 report_fatal_error("Cannot select G_SPLAT_VECTOR with a non-vector result");
3184
3185 unsigned OpIdx = I.getNumExplicitDefs();
3186 if (!I.getOperand(OpIdx).isReg())
3187 report_fatal_error("Unexpected argument in G_SPLAT_VECTOR");
3188
3189 // check if we may construct a constant vector
3190 Register OpReg = I.getOperand(OpIdx).getReg();
3191 bool IsConst = isConstReg(MRI, OpReg);
3192
3193 if (!IsConst && N < 2)
3194 report_fatal_error(
3195 "There must be at least two constituent operands in a vector");
3196
3197 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3198 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3199 TII.get(IsConst ? SPIRV::OpConstantComposite
3200 : SPIRV::OpCompositeConstruct))
3201 .addDef(ResVReg)
3202 .addUse(GR.getSPIRVTypeID(ResType));
3203 for (unsigned i = 0; i < N; ++i)
3204 MIB.addUse(OpReg);
3205 MIB.constrainAllUses(TII, TRI, RBI);
3206 return true;
3207}
3208
3209bool SPIRVInstructionSelector::selectDiscard(Register ResVReg,
3210 SPIRVTypeInst ResType,
3211 MachineInstr &I) const {
3212
3213 unsigned Opcode;
3214
3215 if (STI.canUseExtension(
3216 SPIRV::Extension::SPV_EXT_demote_to_helper_invocation) ||
3217 STI.isAtLeastSPIRVVer(llvm::VersionTuple(1, 6))) {
3218 Opcode = SPIRV::OpDemoteToHelperInvocation;
3219 } else {
3220 Opcode = SPIRV::OpKill;
3221 // OpKill must be the last operation of any basic block.
3222 if (MachineInstr *NextI = I.getNextNode()) {
3223 GR.invalidateMachineInstr(NextI);
3224 NextI->eraseFromParent();
3225 }
3226 }
3227
3228 MachineBasicBlock &BB = *I.getParent();
3229 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3230 .constrainAllUses(TII, TRI, RBI);
3231 return true;
3232}
3233
3234bool SPIRVInstructionSelector::selectCmp(Register ResVReg,
3235 SPIRVTypeInst ResType, unsigned CmpOpc,
3236 MachineInstr &I) const {
3237 Register Cmp0 = I.getOperand(2).getReg();
3238 Register Cmp1 = I.getOperand(3).getReg();
3239 assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() ==
3240 GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() &&
3241 "CMP operands should have the same type");
3242 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc))
3243 .addDef(ResVReg)
3244 .addUse(GR.getSPIRVTypeID(ResType))
3245 .addUse(Cmp0)
3246 .addUse(Cmp1)
3247 .setMIFlags(I.getFlags())
3248 .constrainAllUses(TII, TRI, RBI);
3249 return true;
3250}
3251
3252bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
3253 SPIRVTypeInst ResType,
3254 MachineInstr &I) const {
3255 auto Pred = I.getOperand(1).getPredicate();
3256 unsigned CmpOpc;
3257
3258 Register CmpOperand = I.getOperand(2).getReg();
3259 if (GR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer))
3260 CmpOpc = getPtrCmpOpcode(Pred);
3261 else if (GR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool))
3262 CmpOpc = getBoolCmpOpcode(Pred);
3263 else
3264 CmpOpc = getICmpOpcode(Pred);
3265 return selectCmp(ResVReg, ResType, CmpOpc, I);
3266}
3267
3268Register
3269SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I,
3270 SPIRVTypeInst ResType) const {
3271 Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32);
3272 SPIRVTypeInst SpvI32Ty =
3273 ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII);
3274 // Find a constant in DT or build a new one.
3275 auto ConstInt = ConstantInt::get(LLVMTy, Val);
3276 Register NewReg = GR.find(ConstInt, GR.CurMF);
3277 if (!NewReg.isValid()) {
3278 NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
3279 MachineBasicBlock &BB = *I.getParent();
3280 MachineInstr *MI =
3281 Val == 0
3282 ? BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
3283 .addDef(NewReg)
3284 .addUse(GR.getSPIRVTypeID(SpvI32Ty))
3285 : BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI))
3286 .addDef(NewReg)
3287 .addUse(GR.getSPIRVTypeID(SpvI32Ty))
3288 .addImm(APInt(32, Val).getZExtValue());
3289 constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
3290 GR.add(ConstInt, MI);
3291 }
3292 return NewReg;
3293}
3294
3295bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
3296 SPIRVTypeInst ResType,
3297 MachineInstr &I) const {
3298 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate());
3299 return selectCmp(ResVReg, ResType, CmpOp, I);
3300}
3301
3302bool SPIRVInstructionSelector::selectExp10(Register ResVReg,
3303 SPIRVTypeInst ResType,
3304 MachineInstr &I) const {
3305 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
3306 return selectExtInst(ResVReg, ResType, I, CL::exp10);
3307 }
3308
3309 if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
3310 /// There is no exp10 in GLSL. Use exp10(x) = exp2(x * log2(10)) instead
3311 /// log2(10) ~= 3.3219280948874l
3312
3313 if (ResType->getOpcode() != SPIRV::OpTypeVector &&
3314 ResType->getOpcode() != SPIRV::OpTypeFloat)
3315 return false;
3316
3317 MachineIRBuilder MIRBuilder(I);
3318
3319 SPIRVTypeInst SpirvScalarType = ResType->getOpcode() == SPIRV::OpTypeVector
3320 ? SPIRVTypeInst(GR.getSPIRVTypeForVReg(
3321 ResType->getOperand(1).getReg()))
3322 : ResType;
3323
3324 assert(SpirvScalarType->getOperand(1).getImm() == 32 &&
3325 "only float operands supported by GLSL extended math");
3326
3327 Register ConstReg = GR.buildConstantFP(APFloat(3.3219280948874f),
3328 MIRBuilder, SpirvScalarType);
3329 Register ArgReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3330 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector
3331 ? SPIRV::OpVectorTimesScalar
3332 : SPIRV::OpFMulS;
3333
3334 if (!selectOpWithSrcs(ArgReg, ResType, I,
3335 {I.getOperand(1).getReg(), ConstReg}, Opcode))
3336 return false;
3337 if (!selectExtInst(ResVReg, ResType, I,
3338 {{SPIRV::InstructionSet::GLSL_std_450, GL::Exp2}}, false,
3339 false, {ArgReg}))
3340 return false;
3341
3342 return true;
3343 }
3344
3345 return false;
3346}
3347
3348Register SPIRVInstructionSelector::buildZerosVal(SPIRVTypeInst ResType,
3349 MachineInstr &I) const {
3350 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3351 bool ZeroAsNull = !STI.isShader();
3352 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3353 return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull);
3354 return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
3355}
3356
3357bool SPIRVInstructionSelector::isScalarOrVectorIntConstantZero(
3358 Register Reg) const {
3359 SPIRVTypeInst Type = GR.getSPIRVTypeForVReg(Reg);
3360 if (!Type)
3361 return false;
3362 SPIRVTypeInst CompType = GR.getScalarOrVectorComponentType(Type);
3363 if (!CompType || CompType->getOpcode() != SPIRV::OpTypeInt)
3364 return false;
3365
3366 auto IsZero = [this](Register Reg) {
3367 MachineInstr *Def = getDefInstrMaybeConstant(Reg, MRI);
3368 if (!Def)
3369 return false;
3370
3371 if (Def->getOpcode() == SPIRV::OpConstantNull)
3372 return true;
3373
3374 if (Def->getOpcode() == TargetOpcode::G_CONSTANT ||
3375 Def->getOpcode() == SPIRV::OpConstantI)
3376 return getIConstVal(Reg, MRI) == 0;
3377
3378 return false;
3379 };
3380
3381 if (IsZero(Reg))
3382 return true;
3383
3384 MachineInstr *Def = MRI->getVRegDef(Reg);
3385 if (!Def)
3386 return false;
3387
3388 if (Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
3389 (Def->getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
3390 cast<GIntrinsic>(Def)->getIntrinsicID() ==
3391 Intrinsic::spv_const_composite)) {
3392 unsigned StartOp = Def->getOpcode() == TargetOpcode::G_BUILD_VECTOR ? 1 : 2;
3393 for (unsigned i = StartOp; i < Def->getNumOperands(); ++i) {
3394 if (!IsZero(Def->getOperand(i).getReg()))
3395 return false;
3396 }
3397 return true;
3398 }
3399
3400 return false;
3401}
3402
3403Register SPIRVInstructionSelector::buildZerosValF(SPIRVTypeInst ResType,
3404 MachineInstr &I) const {
3405 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3406 bool ZeroAsNull = !STI.isShader();
3407 APFloat VZero = getZeroFP(GR.getTypeForSPIRVType(ResType));
3408 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3409 return GR.getOrCreateConstVector(VZero, I, ResType, TII, ZeroAsNull);
3410 return GR.getOrCreateConstFP(VZero, I, ResType, TII, ZeroAsNull);
3411}
3412
3413Register SPIRVInstructionSelector::buildOnesValF(SPIRVTypeInst ResType,
3414 MachineInstr &I) const {
3415 // OpenCL uses nulls for Zero. In HLSL we don't use null constants.
3416 bool ZeroAsNull = !STI.isShader();
3417 APFloat VOne = getOneFP(GR.getTypeForSPIRVType(ResType));
3418 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3419 return GR.getOrCreateConstVector(VOne, I, ResType, TII, ZeroAsNull);
3420 return GR.getOrCreateConstFP(VOne, I, ResType, TII, ZeroAsNull);
3421}
3422
3423Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes,
3424 SPIRVTypeInst ResType,
3425 MachineInstr &I) const {
3426 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
3427 APInt One =
3428 AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0);
3429 if (ResType->getOpcode() == SPIRV::OpTypeVector)
3430 return GR.getOrCreateConstVector(One, I, ResType, TII);
3431 return GR.getOrCreateConstInt(One, I, ResType, TII);
3432}
3433
3434bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
3435 SPIRVTypeInst ResType,
3436 MachineInstr &I) const {
3437 Register SelectFirstArg = I.getOperand(2).getReg();
3438 Register SelectSecondArg = I.getOperand(3).getReg();
3439 assert(ResType == GR.getSPIRVTypeForVReg(SelectFirstArg) &&
3440 ResType == GR.getSPIRVTypeForVReg(SelectSecondArg));
3441
3442 bool IsFloatTy =
3443 GR.isScalarOrVectorOfType(SelectFirstArg, SPIRV::OpTypeFloat);
3444 bool IsPtrTy =
3445 GR.isScalarOrVectorOfType(SelectFirstArg, SPIRV::OpTypePointer);
3446 bool IsVectorTy = GR.getSPIRVTypeForVReg(SelectFirstArg)->getOpcode() ==
3447 SPIRV::OpTypeVector;
3448
3449 bool IsScalarBool =
3450 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool);
3451 unsigned Opcode;
3452 if (IsVectorTy) {
3453 if (IsFloatTy) {
3454 Opcode = IsScalarBool ? SPIRV::OpSelectVFSCond : SPIRV::OpSelectVFVCond;
3455 } else if (IsPtrTy) {
3456 Opcode = IsScalarBool ? SPIRV::OpSelectVPSCond : SPIRV::OpSelectVPVCond;
3457 } else {
3458 Opcode = IsScalarBool ? SPIRV::OpSelectVISCond : SPIRV::OpSelectVIVCond;
3459 }
3460 } else {
3461 if (IsFloatTy) {
3462 Opcode = IsScalarBool ? SPIRV::OpSelectSFSCond : SPIRV::OpSelectVFVCond;
3463 } else if (IsPtrTy) {
3464 Opcode = IsScalarBool ? SPIRV::OpSelectSPSCond : SPIRV::OpSelectVPVCond;
3465 } else {
3466 Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
3467 }
3468 }
3469 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
3470 .addDef(ResVReg)
3471 .addUse(GR.getSPIRVTypeID(ResType))
3472 .addUse(I.getOperand(1).getReg())
3473 .addUse(SelectFirstArg)
3474 .addUse(SelectSecondArg)
3475 .constrainAllUses(TII, TRI, RBI);
3476 return true;
3477}
3478
3479// This function is used to extend a bool or a vector of bools into an integer
3480// or vector of integers.
3481bool SPIRVInstructionSelector::selectBoolToInt(Register ResVReg,
3482 SPIRVTypeInst ResType,
3483 Register BooleanVReg,
3484 MachineInstr &InsertAt,
3485 bool IsSigned) const {
3486 // To extend a bool, we need to use OpSelect between constants.
3487 Register ZeroReg = buildZerosVal(ResType, InsertAt);
3488 Register OneReg = buildOnesVal(IsSigned, ResType, InsertAt);
3489 bool IsScalarBool = GR.isScalarOfType(BooleanVReg, SPIRV::OpTypeBool);
3490 unsigned Opcode =
3491 IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
3492 BuildMI(*InsertAt.getParent(), InsertAt, InsertAt.getDebugLoc(),
3493 TII.get(Opcode))
3494 .addDef(ResVReg)
3495 .addUse(GR.getSPIRVTypeID(ResType))
3496 .addUse(BooleanVReg)
3497 .addUse(OneReg)
3498 .addUse(ZeroReg)
3499 .constrainAllUses(TII, TRI, RBI);
3500 return true;
3501}
3502
3503bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
3504 SPIRVTypeInst ResType,
3505 MachineInstr &I, bool IsSigned,
3506 unsigned Opcode) const {
3507 Register SrcReg = I.getOperand(1).getReg();
3508 // We can convert bool value directly to float type without OpConvert*ToF,
3509 // however the translator generates OpSelect+OpConvert*ToF, so we do the same.
3510 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) {
3511 unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType);
3512 SPIRVTypeInst TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII);
3513 if (ResType->getOpcode() == SPIRV::OpTypeVector) {
3514 const unsigned NumElts = ResType->getOperand(2).getImm();
3515 TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
3516 }
3517 SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
3518 selectBoolToInt(SrcReg, TmpType, I.getOperand(1).getReg(), I, false);
3519 }
3520 return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
3521}
3522
3523bool SPIRVInstructionSelector::selectExt(Register ResVReg,
3524 SPIRVTypeInst ResType, MachineInstr &I,
3525 bool IsSigned) const {
3526 Register SrcReg = I.getOperand(1).getReg();
3527 if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool))
3528 return selectBoolToInt(ResVReg, ResType, I.getOperand(1).getReg(), I,
3529 IsSigned);
3530
3531 SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
3532 if (ResType == SrcType)
3533 return BuildCOPY(ResVReg, SrcReg, I);
3534
3535 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
3536 return selectUnOp(ResVReg, ResType, I, Opcode);
3537}
3538
3539bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg,
3540 SPIRVTypeInst ResType,
3541 MachineInstr &I,
3542 bool IsSigned) const {
3543 MachineIRBuilder MIRBuilder(I);
3544 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
3545 MachineBasicBlock &BB = *I.getParent();
3546 // Ensure we have bool.
3547 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
3548 unsigned N = GR.getScalarOrVectorComponentCount(ResType);
3549 if (N > 1)
3550 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
3551 Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
3552 // Build less-than-equal and less-than.
3553 // TODO: replace with one-liner createVirtualRegister() from
3554 // llvm/lib/Target/SPIRV/SPIRVUtils.cpp when PR #116609 is merged.
3555 Register IsLessEqReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3556 MRI->setType(IsLessEqReg, LLT::scalar(64));
3557 GR.assignSPIRVTypeToVReg(ResType, IsLessEqReg, MIRBuilder.getMF());
3558 BuildMI(BB, I, I.getDebugLoc(),
3559 TII.get(IsSigned ? SPIRV::OpSLessThanEqual : SPIRV::OpULessThanEqual))
3560 .addDef(IsLessEqReg)
3561 .addUse(BoolTypeReg)
3562 .addUse(I.getOperand(1).getReg())
3563 .addUse(I.getOperand(2).getReg())
3564 .constrainAllUses(TII, TRI, RBI);
3565 Register IsLessReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
3566 MRI->setType(IsLessReg, LLT::scalar(64));
3567 GR.assignSPIRVTypeToVReg(ResType, IsLessReg, MIRBuilder.getMF());
3568 BuildMI(BB, I, I.getDebugLoc(),
3569 TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan))
3570 .addDef(IsLessReg)
3571 .addUse(BoolTypeReg)
3572 .addUse(I.getOperand(1).getReg())
3573 .addUse(I.getOperand(2).getReg())
3574 .constrainAllUses(TII, TRI, RBI);
3575 // Build selects.
3576 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
3577 Register NegOneOrZeroReg =
3578 MRI->createVirtualRegister(GR.getRegClass(ResType));
3579 MRI->setType(NegOneOrZeroReg, LLT::scalar(64));
3580 GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF());
3581 unsigned SelectOpcode =
3582 N > 1 ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond;
3583 BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
3584 .addDef(NegOneOrZeroReg)
3585 .addUse(ResTypeReg)
3586 .addUse(IsLessReg)
3587 .addUse(buildOnesVal(true, ResType, I)) // -1
3588 .addUse(buildZerosVal(ResType, I))
3589 .constrainAllUses(TII, TRI, RBI);
3590 BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
3591 .addDef(ResVReg)
3592 .addUse(ResTypeReg)
3593 .addUse(IsLessEqReg)
3594 .addUse(NegOneOrZeroReg) // -1 or 0
3595 .addUse(buildOnesVal(false, ResType, I))
3596 .constrainAllUses(TII, TRI, RBI);
3597 return true;
3598}
3599
3600bool SPIRVInstructionSelector::selectIntToBool(Register IntReg,
3601 Register ResVReg,
3602 MachineInstr &I,
3603 SPIRVTypeInst IntTy,
3604 SPIRVTypeInst BoolTy) const {
3605 // To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero.
3606 Register BitIntReg = createVirtualRegister(IntTy, &GR, MRI, MRI->getMF());
3607 bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector;
3608 unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS;
3609 Register Zero = buildZerosVal(IntTy, I);
3610 Register One = buildOnesVal(false, IntTy, I);
3611 MachineBasicBlock &BB = *I.getParent();
3612 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
3613 .addDef(BitIntReg)
3614 .addUse(GR.getSPIRVTypeID(IntTy))
3615 .addUse(IntReg)
3616 .addUse(One)
3617 .constrainAllUses(TII, TRI, RBI);
3618 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual))
3619 .addDef(ResVReg)
3620 .addUse(GR.getSPIRVTypeID(BoolTy))
3621 .addUse(BitIntReg)
3622 .addUse(Zero)
3623 .constrainAllUses(TII, TRI, RBI);
3624 return true;
3625}
3626
3627bool SPIRVInstructionSelector::selectTrunc(Register ResVReg,
3628 SPIRVTypeInst ResType,
3629 MachineInstr &I) const {
3630 Register IntReg = I.getOperand(1).getReg();
3631 const SPIRVTypeInst ArgType = GR.getSPIRVTypeForVReg(IntReg);
3632 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool))
3633 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType);
3634 if (ArgType == ResType)
3635 return BuildCOPY(ResVReg, IntReg, I);
3636 bool IsSigned = GR.isScalarOrVectorSigned(ResType);
3637 unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
3638 return selectUnOp(ResVReg, ResType, I, Opcode);
3639}
3640
3641bool SPIRVInstructionSelector::selectConst(Register ResVReg,
3642 SPIRVTypeInst ResType,
3643 MachineInstr &I) const {
3644 unsigned Opcode = I.getOpcode();
3645 unsigned TpOpcode = ResType->getOpcode();
3646 Register Reg;
3647 if (TpOpcode == SPIRV::OpTypePointer || TpOpcode == SPIRV::OpTypeEvent) {
3648 assert(Opcode == TargetOpcode::G_CONSTANT &&
3649 I.getOperand(1).getCImm()->isZero());
3650 MachineBasicBlock &DepMBB = I.getMF()->front();
3651 MachineIRBuilder MIRBuilder(DepMBB, DepMBB.getFirstNonPHI());
3652 Reg = GR.getOrCreateConstNullPtr(MIRBuilder, ResType);
3653 } else if (Opcode == TargetOpcode::G_FCONSTANT) {
3654 Reg = GR.getOrCreateConstFP(I.getOperand(1).getFPImm()->getValue(), I,
3655 ResType, TII, !STI.isShader());
3656 } else {
3657 Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getValue(), I,
3658 ResType, TII, !STI.isShader());
3659 }
3660 return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I);
3661}
3662
3663bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg,
3664 SPIRVTypeInst ResType,
3665 MachineInstr &I) const {
3666 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
3667 .addDef(ResVReg)
3668 .addUse(GR.getSPIRVTypeID(ResType))
3669 .constrainAllUses(TII, TRI, RBI);
3670 return true;
3671}
3672
3673bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg,
3674 SPIRVTypeInst ResType,
3675 MachineInstr &I) const {
3676 MachineBasicBlock &BB = *I.getParent();
3677 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert))
3678 .addDef(ResVReg)
3679 .addUse(GR.getSPIRVTypeID(ResType))
3680 // object to insert
3681 .addUse(I.getOperand(3).getReg())
3682 // composite to insert into
3683 .addUse(I.getOperand(2).getReg());
3684 for (unsigned i = 4; i < I.getNumOperands(); i++)
3685 MIB.addImm(foldImm(I.getOperand(i), MRI));
3686 MIB.constrainAllUses(TII, TRI, RBI);
3687 return true;
3688}
3689
3690bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg,
3691 SPIRVTypeInst ResType,
3692 MachineInstr &I) const {
3693 Type *MaybeResTy = nullptr;
3694 StringRef ResName;
3695 if (GR.findValueAttrs(&I, MaybeResTy, ResName) &&
3696 MaybeResTy != GR.getTypeForSPIRVType(ResType)) {
3697 assert((!MaybeResTy || MaybeResTy->isAggregateType()) &&
3698 "Expected aggregate type for extractv instruction");
3699 ResType = GR.getOrCreateSPIRVType(MaybeResTy, I,
3700 SPIRV::AccessQualifier::ReadWrite, false);
3701 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *I.getMF());
3702 }
3703 MachineBasicBlock &BB = *I.getParent();
3704 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
3705 .addDef(ResVReg)
3706 .addUse(GR.getSPIRVTypeID(ResType))
3707 .addUse(I.getOperand(2).getReg());
3708 for (unsigned i = 3; i < I.getNumOperands(); i++)
3709 MIB.addImm(foldImm(I.getOperand(i), MRI));
3710 MIB.constrainAllUses(TII, TRI, RBI);
3711 return true;
3712}
3713
3714bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg,
3715 SPIRVTypeInst ResType,
3716 MachineInstr &I) const {
3717 if (getImm(I.getOperand(4), MRI))
3718 return selectInsertVal(ResVReg, ResType, I);
3719 MachineBasicBlock &BB = *I.getParent();
3720 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic))
3721 .addDef(ResVReg)
3722 .addUse(GR.getSPIRVTypeID(ResType))
3723 .addUse(I.getOperand(2).getReg())
3724 .addUse(I.getOperand(3).getReg())
3725 .addUse(I.getOperand(4).getReg())
3726 .constrainAllUses(TII, TRI, RBI);
3727 return true;
3728}
3729
3730bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg,
3731 SPIRVTypeInst ResType,
3732 MachineInstr &I) const {
3733 if (getImm(I.getOperand(3), MRI))
3734 return selectExtractVal(ResVReg, ResType, I);
3735 MachineBasicBlock &BB = *I.getParent();
3736 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic))
3737 .addDef(ResVReg)
3738 .addUse(GR.getSPIRVTypeID(ResType))
3739 .addUse(I.getOperand(2).getReg())
3740 .addUse(I.getOperand(3).getReg())
3741 .constrainAllUses(TII, TRI, RBI);
3742 return true;
3743}
3744
3745bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
3746 SPIRVTypeInst ResType,
3747 MachineInstr &I) const {
3748 const bool IsGEPInBounds = I.getOperand(2).getImm();
3749
3750 // OpAccessChain could be used for OpenCL, but the SPIRV-LLVM Translator only
3751 // relies on PtrAccessChain, so we'll try not to deviate. For Vulkan however,
3752 // we have to use Op[InBounds]AccessChain.
3753 const unsigned Opcode = STI.isLogicalSPIRV()
3754 ? (IsGEPInBounds ? SPIRV::OpInBoundsAccessChain
3755 : SPIRV::OpAccessChain)
3756 : (IsGEPInBounds ? SPIRV::OpInBoundsPtrAccessChain
3757 : SPIRV::OpPtrAccessChain);
3758
3759 auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
3760 .addDef(ResVReg)
3761 .addUse(GR.getSPIRVTypeID(ResType))
3762 // Object to get a pointer to.
3763 .addUse(I.getOperand(3).getReg());
3764 assert(
3765 (Opcode == SPIRV::OpPtrAccessChain ||
3766 Opcode == SPIRV::OpInBoundsPtrAccessChain ||
3767 (getImm(I.getOperand(4), MRI) && foldImm(I.getOperand(4), MRI) == 0)) &&
3768 "Cannot translate GEP to OpAccessChain. First index must be 0.");
3769
3770 // Adding indices.
3771 const unsigned StartingIndex =
3772 (Opcode == SPIRV::OpAccessChain || Opcode == SPIRV::OpInBoundsAccessChain)
3773 ? 5
3774 : 4;
3775 for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i)
3776 Res.addUse(I.getOperand(i).getReg());
3777 Res.constrainAllUses(TII, TRI, RBI);
3778 return true;
3779}
3780
3781// Maybe wrap a value into OpSpecConstantOp
3782bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
3783 MachineInstr &I, SmallVector<Register> &CompositeArgs) const {
3784 unsigned Lim = I.getNumExplicitOperands();
3785 for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) {
3786 Register OpReg = I.getOperand(i).getReg();
3787 MachineInstr *OpDefine = MRI->getVRegDef(OpReg);
3788 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
3789 if (!OpDefine || !OpType || isConstReg(MRI, OpDefine) ||
3790 OpDefine->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST ||
3791 OpDefine->getOpcode() == TargetOpcode::G_INTTOPTR ||
3792 GR.isAggregateType(OpType)) {
3793 // The case of G_ADDRSPACE_CAST inside spv_const_composite() is processed
3794 // by selectAddrSpaceCast(), and G_INTTOPTR is processed by selectUnOp()
3795 CompositeArgs.push_back(OpReg);
3796 continue;
3797 }
3798 MachineFunction *MF = I.getMF();
3799 Register WrapReg = GR.find(OpDefine, MF);
3800 if (WrapReg.isValid()) {
3801 CompositeArgs.push_back(WrapReg);
3802 continue;
3803 }
3804 // Create a new register for the wrapper
3805 WrapReg = MRI->createVirtualRegister(GR.getRegClass(OpType));
3806 CompositeArgs.push_back(WrapReg);
3807 // Decorate the wrapper register and generate a new instruction
3808 MRI->setType(WrapReg, LLT::pointer(0, 64));
3809 GR.assignSPIRVTypeToVReg(OpType, WrapReg, *MF);
3810 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3811 TII.get(SPIRV::OpSpecConstantOp))
3812 .addDef(WrapReg)
3813 .addUse(GR.getSPIRVTypeID(OpType))
3814 .addImm(static_cast<uint32_t>(SPIRV::Opcode::Bitcast))
3815 .addUse(OpReg);
3816 GR.add(OpDefine, MIB);
3817 MIB.constrainAllUses(TII, TRI, RBI);
3818 }
3819 return true;
3820}
3821
3822bool SPIRVInstructionSelector::selectDerivativeInst(
3823 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
3824 const unsigned DPdOpCode) const {
3825 // TODO: This should check specifically for Fragment Execution Model, but STI
3826 // doesn't provide that information yet. See #167562
3827 errorIfInstrOutsideShader(I);
3828
3829 // If the arg/result types are half then we need to wrap the instr in
3830 // conversions to float
3831 // This case occurs because a half arg/result is legal in HLSL but not spirv.
3832 Register SrcReg = I.getOperand(2).getReg();
3833 SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
3834 unsigned BitWidth = std::min(GR.getScalarOrVectorBitWidth(SrcType),
3835 GR.getScalarOrVectorBitWidth(ResType));
3836 if (BitWidth == 32)
3837 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
3838 .addDef(ResVReg)
3839 .addUse(GR.getSPIRVTypeID(ResType))
3840 .addUse(I.getOperand(2).getReg());
3841
3842 MachineIRBuilder MIRBuilder(I);
3843 unsigned componentCount = GR.getScalarOrVectorComponentCount(SrcType);
3844 SPIRVTypeInst F32ConvertTy = GR.getOrCreateSPIRVFloatType(32, I, TII);
3845 if (componentCount != 1)
3846 F32ConvertTy = GR.getOrCreateSPIRVVectorType(F32ConvertTy, componentCount,
3847 MIRBuilder, false);
3848
3849 const TargetRegisterClass *RegClass = GR.getRegClass(SrcType);
3850 Register ConvertToVReg = MRI->createVirtualRegister(RegClass);
3851 Register DpdOpVReg = MRI->createVirtualRegister(RegClass);
3852
3853 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
3854 .addDef(ConvertToVReg)
3855 .addUse(GR.getSPIRVTypeID(F32ConvertTy))
3856 .addUse(SrcReg)
3857 .constrainAllUses(TII, TRI, RBI);
3858 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
3859 .addDef(DpdOpVReg)
3860 .addUse(GR.getSPIRVTypeID(F32ConvertTy))
3861 .addUse(ConvertToVReg)
3862 .constrainAllUses(TII, TRI, RBI);
3863 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
3864 .addDef(ResVReg)
3865 .addUse(GR.getSPIRVTypeID(ResType))
3866 .addUse(DpdOpVReg)
3867 .constrainAllUses(TII, TRI, RBI);
3868 return true;
3869}
3870
3871bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
3872 SPIRVTypeInst ResType,
3873 MachineInstr &I) const {
3874 MachineBasicBlock &BB = *I.getParent();
3875 Intrinsic::ID IID = cast<GIntrinsic>(I).getIntrinsicID();
3876 switch (IID) {
3877 case Intrinsic::spv_load:
3878 return selectLoad(ResVReg, ResType, I);
3879 case Intrinsic::spv_store:
3880 return selectStore(I);
3881 case Intrinsic::spv_extractv:
3882 return selectExtractVal(ResVReg, ResType, I);
3883 case Intrinsic::spv_insertv:
3884 return selectInsertVal(ResVReg, ResType, I);
3885 case Intrinsic::spv_extractelt:
3886 return selectExtractElt(ResVReg, ResType, I);
3887 case Intrinsic::spv_insertelt:
3888 return selectInsertElt(ResVReg, ResType, I);
3889 case Intrinsic::spv_gep:
3890 return selectGEP(ResVReg, ResType, I);
3891 case Intrinsic::spv_bitcast: {
3892 Register OpReg = I.getOperand(2).getReg();
3893 SPIRVTypeInst OpType =
3894 OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr;
3895 if (!GR.isBitcastCompatible(ResType, OpType))
3896 report_fatal_error("incompatible result and operand types in a bitcast");
3897 return selectOpWithSrcs(ResVReg, ResType, I, {OpReg}, SPIRV::OpBitcast);
3898 }
3899 case Intrinsic::spv_unref_global:
3900 case Intrinsic::spv_init_global: {
3901 MachineInstr *MI = MRI->getVRegDef(I.getOperand(1).getReg());
3902 MachineInstr *Init = I.getNumExplicitOperands() > 2
3903 ? MRI->getVRegDef(I.getOperand(2).getReg())
3904 : nullptr;
3905 assert(MI);
3906 Register GVarVReg = MI->getOperand(0).getReg();
3907 if (!selectGlobalValue(GVarVReg, *MI, Init))
3908 return false;
3909 // We violate SSA form by inserting OpVariable and still having a gMIR
3910 // instruction %vreg = G_GLOBAL_VALUE @gvar. We need to fix this by erasing
3911 // the duplicated definition.
3912 if (MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE) {
3913 GR.invalidateMachineInstr(MI);
3914 MI->eraseFromParent();
3915 }
3916 return true;
3917 }
3918 case Intrinsic::spv_undef: {
3919 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
3920 .addDef(ResVReg)
3921 .addUse(GR.getSPIRVTypeID(ResType));
3922 MIB.constrainAllUses(TII, TRI, RBI);
3923 return true;
3924 }
3925 case Intrinsic::spv_const_composite: {
3926 // If no values are attached, the composite is null constant.
3927 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands();
3928 SmallVector<Register> CompositeArgs;
3929 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
3930
3931 // skip type MD node we already used when generated assign.type for this
3932 if (!IsNull) {
3933 if (!wrapIntoSpecConstantOp(I, CompositeArgs))
3934 return false;
3935 MachineIRBuilder MIR(I);
3936 SmallVector<MachineInstr *, 4> Instructions = createContinuedInstructions(
3937 MIR, SPIRV::OpConstantComposite, 3,
3938 SPIRV::OpConstantCompositeContinuedINTEL, CompositeArgs, ResVReg,
3939 GR.getSPIRVTypeID(ResType));
3940 for (auto *Instr : Instructions) {
3941 Instr->setDebugLoc(I.getDebugLoc());
3942 constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI);
3943 }
3944 return true;
3945 } else {
3946 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
3947 .addDef(ResVReg)
3948 .addUse(GR.getSPIRVTypeID(ResType));
3949 MIB.constrainAllUses(TII, TRI, RBI);
3950 return true;
3951 }
3952 }
3953 case Intrinsic::spv_assign_name: {
3954 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName));
3955 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg());
3956 for (unsigned i = I.getNumExplicitDefs() + 2;
3957 i < I.getNumExplicitOperands(); ++i) {
3958 MIB.addImm(I.getOperand(i).getImm());
3959 }
3960 MIB.constrainAllUses(TII, TRI, RBI);
3961 return true;
3962 }
3963 case Intrinsic::spv_switch: {
3964 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch));
3965 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) {
3966 if (I.getOperand(i).isReg())
3967 MIB.addReg(I.getOperand(i).getReg());
3968 else if (I.getOperand(i).isCImm())
3969 addNumImm(I.getOperand(i).getCImm()->getValue(), MIB);
3970 else if (I.getOperand(i).isMBB())
3971 MIB.addMBB(I.getOperand(i).getMBB());
3972 else
3973 llvm_unreachable("Unexpected OpSwitch operand");
3974 }
3975 MIB.constrainAllUses(TII, TRI, RBI);
3976 return true;
3977 }
3978 case Intrinsic::spv_loop_merge: {
3979 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopMerge));
3980 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) {
3981 if (I.getOperand(i).isMBB())
3982 MIB.addMBB(I.getOperand(i).getMBB());
3983 else
3984 MIB.addImm(foldImm(I.getOperand(i), MRI));
3985 }
3986 MIB.constrainAllUses(TII, TRI, RBI);
3987 return true;
3988 }
3989 case Intrinsic::spv_loop_control_intel: {
3990 auto MIB =
3991 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopControlINTEL));
3992 for (unsigned J = 1; J < I.getNumExplicitOperands(); ++J)
3993 MIB.addImm(foldImm(I.getOperand(J), MRI));
3994 MIB.constrainAllUses(TII, TRI, RBI);
3995 return true;
3996 }
3997 case Intrinsic::spv_selection_merge: {
3998 auto MIB =
3999 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSelectionMerge));
4000 assert(I.getOperand(1).isMBB() &&
4001 "operand 1 to spv_selection_merge must be a basic block");
4002 MIB.addMBB(I.getOperand(1).getMBB());
4003 MIB.addImm(getSelectionOperandForImm(I.getOperand(2).getImm()));
4004 MIB.constrainAllUses(TII, TRI, RBI);
4005 return true;
4006 }
4007 case Intrinsic::spv_cmpxchg:
4008 return selectAtomicCmpXchg(ResVReg, ResType, I);
4009 case Intrinsic::spv_unreachable:
4010 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable))
4011 .constrainAllUses(TII, TRI, RBI);
4012 return true;
4013 case Intrinsic::spv_alloca:
4014 return selectFrameIndex(ResVReg, ResType, I);
4015 case Intrinsic::spv_alloca_array:
4016 return selectAllocaArray(ResVReg, ResType, I);
4017 case Intrinsic::spv_assume:
4018 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
4019 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR))
4020 .addUse(I.getOperand(1).getReg())
4021 .constrainAllUses(TII, TRI, RBI);
4022 return true;
4023 }
4024 break;
4025 case Intrinsic::spv_expect:
4026 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
4027 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR))
4028 .addDef(ResVReg)
4029 .addUse(GR.getSPIRVTypeID(ResType))
4030 .addUse(I.getOperand(2).getReg())
4031 .addUse(I.getOperand(3).getReg())
4032 .constrainAllUses(TII, TRI, RBI);
4033 return true;
4034 }
4035 break;
4036 case Intrinsic::arithmetic_fence:
4037 if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) {
4038 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpArithmeticFenceEXT))
4039 .addDef(ResVReg)
4040 .addUse(GR.getSPIRVTypeID(ResType))
4041 .addUse(I.getOperand(2).getReg())
4042 .constrainAllUses(TII, TRI, RBI);
4043 return true;
4044 } else
4045 return BuildCOPY(ResVReg, I.getOperand(2).getReg(), I);
4046 break;
4047 case Intrinsic::spv_thread_id:
4048 // The HLSL SV_DispatchThreadID semantic is lowered to llvm.spv.thread.id
4049 // intrinsic in LLVM IR for SPIR-V backend.
4050 //
4051 // In SPIR-V backend, llvm.spv.thread.id is now correctly translated to a
4052 // `GlobalInvocationId` builtin variable
4053 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalInvocationId, ResVReg,
4054 ResType, I);
4055 case Intrinsic::spv_thread_id_in_group:
4056 // The HLSL SV_GroupThreadId semantic is lowered to
4057 // llvm.spv.thread.id.in.group intrinsic in LLVM IR for SPIR-V backend.
4058 //
4059 // In SPIR-V backend, llvm.spv.thread.id.in.group is now correctly
4060 // translated to a `LocalInvocationId` builtin variable
4061 return loadVec3BuiltinInputID(SPIRV::BuiltIn::LocalInvocationId, ResVReg,
4062 ResType, I);
4063 case Intrinsic::spv_group_id:
4064 // The HLSL SV_GroupId semantic is lowered to
4065 // llvm.spv.group.id intrinsic in LLVM IR for SPIR-V backend.
4066 //
4067 // In SPIR-V backend, llvm.spv.group.id is now translated to a `WorkgroupId`
4068 // builtin variable
4069 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupId, ResVReg, ResType,
4070 I);
4071 case Intrinsic::spv_flattened_thread_id_in_group:
4072 // The HLSL SV_GroupIndex semantic is lowered to
4073 // llvm.spv.flattened.thread.id.in.group() intrinsic in LLVM IR for SPIR-V
4074 // backend.
4075 //
4076 // In SPIR-V backend, llvm.spv.flattened.thread.id.in.group is translated to
4077 // a `LocalInvocationIndex` builtin variable
4078 return loadBuiltinInputID(SPIRV::BuiltIn::LocalInvocationIndex, ResVReg,
4079 ResType, I);
4080 case Intrinsic::spv_workgroup_size:
4081 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupSize, ResVReg,
4082 ResType, I);
4083 case Intrinsic::spv_global_size:
4084 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalSize, ResVReg, ResType,
4085 I);
4086 case Intrinsic::spv_global_offset:
4087 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalOffset, ResVReg,
4088 ResType, I);
4089 case Intrinsic::spv_num_workgroups:
4090 return loadVec3BuiltinInputID(SPIRV::BuiltIn::NumWorkgroups, ResVReg,
4091 ResType, I);
4092 case Intrinsic::spv_subgroup_size:
4093 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupSize, ResVReg, ResType,
4094 I);
4095 case Intrinsic::spv_num_subgroups:
4096 return loadBuiltinInputID(SPIRV::BuiltIn::NumSubgroups, ResVReg, ResType,
4097 I);
4098 case Intrinsic::spv_subgroup_id:
4099 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupId, ResVReg, ResType, I);
4100 case Intrinsic::spv_subgroup_local_invocation_id:
4101 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupLocalInvocationId,
4102 ResVReg, ResType, I);
4103 case Intrinsic::spv_subgroup_max_size:
4104 return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupMaxSize, ResVReg, ResType,
4105 I);
4106 case Intrinsic::spv_fdot:
4107 return selectFloatDot(ResVReg, ResType, I);
4108 case Intrinsic::spv_udot:
4109 case Intrinsic::spv_sdot:
4110 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4111 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4112 return selectIntegerDot(ResVReg, ResType, I,
4113 /*Signed=*/IID == Intrinsic::spv_sdot);
4114 return selectIntegerDotExpansion(ResVReg, ResType, I);
4115 case Intrinsic::spv_dot4add_i8packed:
4116 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4117 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4118 return selectDot4AddPacked<true>(ResVReg, ResType, I);
4119 return selectDot4AddPackedExpansion<true>(ResVReg, ResType, I);
4120 case Intrinsic::spv_dot4add_u8packed:
4121 if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_integer_dot_product) ||
4122 STI.isAtLeastSPIRVVer(VersionTuple(1, 6)))
4123 return selectDot4AddPacked<false>(ResVReg, ResType, I);
4124 return selectDot4AddPackedExpansion<false>(ResVReg, ResType, I);
4125 case Intrinsic::spv_all:
4126 return selectAll(ResVReg, ResType, I);
4127 case Intrinsic::spv_any:
4128 return selectAny(ResVReg, ResType, I);
4129 case Intrinsic::spv_cross:
4130 return selectExtInst(ResVReg, ResType, I, CL::cross, GL::Cross);
4131 case Intrinsic::spv_distance:
4132 return selectExtInst(ResVReg, ResType, I, CL::distance, GL::Distance);
4133 case Intrinsic::spv_lerp:
4134 return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix);
4135 case Intrinsic::spv_length:
4136 return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length);
4137 case Intrinsic::spv_degrees:
4138 return selectExtInst(ResVReg, ResType, I, CL::degrees, GL::Degrees);
4139 case Intrinsic::spv_faceforward:
4140 return selectExtInst(ResVReg, ResType, I, GL::FaceForward);
4141 case Intrinsic::spv_frac:
4142 return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
4143 case Intrinsic::spv_isinf:
4144 return selectOpIsInf(ResVReg, ResType, I);
4145 case Intrinsic::spv_isnan:
4146 return selectOpIsNan(ResVReg, ResType, I);
4147 case Intrinsic::spv_normalize:
4148 return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
4149 case Intrinsic::spv_refract:
4150 return selectExtInst(ResVReg, ResType, I, GL::Refract);
4151 case Intrinsic::spv_reflect:
4152 return selectExtInst(ResVReg, ResType, I, GL::Reflect);
4153 case Intrinsic::spv_rsqrt:
4154 return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
4155 case Intrinsic::spv_sign:
4156 return selectSign(ResVReg, ResType, I);
4157 case Intrinsic::spv_smoothstep:
4158 return selectExtInst(ResVReg, ResType, I, CL::smoothstep, GL::SmoothStep);
4159 case Intrinsic::spv_firstbituhigh: // There is no CL equivalent of FindUMsb
4160 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/false);
4161 case Intrinsic::spv_firstbitshigh: // There is no CL equivalent of FindSMsb
4162 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true);
4163 case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb
4164 return selectFirstBitLow(ResVReg, ResType, I);
4165 case Intrinsic::spv_group_memory_barrier_with_group_sync: {
4166 Register MemSemReg =
4167 buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I);
4168 Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I);
4169 MachineBasicBlock &BB = *I.getParent();
4170 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier))
4171 .addUse(ScopeReg)
4172 .addUse(ScopeReg)
4173 .addUse(MemSemReg)
4174 .constrainAllUses(TII, TRI, RBI);
4175 return true;
4176 }
4177 case Intrinsic::spv_generic_cast_to_ptr_explicit: {
4178 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg();
4179 SPIRV::StorageClass::StorageClass ResSC =
4180 GR.getPointerStorageClass(ResType);
4181 if (!isGenericCastablePtr(ResSC))
4182 report_fatal_error("The target storage class is not castable from the "
4183 "Generic storage class");
4184 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpGenericCastToPtrExplicit))
4185 .addDef(ResVReg)
4186 .addUse(GR.getSPIRVTypeID(ResType))
4187 .addUse(PtrReg)
4188 .addImm(ResSC)
4189 .constrainAllUses(TII, TRI, RBI);
4190 return true;
4191 }
4192 case Intrinsic::spv_lifetime_start:
4193 case Intrinsic::spv_lifetime_end: {
4194 unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart
4195 : SPIRV::OpLifetimeStop;
4196 int64_t Size = I.getOperand(I.getNumExplicitDefs() + 1).getImm();
4197 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg();
4198 if (Size == -1)
4199 Size = 0;
4200 BuildMI(BB, I, I.getDebugLoc(), TII.get(Op))
4201 .addUse(PtrReg)
4202 .addImm(Size)
4203 .constrainAllUses(TII, TRI, RBI);
4204 return true;
4205 }
4206 case Intrinsic::spv_saturate:
4207 return selectSaturate(ResVReg, ResType, I);
4208 case Intrinsic::spv_nclamp:
4209 return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp);
4210 case Intrinsic::spv_uclamp:
4211 return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
4212 case Intrinsic::spv_sclamp:
4213 return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
4214 case Intrinsic::spv_subgroup_prefix_bit_count:
4215 return selectWavePrefixBitCount(ResVReg, ResType, I);
4216 case Intrinsic::spv_wave_active_countbits:
4217 return selectWaveActiveCountBits(ResVReg, ResType, I);
4218 case Intrinsic::spv_wave_all_equal:
4219 return selectWaveActiveAllEqual(ResVReg, ResType, I);
4220 case Intrinsic::spv_wave_all:
4221 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAll);
4222 case Intrinsic::spv_wave_any:
4223 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
4224 case Intrinsic::spv_subgroup_ballot:
4225 return selectWaveOpInst(ResVReg, ResType, I,
4226 SPIRV::OpGroupNonUniformBallot);
4227 case Intrinsic::spv_wave_is_first_lane:
4228 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
4229 case Intrinsic::spv_wave_reduce_umax:
4230 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true);
4231 case Intrinsic::spv_wave_reduce_max:
4232 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ false);
4233 case Intrinsic::spv_wave_reduce_umin:
4234 return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ true);
4235 case Intrinsic::spv_wave_reduce_min:
4236 return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ false);
4237 case Intrinsic::spv_wave_reduce_sum:
4238 return selectWaveReduceSum(ResVReg, ResType, I);
4239 case Intrinsic::spv_wave_readlane:
4240 return selectWaveOpInst(ResVReg, ResType, I,
4241 SPIRV::OpGroupNonUniformShuffle);
4242 case Intrinsic::spv_wave_prefix_sum:
4243 return selectWaveExclusiveScanSum(ResVReg, ResType, I);
4244 case Intrinsic::spv_wave_prefix_product:
4245 return selectWaveExclusiveScanProduct(ResVReg, ResType, I);
4246 case Intrinsic::spv_step:
4247 return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
4248 case Intrinsic::spv_radians:
4249 return selectExtInst(ResVReg, ResType, I, CL::radians, GL::Radians);
4250 // Discard intrinsics which we do not expect to actually represent code after
4251 // lowering or intrinsics which are not implemented but should not crash when
4252 // found in a customer's LLVM IR input.
4253 case Intrinsic::instrprof_increment:
4254 case Intrinsic::instrprof_increment_step:
4255 case Intrinsic::instrprof_value_profile:
4256 break;
4257 // Discard internal intrinsics.
4258 case Intrinsic::spv_value_md:
4259 break;
4260 case Intrinsic::spv_resource_handlefrombinding: {
4261 return selectHandleFromBinding(ResVReg, ResType, I);
4262 }
4263 case Intrinsic::spv_resource_counterhandlefrombinding:
4264 return selectCounterHandleFromBinding(ResVReg, ResType, I);
4265 case Intrinsic::spv_resource_updatecounter:
4266 return selectUpdateCounter(ResVReg, ResType, I);
4267 case Intrinsic::spv_resource_store_typedbuffer: {
4268 return selectImageWriteIntrinsic(I);
4269 }
4270 case Intrinsic::spv_resource_load_typedbuffer: {
4271 return selectReadImageIntrinsic(ResVReg, ResType, I);
4272 }
4273 case Intrinsic::spv_resource_sample:
4274 case Intrinsic::spv_resource_sample_clamp:
4275 return selectSampleBasicIntrinsic(ResVReg, ResType, I);
4276 case Intrinsic::spv_resource_samplebias:
4277 case Intrinsic::spv_resource_samplebias_clamp:
4278 return selectSampleBiasIntrinsic(ResVReg, ResType, I);
4279 case Intrinsic::spv_resource_samplegrad:
4280 case Intrinsic::spv_resource_samplegrad_clamp:
4281 return selectSampleGradIntrinsic(ResVReg, ResType, I);
4282 case Intrinsic::spv_resource_samplelevel:
4283 return selectSampleLevelIntrinsic(ResVReg, ResType, I);
4284 case Intrinsic::spv_resource_samplecmp:
4285 case Intrinsic::spv_resource_samplecmp_clamp:
4286 return selectSampleCmpIntrinsic(ResVReg, ResType, I);
4287 case Intrinsic::spv_resource_samplecmplevelzero:
4288 return selectSampleCmpLevelZeroIntrinsic(ResVReg, ResType, I);
4289 case Intrinsic::spv_resource_gather:
4290 case Intrinsic::spv_resource_gather_cmp:
4291 return selectGatherIntrinsic(ResVReg, ResType, I);
4292 case Intrinsic::spv_resource_getpointer: {
4293 return selectResourceGetPointer(ResVReg, ResType, I);
4294 }
4295 case Intrinsic::spv_pushconstant_getpointer: {
4296 return selectPushConstantGetPointer(ResVReg, ResType, I);
4297 }
4298 case Intrinsic::spv_discard: {
4299 return selectDiscard(ResVReg, ResType, I);
4300 }
4301 case Intrinsic::spv_resource_nonuniformindex: {
4302 return selectResourceNonUniformIndex(ResVReg, ResType, I);
4303 }
4304 case Intrinsic::spv_unpackhalf2x16: {
4305 return selectExtInst(ResVReg, ResType, I, GL::UnpackHalf2x16);
4306 }
4307 case Intrinsic::spv_packhalf2x16: {
4308 return selectExtInst(ResVReg, ResType, I, GL::PackHalf2x16);
4309 }
4310 case Intrinsic::spv_ddx:
4311 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdx);
4312 case Intrinsic::spv_ddy:
4313 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdy);
4314 case Intrinsic::spv_ddx_coarse:
4315 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdxCoarse);
4316 case Intrinsic::spv_ddy_coarse:
4317 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdyCoarse);
4318 case Intrinsic::spv_ddx_fine:
4319 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdxFine);
4320 case Intrinsic::spv_ddy_fine:
4321 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpDPdyFine);
4322 case Intrinsic::spv_fwidth:
4323 return selectDerivativeInst(ResVReg, ResType, I, SPIRV::OpFwidth);
4324 default: {
4325 std::string DiagMsg;
4326 raw_string_ostream OS(DiagMsg);
4327 I.print(OS);
4328 DiagMsg = "Intrinsic selection not implemented: " + DiagMsg;
4329 report_fatal_error(DiagMsg.c_str(), false);
4330 }
4331 }
4332 return true;
4333}
4334
4335bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg,
4336 SPIRVTypeInst ResType,
4337 MachineInstr &I) const {
4338 // The images need to be loaded in the same basic block as their use. We defer
4339 // loading the image to the intrinsic that uses it.
4340 if (ResType->getOpcode() == SPIRV::OpTypeImage)
4341 return true;
4342
4343 return loadHandleBeforePosition(ResVReg, GR.getSPIRVTypeForVReg(ResVReg),
4344 *cast<GIntrinsic>(&I), I);
4345}
4346
4347bool SPIRVInstructionSelector::selectCounterHandleFromBinding(
4348 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4349 auto &Intr = cast<GIntrinsic>(I);
4350 assert(Intr.getIntrinsicID() ==
4351 Intrinsic::spv_resource_counterhandlefrombinding);
4352
4353 // Extract information from the intrinsic call.
4354 Register MainHandleReg = Intr.getOperand(2).getReg();
4355 auto *MainHandleDef = cast<GIntrinsic>(getVRegDef(*MRI, MainHandleReg));
4356 assert(MainHandleDef->getIntrinsicID() ==
4357 Intrinsic::spv_resource_handlefrombinding);
4358
4359 uint32_t Set = getIConstVal(Intr.getOperand(4).getReg(), MRI);
4360 uint32_t Binding = getIConstVal(Intr.getOperand(3).getReg(), MRI);
4361 uint32_t ArraySize = getIConstVal(MainHandleDef->getOperand(4).getReg(), MRI);
4362 Register IndexReg = MainHandleDef->getOperand(5).getReg();
4363 std::string CounterName =
4364 getStringValueFromReg(MainHandleDef->getOperand(6).getReg(), *MRI) +
4365 ".counter";
4366
4367 // Create the counter variable.
4368 MachineIRBuilder MIRBuilder(I);
4369 Register CounterVarReg =
4370 buildPointerToResource(SPIRVTypeInst(GR.getPointeeType(ResType)),
4371 GR.getPointerStorageClass(ResType), Set, Binding,
4372 ArraySize, IndexReg, CounterName, MIRBuilder);
4373
4374 return BuildCOPY(ResVReg, CounterVarReg, I);
4375}
4376
4377bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg,
4378 SPIRVTypeInst ResType,
4379 MachineInstr &I) const {
4380 auto &Intr = cast<GIntrinsic>(I);
4381 assert(Intr.getIntrinsicID() == Intrinsic::spv_resource_updatecounter);
4382
4383 Register CounterHandleReg = Intr.getOperand(2).getReg();
4384 Register IncrReg = Intr.getOperand(3).getReg();
4385
4386 // The counter handle is a pointer to the counter variable (which is a struct
4387 // containing an i32). We need to get a pointer to that i32 member to do the
4388 // atomic operation.
4389#ifndef NDEBUG
4390 SPIRVTypeInst CounterVarType = GR.getSPIRVTypeForVReg(CounterHandleReg);
4391 SPIRVTypeInst CounterVarPointeeType = GR.getPointeeType(CounterVarType);
4392 assert(CounterVarPointeeType &&
4393 CounterVarPointeeType->getOpcode() == SPIRV::OpTypeStruct &&
4394 "Counter variable must be a struct");
4395 assert(GR.getPointerStorageClass(CounterVarType) ==
4396 SPIRV::StorageClass::StorageBuffer &&
4397 "Counter variable must be in the storage buffer storage class");
4398 assert(CounterVarPointeeType->getNumOperands() == 2 &&
4399 "Counter variable must have exactly 1 member in the struct");
4400 const SPIRVTypeInst MemberType =
4401 GR.getSPIRVTypeForVReg(CounterVarPointeeType->getOperand(1).getReg());
4402 assert(MemberType->getOpcode() == SPIRV::OpTypeInt &&
4403 "Counter variable struct must have a single i32 member");
4404#endif
4405
4406 // The struct has a single i32 member.
4407 MachineIRBuilder MIRBuilder(I);
4408 const Type *LLVMIntType =
4409 Type::getInt32Ty(I.getMF()->getFunction().getContext());
4410
4411 SPIRVTypeInst IntPtrType = GR.getOrCreateSPIRVPointerType(
4412 LLVMIntType, MIRBuilder, SPIRV::StorageClass::StorageBuffer);
4413
4414 Register Zero = buildI32Constant(0, I);
4415
4416 Register PtrToCounter =
4417 MRI->createVirtualRegister(GR.getRegClass(IntPtrType));
4418 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain))
4419 .addDef(PtrToCounter)
4420 .addUse(GR.getSPIRVTypeID(IntPtrType))
4421 .addUse(CounterHandleReg)
4422 .addUse(Zero)
4423 .constrainAllUses(TII, TRI, RBI);
4424
4425 // For UAV/SSBO counters, the scope is Device. The counter variable is not
4426 // used as a flag. So the memory semantics can be None.
4427 Register Scope = buildI32Constant(SPIRV::Scope::Device, I);
4428 Register Semantics = buildI32Constant(SPIRV::MemorySemantics::None, I);
4429
4430 int64_t IncrVal = getIConstValSext(IncrReg, MRI);
4431 Register Incr = buildI32Constant(static_cast<uint32_t>(IncrVal), I);
4432
4433 Register AtomicRes = MRI->createVirtualRegister(GR.getRegClass(ResType));
4434 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAtomicIAdd))
4435 .addDef(AtomicRes)
4436 .addUse(GR.getSPIRVTypeID(ResType))
4437 .addUse(PtrToCounter)
4438 .addUse(Scope)
4439 .addUse(Semantics)
4440 .addUse(Incr)
4441 .constrainAllUses(TII, TRI, RBI);
4442 if (IncrVal >= 0) {
4443 return BuildCOPY(ResVReg, AtomicRes, I);
4444 }
4445
4446 // In HLSL, IncrementCounter returns the value *before* the increment, while
4447 // DecrementCounter returns the value *after* the decrement. Both are lowered
4448 // to the same atomic intrinsic which returns the value *before* the
4449 // operation. So for decrements (negative IncrVal), we must subtract the
4450 // increment value from the result to get the post-decrement value.
4451 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
4452 .addDef(ResVReg)
4453 .addUse(GR.getSPIRVTypeID(ResType))
4454 .addUse(AtomicRes)
4455 .addUse(Incr)
4456 .constrainAllUses(TII, TRI, RBI);
4457 return true;
4458}
4459bool SPIRVInstructionSelector::selectReadImageIntrinsic(Register &ResVReg,
4460 SPIRVTypeInst ResType,
4461 MachineInstr &I) const {
4462
4463 // If the load of the image is in a different basic block, then
4464 // this will generate invalid code. A proper solution is to move
4465 // the OpLoad from selectHandleFromBinding here. However, to do
4466 // that we will need to change the return type of the intrinsic.
4467 // We will do that when we can, but for now trying to move forward with other
4468 // issues.
4469 Register ImageReg = I.getOperand(2).getReg();
4470 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4471 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4472 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4473 *ImageDef, I)) {
4474 return false;
4475 }
4476
4477 Register IdxReg = I.getOperand(3).getReg();
4478 DebugLoc Loc = I.getDebugLoc();
4479 MachineInstr &Pos = I;
4480
4481 return generateImageReadOrFetch(ResVReg, ResType, NewImageReg, IdxReg, Loc,
4482 Pos);
4483}
4484
4485bool SPIRVInstructionSelector::generateSampleImage(
4486 Register ResVReg, SPIRVTypeInst ResType, Register ImageReg,
4487 Register SamplerReg, Register CoordinateReg, const ImageOperands &ImOps,
4488 DebugLoc Loc, MachineInstr &Pos) const {
4489 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4490 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4491 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4492 *ImageDef, Pos)) {
4493 return false;
4494 }
4495
4496 auto *SamplerDef = cast<GIntrinsic>(getVRegDef(*MRI, SamplerReg));
4497 Register NewSamplerReg =
4498 MRI->createVirtualRegister(MRI->getRegClass(SamplerReg));
4499 if (!loadHandleBeforePosition(NewSamplerReg,
4500 GR.getSPIRVTypeForVReg(SamplerReg), *SamplerDef,
4501 Pos)) {
4502 return false;
4503 }
4504
4505 MachineIRBuilder MIRBuilder(Pos);
4506 SPIRVTypeInst SampledImageType = GR.getOrCreateOpTypeSampledImage(
4507 GR.getSPIRVTypeForVReg(ImageReg), MIRBuilder);
4508 Register SampledImageReg =
4509 MRI->createVirtualRegister(GR.getRegClass(SampledImageType));
4510
4511 BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpSampledImage))
4512 .addDef(SampledImageReg)
4513 .addUse(GR.getSPIRVTypeID(SampledImageType))
4514 .addUse(NewImageReg)
4515 .addUse(NewSamplerReg)
4516 .constrainAllUses(TII, TRI, RBI);
4517
4518 bool IsExplicitLod = ImOps.GradX.has_value() || ImOps.GradY.has_value() ||
4519 ImOps.Lod.has_value();
4520 unsigned Opcode = IsExplicitLod ? SPIRV::OpImageSampleExplicitLod
4521 : SPIRV::OpImageSampleImplicitLod;
4522 if (ImOps.Compare)
4523 Opcode = IsExplicitLod ? SPIRV::OpImageSampleDrefExplicitLod
4524 : SPIRV::OpImageSampleDrefImplicitLod;
4525
4526 auto MIB = BuildMI(*Pos.getParent(), Pos, Loc, TII.get(Opcode))
4527 .addDef(ResVReg)
4528 .addUse(GR.getSPIRVTypeID(ResType))
4529 .addUse(SampledImageReg)
4530 .addUse(CoordinateReg);
4531
4532 if (ImOps.Compare)
4533 MIB.addUse(*ImOps.Compare);
4534
4535 uint32_t ImageOperands = 0;
4536 if (ImOps.Bias)
4537 ImageOperands |= SPIRV::ImageOperand::Bias;
4538 if (ImOps.Lod)
4539 ImageOperands |= SPIRV::ImageOperand::Lod;
4540 if (ImOps.GradX && ImOps.GradY)
4541 ImageOperands |= SPIRV::ImageOperand::Grad;
4542 if (ImOps.Offset && !isScalarOrVectorIntConstantZero(*ImOps.Offset)) {
4543 if (isConstReg(MRI, *ImOps.Offset))
4544 ImageOperands |= SPIRV::ImageOperand::ConstOffset;
4545 else {
4546 Pos.emitGenericError(
4547 "Non-constant offsets are not supported in sample instructions.");
4548 }
4549 }
4550 if (ImOps.MinLod)
4551 ImageOperands |= SPIRV::ImageOperand::MinLod;
4552
4553 if (ImageOperands != 0) {
4554 MIB.addImm(ImageOperands);
4555 if (ImageOperands & SPIRV::ImageOperand::Bias)
4556 MIB.addUse(*ImOps.Bias);
4557 if (ImageOperands & SPIRV::ImageOperand::Lod)
4558 MIB.addUse(*ImOps.Lod);
4559 if (ImageOperands & SPIRV::ImageOperand::Grad) {
4560 MIB.addUse(*ImOps.GradX);
4561 MIB.addUse(*ImOps.GradY);
4562 }
4563 if (ImageOperands &
4564 (SPIRV::ImageOperand::ConstOffset | SPIRV::ImageOperand::Offset))
4565 MIB.addUse(*ImOps.Offset);
4566 if (ImageOperands & SPIRV::ImageOperand::MinLod)
4567 MIB.addUse(*ImOps.MinLod);
4568 }
4569
4570 MIB.constrainAllUses(TII, TRI, RBI);
4571 return true;
4572}
4573
4574bool SPIRVInstructionSelector::selectSampleBasicIntrinsic(
4575 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4576 Register ImageReg = I.getOperand(2).getReg();
4577 Register SamplerReg = I.getOperand(3).getReg();
4578 Register CoordinateReg = I.getOperand(4).getReg();
4579 ImageOperands ImOps;
4580 if (I.getNumOperands() > 5)
4581 ImOps.Offset = I.getOperand(5).getReg();
4582 if (I.getNumOperands() > 6)
4583 ImOps.MinLod = I.getOperand(6).getReg();
4584 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4585 CoordinateReg, ImOps, I.getDebugLoc(), I);
4586}
4587
4588bool SPIRVInstructionSelector::selectSampleBiasIntrinsic(
4589 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4590 Register ImageReg = I.getOperand(2).getReg();
4591 Register SamplerReg = I.getOperand(3).getReg();
4592 Register CoordinateReg = I.getOperand(4).getReg();
4593 ImageOperands ImOps;
4594 ImOps.Bias = I.getOperand(5).getReg();
4595 if (I.getNumOperands() > 6)
4596 ImOps.Offset = I.getOperand(6).getReg();
4597 if (I.getNumOperands() > 7)
4598 ImOps.MinLod = I.getOperand(7).getReg();
4599 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4600 CoordinateReg, ImOps, I.getDebugLoc(), I);
4601}
4602
4603bool SPIRVInstructionSelector::selectSampleGradIntrinsic(
4604 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4605 Register ImageReg = I.getOperand(2).getReg();
4606 Register SamplerReg = I.getOperand(3).getReg();
4607 Register CoordinateReg = I.getOperand(4).getReg();
4608 ImageOperands ImOps;
4609 ImOps.GradX = I.getOperand(5).getReg();
4610 ImOps.GradY = I.getOperand(6).getReg();
4611 if (I.getNumOperands() > 7)
4612 ImOps.Offset = I.getOperand(7).getReg();
4613 if (I.getNumOperands() > 8)
4614 ImOps.MinLod = I.getOperand(8).getReg();
4615 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4616 CoordinateReg, ImOps, I.getDebugLoc(), I);
4617}
4618
4619bool SPIRVInstructionSelector::selectSampleLevelIntrinsic(
4620 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4621 Register ImageReg = I.getOperand(2).getReg();
4622 Register SamplerReg = I.getOperand(3).getReg();
4623 Register CoordinateReg = I.getOperand(4).getReg();
4624 ImageOperands ImOps;
4625 ImOps.Lod = I.getOperand(5).getReg();
4626 if (I.getNumOperands() > 6)
4627 ImOps.Offset = I.getOperand(6).getReg();
4628 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4629 CoordinateReg, ImOps, I.getDebugLoc(), I);
4630}
4631
4632bool SPIRVInstructionSelector::selectSampleCmpIntrinsic(Register &ResVReg,
4633 SPIRVTypeInst ResType,
4634 MachineInstr &I) const {
4635 Register ImageReg = I.getOperand(2).getReg();
4636 Register SamplerReg = I.getOperand(3).getReg();
4637 Register CoordinateReg = I.getOperand(4).getReg();
4638 ImageOperands ImOps;
4639 ImOps.Compare = I.getOperand(5).getReg();
4640 if (I.getNumOperands() > 6)
4641 ImOps.Offset = I.getOperand(6).getReg();
4642 if (I.getNumOperands() > 7)
4643 ImOps.MinLod = I.getOperand(7).getReg();
4644 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4645 CoordinateReg, ImOps, I.getDebugLoc(), I);
4646}
4647
4648bool SPIRVInstructionSelector::selectSampleCmpLevelZeroIntrinsic(
4649 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4650 Register ImageReg = I.getOperand(2).getReg();
4651 Register SamplerReg = I.getOperand(3).getReg();
4652 Register CoordinateReg = I.getOperand(4).getReg();
4653 ImageOperands ImOps;
4654 ImOps.Compare = I.getOperand(5).getReg();
4655 if (I.getNumOperands() > 6)
4656 ImOps.Offset = I.getOperand(6).getReg();
4657 SPIRVTypeInst FloatTy = GR.getOrCreateSPIRVFloatType(32, I, TII);
4658 ImOps.Lod = GR.getOrCreateConstFP(APFloat(0.0f), I, FloatTy, TII);
4659 return generateSampleImage(ResVReg, ResType, ImageReg, SamplerReg,
4660 CoordinateReg, ImOps, I.getDebugLoc(), I);
4661}
4662
4663bool SPIRVInstructionSelector::selectGatherIntrinsic(Register &ResVReg,
4664 SPIRVTypeInst ResType,
4665 MachineInstr &I) const {
4666 Register ImageReg = I.getOperand(2).getReg();
4667 Register SamplerReg = I.getOperand(3).getReg();
4668 Register CoordinateReg = I.getOperand(4).getReg();
4669 SPIRVTypeInst ImageType = GR.getSPIRVTypeForVReg(ImageReg);
4670 assert(ImageType && ImageType->getOpcode() == SPIRV::OpTypeImage &&
4671 "ImageReg is not an image type.");
4672
4673 Register ComponentOrCompareReg;
4674 Register OffsetReg;
4675
4676 ComponentOrCompareReg = I.getOperand(5).getReg();
4677 OffsetReg = I.getOperand(6).getReg();
4678 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4679 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4680 if (!loadHandleBeforePosition(NewImageReg, ImageType, *ImageDef, I)) {
4681 return false;
4682 }
4683
4684 auto Dim = static_cast<SPIRV::Dim::Dim>(ImageType->getOperand(2).getImm());
4685 if (Dim != SPIRV::Dim::DIM_2D && Dim != SPIRV::Dim::DIM_Cube &&
4686 Dim != SPIRV::Dim::DIM_Rect) {
4687 I.emitGenericError(
4688 "Gather operations are only supported for 2D, Cube, and Rect images.");
4689 return false;
4690 }
4691
4692 auto *SamplerDef = cast<GIntrinsic>(getVRegDef(*MRI, SamplerReg));
4693 Register NewSamplerReg =
4694 MRI->createVirtualRegister(MRI->getRegClass(SamplerReg));
4695 if (!loadHandleBeforePosition(
4696 NewSamplerReg, GR.getSPIRVTypeForVReg(SamplerReg), *SamplerDef, I)) {
4697 return false;
4698 }
4699
4700 MachineIRBuilder MIRBuilder(I);
4701 SPIRVTypeInst SampledImageType =
4702 GR.getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
4703 Register SampledImageReg =
4704 MRI->createVirtualRegister(GR.getRegClass(SampledImageType));
4705
4706 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpSampledImage))
4707 .addDef(SampledImageReg)
4708 .addUse(GR.getSPIRVTypeID(SampledImageType))
4709 .addUse(NewImageReg)
4710 .addUse(NewSamplerReg)
4711 .constrainAllUses(TII, TRI, RBI);
4712
4713 auto IntrId = cast<GIntrinsic>(I).getIntrinsicID();
4714 bool IsGatherCmp = IntrId == Intrinsic::spv_resource_gather_cmp;
4715 unsigned Opcode =
4716 IsGatherCmp ? SPIRV::OpImageDrefGather : SPIRV::OpImageGather;
4717
4718 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
4719 .addDef(ResVReg)
4720 .addUse(GR.getSPIRVTypeID(ResType))
4721 .addUse(SampledImageReg)
4722 .addUse(CoordinateReg)
4723 .addUse(ComponentOrCompareReg);
4724
4725 uint32_t ImageOperands = 0;
4726 if (OffsetReg && !isScalarOrVectorIntConstantZero(OffsetReg)) {
4727 if (Dim == SPIRV::Dim::DIM_Cube) {
4728 I.emitGenericError(
4729 "Gather operations with offset are not supported for Cube images.");
4730 return false;
4731 }
4732 if (isConstReg(MRI, OffsetReg))
4733 ImageOperands |= SPIRV::ImageOperand::ConstOffset;
4734 else {
4735 ImageOperands |= SPIRV::ImageOperand::Offset;
4736 }
4737 }
4738
4739 if (ImageOperands != 0) {
4740 MIB.addImm(ImageOperands);
4741 if (ImageOperands &
4742 (SPIRV::ImageOperand::ConstOffset | SPIRV::ImageOperand::Offset))
4743 MIB.addUse(OffsetReg);
4744 }
4745
4746 MIB.constrainAllUses(TII, TRI, RBI);
4747 return true;
4748}
4749
4750bool SPIRVInstructionSelector::generateImageReadOrFetch(
4751 Register &ResVReg, SPIRVTypeInst ResType, Register ImageReg,
4752 Register IdxReg, DebugLoc Loc, MachineInstr &Pos) const {
4753 SPIRVTypeInst ImageType = GR.getSPIRVTypeForVReg(ImageReg);
4754 assert(ImageType && ImageType->getOpcode() == SPIRV::OpTypeImage &&
4755 "ImageReg is not an image type.");
4756
4757 bool IsSignedInteger =
4758 sampledTypeIsSignedInteger(GR.getTypeForSPIRVType(ImageType));
4759 // Check if the "sampled" operand of the image type is 1.
4760 // https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpImageFetch
4761 auto SampledOp = ImageType->getOperand(6);
4762 bool IsFetch = (SampledOp.getImm() == 1);
4763
4764 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
4765 if (ResultSize == 4) {
4766 auto BMI =
4767 BuildMI(*Pos.getParent(), Pos, Loc,
4768 TII.get(IsFetch ? SPIRV::OpImageFetch : SPIRV::OpImageRead))
4769 .addDef(ResVReg)
4770 .addUse(GR.getSPIRVTypeID(ResType))
4771 .addUse(ImageReg)
4772 .addUse(IdxReg);
4773
4774 if (IsSignedInteger)
4775 BMI.addImm(0x1000); // SignExtend
4776 BMI.constrainAllUses(TII, TRI, RBI);
4777 return true;
4778 }
4779
4780 SPIRVTypeInst ReadType = widenTypeToVec4(ResType, Pos);
4781 Register ReadReg = MRI->createVirtualRegister(GR.getRegClass(ReadType));
4782 auto BMI =
4783 BuildMI(*Pos.getParent(), Pos, Loc,
4784 TII.get(IsFetch ? SPIRV::OpImageFetch : SPIRV::OpImageRead))
4785 .addDef(ReadReg)
4786 .addUse(GR.getSPIRVTypeID(ReadType))
4787 .addUse(ImageReg)
4788 .addUse(IdxReg);
4789 if (IsSignedInteger)
4790 BMI.addImm(0x1000); // SignExtend
4791 BMI.constrainAllUses(TII, TRI, RBI);
4792
4793 if (ResultSize == 1) {
4794 BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpCompositeExtract))
4795 .addDef(ResVReg)
4796 .addUse(GR.getSPIRVTypeID(ResType))
4797 .addUse(ReadReg)
4798 .addImm(0)
4799 .constrainAllUses(TII, TRI, RBI);
4800 return true;
4801 }
4802 return extractSubvector(ResVReg, ResType, ReadReg, Pos);
4803}
4804
4805bool SPIRVInstructionSelector::selectResourceGetPointer(Register &ResVReg,
4806 SPIRVTypeInst ResType,
4807 MachineInstr &I) const {
4808 Register ResourcePtr = I.getOperand(2).getReg();
4809 SPIRVTypeInst RegType = GR.getSPIRVTypeForVReg(ResourcePtr, I.getMF());
4810 if (RegType->getOpcode() == SPIRV::OpTypeImage) {
4811 // For texel buffers, the index into the image is part of the OpImageRead or
4812 // OpImageWrite instructions. So we will do nothing in this case. This
4813 // intrinsic will be combined with the load or store when selecting the load
4814 // or store.
4815 return true;
4816 }
4817
4818 assert(ResType->getOpcode() == SPIRV::OpTypePointer);
4819 MachineIRBuilder MIRBuilder(I);
4820
4821 Register IndexReg = I.getOperand(3).getReg();
4822 Register ZeroReg =
4823 buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I);
4824 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain))
4825 .addDef(ResVReg)
4826 .addUse(GR.getSPIRVTypeID(ResType))
4827 .addUse(ResourcePtr)
4828 .addUse(ZeroReg)
4829 .addUse(IndexReg)
4830 .constrainAllUses(TII, TRI, RBI);
4831 return true;
4832}
4833
4834bool SPIRVInstructionSelector::selectPushConstantGetPointer(
4835 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4836 MRI->replaceRegWith(ResVReg, I.getOperand(2).getReg());
4837 return true;
4838}
4839
4840bool SPIRVInstructionSelector::selectResourceNonUniformIndex(
4841 Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const {
4842 Register ObjReg = I.getOperand(2).getReg();
4843 if (!BuildCOPY(ResVReg, ObjReg, I))
4844 return false;
4845
4846 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::NonUniformEXT, {});
4847 // Check for the registers that use the index marked as non-uniform
4848 // and recursively mark them as non-uniform.
4849 // Per the spec, it's necessary that the final argument used for
4850 // load/store/sample/atomic must be decorated, so we need to propagate the
4851 // decoration through access chains and copies.
4852 // https://docs.vulkan.org/samples/latest/samples/extensions/descriptor_indexing/README.html#_when_to_use_non_uniform_indexing_qualifier
4853 decorateUsesAsNonUniform(ResVReg);
4854 return true;
4855}
4856
4857void SPIRVInstructionSelector::decorateUsesAsNonUniform(
4858 Register &NonUniformReg) const {
4859 llvm::SmallVector<Register> WorkList = {NonUniformReg};
4860 while (WorkList.size() > 0) {
4861 Register CurrentReg = WorkList.back();
4862 WorkList.pop_back();
4863
4864 bool IsDecorated = false;
4865 for (MachineInstr &Use : MRI->use_instructions(CurrentReg)) {
4866 if (Use.getOpcode() == SPIRV::OpDecorate &&
4867 Use.getOperand(1).getImm() == SPIRV::Decoration::NonUniformEXT) {
4868 IsDecorated = true;
4869 continue;
4870 }
4871 // Check if the instruction has the result register and add it to the
4872 // worklist.
4873 if (Use.getOperand(0).isReg() && Use.getOperand(0).isDef()) {
4874 Register ResultReg = Use.getOperand(0).getReg();
4875 if (ResultReg == CurrentReg)
4876 continue;
4877 WorkList.push_back(ResultReg);
4878 }
4879 }
4880
4881 if (!IsDecorated) {
4882 buildOpDecorate(CurrentReg, *MRI->getVRegDef(CurrentReg), TII,
4883 SPIRV::Decoration::NonUniformEXT, {});
4884 }
4885 }
4886}
4887
4888bool SPIRVInstructionSelector::extractSubvector(
4889 Register &ResVReg, SPIRVTypeInst ResType, Register &ReadReg,
4890 MachineInstr &InsertionPoint) const {
4891 SPIRVTypeInst InputType = GR.getResultType(ReadReg);
4892 [[maybe_unused]] uint64_t InputSize =
4893 GR.getScalarOrVectorComponentCount(InputType);
4894 uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
4895 assert(InputSize > 1 && "The input must be a vector.");
4896 assert(ResultSize > 1 && "The result must be a vector.");
4897 assert(ResultSize < InputSize &&
4898 "Cannot extract more element than there are in the input.");
4899 SmallVector<Register> ComponentRegisters;
4900 SPIRVTypeInst ScalarType = GR.getScalarOrVectorComponentType(ResType);
4901 const TargetRegisterClass *ScalarRegClass = GR.getRegClass(ScalarType);
4902 for (uint64_t I = 0; I < ResultSize; I++) {
4903 Register ComponentReg = MRI->createVirtualRegister(ScalarRegClass);
4904 BuildMI(*InsertionPoint.getParent(), InsertionPoint,
4905 InsertionPoint.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
4906 .addDef(ComponentReg)
4907 .addUse(ScalarType->getOperand(0).getReg())
4908 .addUse(ReadReg)
4909 .addImm(I)
4910 .constrainAllUses(TII, TRI, RBI);
4911 ComponentRegisters.emplace_back(ComponentReg);
4912 }
4913
4914 MachineInstrBuilder MIB = BuildMI(*InsertionPoint.getParent(), InsertionPoint,
4915 InsertionPoint.getDebugLoc(),
4916 TII.get(SPIRV::OpCompositeConstruct))
4917 .addDef(ResVReg)
4918 .addUse(GR.getSPIRVTypeID(ResType));
4919
4920 for (Register ComponentReg : ComponentRegisters)
4921 MIB.addUse(ComponentReg);
4922 MIB.constrainAllUses(TII, TRI, RBI);
4923 return true;
4924}
4925
4926bool SPIRVInstructionSelector::selectImageWriteIntrinsic(
4927 MachineInstr &I) const {
4928 // If the load of the image is in a different basic block, then
4929 // this will generate invalid code. A proper solution is to move
4930 // the OpLoad from selectHandleFromBinding here. However, to do
4931 // that we will need to change the return type of the intrinsic.
4932 // We will do that when we can, but for now trying to move forward with other
4933 // issues.
4934 Register ImageReg = I.getOperand(1).getReg();
4935 auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg));
4936 Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg));
4937 if (!loadHandleBeforePosition(NewImageReg, GR.getSPIRVTypeForVReg(ImageReg),
4938 *ImageDef, I)) {
4939 return false;
4940 }
4941
4942 Register CoordinateReg = I.getOperand(2).getReg();
4943 Register DataReg = I.getOperand(3).getReg();
4944 assert(GR.getResultType(DataReg)->getOpcode() == SPIRV::OpTypeVector);
4945 assert(GR.getScalarOrVectorComponentCount(GR.getResultType(DataReg)) == 4);
4946 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageWrite))
4947 .addUse(NewImageReg)
4948 .addUse(CoordinateReg)
4949 .addUse(DataReg)
4950 .constrainAllUses(TII, TRI, RBI);
4951 return true;
4952}
4953
4954Register SPIRVInstructionSelector::buildPointerToResource(
4955 SPIRVTypeInst SpirvResType, SPIRV::StorageClass::StorageClass SC,
4956 uint32_t Set, uint32_t Binding, uint32_t ArraySize, Register IndexReg,
4957 StringRef Name, MachineIRBuilder MIRBuilder) const {
4958 const Type *ResType = GR.getTypeForSPIRVType(SpirvResType);
4959 if (ArraySize == 1) {
4960 SPIRVTypeInst PtrType =
4961 GR.getOrCreateSPIRVPointerType(ResType, MIRBuilder, SC);
4962 assert(GR.getPointeeType(PtrType) == SpirvResType &&
4963 "SpirvResType did not have an explicit layout.");
4964 return GR.getOrCreateGlobalVariableWithBinding(PtrType, Set, Binding, Name,
4965 MIRBuilder);
4966 }
4967
4968 const Type *VarType = ArrayType::get(const_cast<Type *>(ResType), ArraySize);
4969 SPIRVTypeInst VarPointerType =
4970 GR.getOrCreateSPIRVPointerType(VarType, MIRBuilder, SC);
4971 Register VarReg = GR.getOrCreateGlobalVariableWithBinding(
4972 VarPointerType, Set, Binding, Name, MIRBuilder);
4973
4974 SPIRVTypeInst ResPointerType =
4975 GR.getOrCreateSPIRVPointerType(ResType, MIRBuilder, SC);
4976 Register AcReg = MRI->createVirtualRegister(GR.getRegClass(ResPointerType));
4977
4978 MIRBuilder.buildInstr(SPIRV::OpAccessChain)
4979 .addDef(AcReg)
4980 .addUse(GR.getSPIRVTypeID(ResPointerType))
4981 .addUse(VarReg)
4982 .addUse(IndexReg);
4983
4984 return AcReg;
4985}
4986
4987bool SPIRVInstructionSelector::selectFirstBitSet16(
4988 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
4989 unsigned ExtendOpcode, unsigned BitSetOpcode) const {
4990 Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
4991 if (!selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()},
4992 ExtendOpcode))
4993 return false;
4994
4995 return selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode);
4996}
4997
4998bool SPIRVInstructionSelector::selectFirstBitSet32(
4999 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
5000 unsigned BitSetOpcode) const {
5001 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
5002 .addDef(ResVReg)
5003 .addUse(GR.getSPIRVTypeID(ResType))
5004 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
5005 .addImm(BitSetOpcode)
5006 .addUse(SrcReg)
5007 .constrainAllUses(TII, TRI, RBI);
5008 return true;
5009}
5010
5011bool SPIRVInstructionSelector::selectFirstBitSet64Overflow(
5012 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
5013 unsigned BitSetOpcode, bool SwapPrimarySide) const {
5014
5015 // SPIR-V allow vectors of size 2,3,4 only. Calling with a larger vectors
5016 // requires creating a param register and return register with an invalid
5017 // vector size. If that is resolved, then this function can be used for
5018 // vectors of any component size.
5019 unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType);
5020 assert(ComponentCount < 5 && "Vec 5+ will generate invalid SPIR-V ops");
5021
5022 MachineIRBuilder MIRBuilder(I);
5023 SPIRVTypeInst BaseType = GR.retrieveScalarOrVectorIntType(ResType);
5024 SPIRVTypeInst I64Type = GR.getOrCreateSPIRVIntegerType(64, MIRBuilder);
5025 SPIRVTypeInst I64x2Type =
5026 GR.getOrCreateSPIRVVectorType(I64Type, 2, MIRBuilder, false);
5027 SPIRVTypeInst Vec2ResType =
5028 GR.getOrCreateSPIRVVectorType(BaseType, 2, MIRBuilder, false);
5029
5030 std::vector<Register> PartialRegs;
5031
5032 // Loops 0, 2, 4, ... but stops one loop early when ComponentCount is odd
5033 unsigned CurrentComponent = 0;
5034 for (; CurrentComponent + 1 < ComponentCount; CurrentComponent += 2) {
5035 // This register holds the firstbitX result for each of the i64x2 vectors
5036 // extracted from SrcReg
5037 Register BitSetResult =
5038 MRI->createVirtualRegister(GR.getRegClass(I64x2Type));
5039
5040 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
5041 TII.get(SPIRV::OpVectorShuffle))
5042 .addDef(BitSetResult)
5043 .addUse(GR.getSPIRVTypeID(I64x2Type))
5044 .addUse(SrcReg)
5045 .addUse(SrcReg)
5046 .addImm(CurrentComponent)
5047 .addImm(CurrentComponent + 1);
5048
5049 MIB.constrainAllUses(TII, TRI, RBI);
5050
5051 Register SubVecBitSetReg =
5052 MRI->createVirtualRegister(GR.getRegClass(Vec2ResType));
5053
5054 if (!selectFirstBitSet64(SubVecBitSetReg, Vec2ResType, I, BitSetResult,
5055 BitSetOpcode, SwapPrimarySide))
5056 return false;
5057
5058 PartialRegs.push_back(SubVecBitSetReg);
5059 }
5060
5061 // On odd component counts we need to handle one more component
5062 if (CurrentComponent != ComponentCount) {
5063 bool ZeroAsNull = !STI.isShader();
5064 Register FinalElemReg = MRI->createVirtualRegister(GR.getRegClass(I64Type));
5065 Register ConstIntLastIdx = GR.getOrCreateConstInt(
5066 ComponentCount - 1, I, BaseType, TII, ZeroAsNull);
5067
5068 if (!selectOpWithSrcs(FinalElemReg, I64Type, I, {SrcReg, ConstIntLastIdx},
5069 SPIRV::OpVectorExtractDynamic))
5070 return false;
5071
5072 Register FinalElemBitSetReg =
5073 MRI->createVirtualRegister(GR.getRegClass(BaseType));
5074
5075 if (!selectFirstBitSet64(FinalElemBitSetReg, BaseType, I, FinalElemReg,
5076 BitSetOpcode, SwapPrimarySide))
5077 return false;
5078
5079 PartialRegs.push_back(FinalElemBitSetReg);
5080 }
5081
5082 // Join all the resulting registers back into the return type in order
5083 // (ie i32x2, i32x2, i32x1 -> i32x5)
5084 return selectOpWithSrcs(ResVReg, ResType, I, std::move(PartialRegs),
5085 SPIRV::OpCompositeConstruct);
5086}
5087
5088bool SPIRVInstructionSelector::selectFirstBitSet64(
5089 Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, Register SrcReg,
5090 unsigned BitSetOpcode, bool SwapPrimarySide) const {
5091 unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType);
5092 SPIRVTypeInst BaseType = GR.retrieveScalarOrVectorIntType(ResType);
5093 bool ZeroAsNull = !STI.isShader();
5094 Register ConstIntZero =
5095 GR.getOrCreateConstInt(0, I, BaseType, TII, ZeroAsNull);
5096 Register ConstIntOne =
5097 GR.getOrCreateConstInt(1, I, BaseType, TII, ZeroAsNull);
5098
5099 // SPIRV doesn't support vectors with more than 4 components. Since the
5100 // algoritm below converts i64 -> i32x2 and i64x4 -> i32x8 it can only
5101 // operate on vectors with 2 or less components. When largers vectors are
5102 // seen. Split them, recurse, then recombine them.
5103 if (ComponentCount > 2) {
5104 return selectFirstBitSet64Overflow(ResVReg, ResType, I, SrcReg,
5105 BitSetOpcode, SwapPrimarySide);
5106 }
5107
5108 // 1. Split int64 into 2 pieces using a bitcast
5109 MachineIRBuilder MIRBuilder(I);
5110 SPIRVTypeInst PostCastType = GR.getOrCreateSPIRVVectorType(
5111 BaseType, 2 * ComponentCount, MIRBuilder, false);
5112 Register BitcastReg =
5113 MRI->createVirtualRegister(GR.getRegClass(PostCastType));
5114
5115 if (!selectOpWithSrcs(BitcastReg, PostCastType, I, {SrcReg},
5116 SPIRV::OpBitcast))
5117 return false;
5118
5119 // 2. Find the first set bit from the primary side for all the pieces in #1
5120 Register FBSReg = MRI->createVirtualRegister(GR.getRegClass(PostCastType));
5121 if (!selectFirstBitSet32(FBSReg, PostCastType, I, BitcastReg, BitSetOpcode))
5122 return false;
5123
5124 // 3. Split result vector into high bits and low bits
5125 Register HighReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5126 Register LowReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5127
5128 bool IsScalarRes = ResType->getOpcode() != SPIRV::OpTypeVector;
5129 if (IsScalarRes) {
5130 // if scalar do a vector extract
5131 if (!selectOpWithSrcs(HighReg, ResType, I, {FBSReg, ConstIntZero},
5132 SPIRV::OpVectorExtractDynamic))
5133 return false;
5134 if (!selectOpWithSrcs(LowReg, ResType, I, {FBSReg, ConstIntOne},
5135 SPIRV::OpVectorExtractDynamic))
5136 return false;
5137 } else {
5138 // if vector do a shufflevector
5139 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
5140 TII.get(SPIRV::OpVectorShuffle))
5141 .addDef(HighReg)
5142 .addUse(GR.getSPIRVTypeID(ResType))
5143 .addUse(FBSReg)
5144 // Per the spec, repeat the vector if only one vec is needed
5145 .addUse(FBSReg);
5146
5147 // high bits are stored in even indexes. Extract them from FBSReg
5148 for (unsigned J = 0; J < ComponentCount * 2; J += 2) {
5149 MIB.addImm(J);
5150 }
5151
5152 MIB.constrainAllUses(TII, TRI, RBI);
5153
5154 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
5155 TII.get(SPIRV::OpVectorShuffle))
5156 .addDef(LowReg)
5157 .addUse(GR.getSPIRVTypeID(ResType))
5158 .addUse(FBSReg)
5159 // Per the spec, repeat the vector if only one vec is needed
5160 .addUse(FBSReg);
5161
5162 // low bits are stored in odd indexes. Extract them from FBSReg
5163 for (unsigned J = 1; J < ComponentCount * 2; J += 2) {
5164 MIB.addImm(J);
5165 }
5166 MIB.constrainAllUses(TII, TRI, RBI);
5167 }
5168
5169 // 4. Check the result. When primary bits == -1 use secondary, otherwise use
5170 // primary
5171 SPIRVTypeInst BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
5172 Register NegOneReg;
5173 Register Reg0;
5174 Register Reg32;
5175 unsigned SelectOp;
5176 unsigned AddOp;
5177
5178 if (IsScalarRes) {
5179 NegOneReg =
5180 GR.getOrCreateConstInt((unsigned)-1, I, ResType, TII, ZeroAsNull);
5181 Reg0 = GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull);
5182 Reg32 = GR.getOrCreateConstInt(32, I, ResType, TII, ZeroAsNull);
5183 SelectOp = SPIRV::OpSelectSISCond;
5184 AddOp = SPIRV::OpIAddS;
5185 } else {
5186 BoolType = GR.getOrCreateSPIRVVectorType(BoolType, ComponentCount,
5187 MIRBuilder, false);
5188 NegOneReg =
5189 GR.getOrCreateConstVector((unsigned)-1, I, ResType, TII, ZeroAsNull);
5190 Reg0 = GR.getOrCreateConstVector(0, I, ResType, TII, ZeroAsNull);
5191 Reg32 = GR.getOrCreateConstVector(32, I, ResType, TII, ZeroAsNull);
5192 SelectOp = SPIRV::OpSelectVIVCond;
5193 AddOp = SPIRV::OpIAddV;
5194 }
5195
5196 Register PrimaryReg = HighReg;
5197 Register SecondaryReg = LowReg;
5198 Register PrimaryShiftReg = Reg32;
5199 Register SecondaryShiftReg = Reg0;
5200
5201 // By default the emitted opcodes check for the set bit from the MSB side.
5202 // Setting SwapPrimarySide checks the set bit from the LSB side
5203 if (SwapPrimarySide) {
5204 PrimaryReg = LowReg;
5205 SecondaryReg = HighReg;
5206 PrimaryShiftReg = Reg0;
5207 SecondaryShiftReg = Reg32;
5208 }
5209
5210 // Check if the primary bits are == -1
5211 Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
5212 if (!selectOpWithSrcs(BReg, BoolType, I, {PrimaryReg, NegOneReg},
5213 SPIRV::OpIEqual))
5214 return false;
5215
5216 // Select secondary bits if true in BReg, otherwise primary bits
5217 Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5218 if (!selectOpWithSrcs(TmpReg, ResType, I, {BReg, SecondaryReg, PrimaryReg},
5219 SelectOp))
5220 return false;
5221
5222 // 5. Add 32 when high bits are used, otherwise 0 for low bits
5223 Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5224 if (!selectOpWithSrcs(ValReg, ResType, I,
5225 {BReg, SecondaryShiftReg, PrimaryShiftReg}, SelectOp))
5226 return false;
5227
5228 return selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, AddOp);
5229}
5230
5231bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
5232 SPIRVTypeInst ResType,
5233 MachineInstr &I,
5234 bool IsSigned) const {
5235 // FindUMsb and FindSMsb intrinsics only support 32 bit integers
5236 Register OpReg = I.getOperand(2).getReg();
5237 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
5238 // zero or sign extend
5239 unsigned ExtendOpcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
5240 unsigned BitSetOpcode = IsSigned ? GL::FindSMsb : GL::FindUMsb;
5241
5242 switch (GR.getScalarOrVectorBitWidth(OpType)) {
5243 case 16:
5244 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
5245 case 32:
5246 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
5247 case 64:
5248 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
5249 /*SwapPrimarySide=*/false);
5250 default:
5251 report_fatal_error(
5252 "spv_firstbituhigh and spv_firstbitshigh only support 16,32,64 bits.");
5253 }
5254}
5255
5256bool SPIRVInstructionSelector::selectFirstBitLow(Register ResVReg,
5257 SPIRVTypeInst ResType,
5258 MachineInstr &I) const {
5259 // FindILsb intrinsic only supports 32 bit integers
5260 Register OpReg = I.getOperand(2).getReg();
5261 SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg);
5262 // OpUConvert treats the operand bits as an unsigned i16 and zero extends it
5263 // to an unsigned i32. As this leaves all the least significant bits unchanged
5264 // so the first set bit from the LSB side doesn't change.
5265 unsigned ExtendOpcode = SPIRV::OpUConvert;
5266 unsigned BitSetOpcode = GL::FindILsb;
5267
5268 switch (GR.getScalarOrVectorBitWidth(OpType)) {
5269 case 16:
5270 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
5271 case 32:
5272 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
5273 case 64:
5274 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
5275 /*SwapPrimarySide=*/true);
5276 default:
5277 report_fatal_error("spv_firstbitlow only supports 16,32,64 bits.");
5278 }
5279}
5280
5281bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
5282 SPIRVTypeInst ResType,
5283 MachineInstr &I) const {
5284 // there was an allocation size parameter to the allocation instruction
5285 // that is not 1
5286 MachineBasicBlock &BB = *I.getParent();
5287 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVariableLengthArrayINTEL))
5288 .addDef(ResVReg)
5289 .addUse(GR.getSPIRVTypeID(ResType))
5290 .addUse(I.getOperand(2).getReg())
5291 .constrainAllUses(TII, TRI, RBI);
5292 if (!STI.isShader()) {
5293 unsigned Alignment = I.getOperand(3).getImm();
5294 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment});
5295 }
5296 return true;
5297}
5298
5299bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
5300 SPIRVTypeInst ResType,
5301 MachineInstr &I) const {
5302 // Change order of instructions if needed: all OpVariable instructions in a
5303 // function must be the first instructions in the first block
5304 auto It = getOpVariableMBBIt(I);
5305 BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable))
5306 .addDef(ResVReg)
5307 .addUse(GR.getSPIRVTypeID(ResType))
5308 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function))
5309 .constrainAllUses(TII, TRI, RBI);
5310 if (!STI.isShader()) {
5311 unsigned Alignment = I.getOperand(2).getImm();
5312 buildOpDecorate(ResVReg, *It, TII, SPIRV::Decoration::Alignment,
5313 {Alignment});
5314 }
5315 return true;
5316}
5317
5318bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const {
5319 // InstructionSelector walks backwards through the instructions. We can use
5320 // both a G_BR and a G_BRCOND to create an OpBranchConditional. We hit G_BR
5321 // first, so can generate an OpBranchConditional here. If there is no
5322 // G_BRCOND, we just use OpBranch for a regular unconditional branch.
5323 const MachineInstr *PrevI = I.getPrevNode();
5324 MachineBasicBlock &MBB = *I.getParent();
5325 if (PrevI != nullptr && PrevI->getOpcode() == TargetOpcode::G_BRCOND) {
5326 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional))
5327 .addUse(PrevI->getOperand(0).getReg())
5328 .addMBB(PrevI->getOperand(1).getMBB())
5329 .addMBB(I.getOperand(0).getMBB())
5330 .constrainAllUses(TII, TRI, RBI);
5331 return true;
5332 }
5333 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch))
5334 .addMBB(I.getOperand(0).getMBB())
5335 .constrainAllUses(TII, TRI, RBI);
5336 return true;
5337}
5338
5339bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const {
5340 // InstructionSelector walks backwards through the instructions. For an
5341 // explicit conditional branch with no fallthrough, we use both a G_BR and a
5342 // G_BRCOND to create an OpBranchConditional. We should hit G_BR first, and
5343 // generate the OpBranchConditional in selectBranch above.
5344 //
5345 // If an OpBranchConditional has been generated, we simply return, as the work
5346 // is alread done. If there is no OpBranchConditional, LLVM must be relying on
5347 // implicit fallthrough to the next basic block, so we need to create an
5348 // OpBranchConditional with an explicit "false" argument pointing to the next
5349 // basic block that LLVM would fall through to.
5350 const MachineInstr *NextI = I.getNextNode();
5351 // Check if this has already been successfully selected.
5352 if (NextI != nullptr && NextI->getOpcode() == SPIRV::OpBranchConditional)
5353 return true;
5354 // Must be relying on implicit block fallthrough, so generate an
5355 // OpBranchConditional with the "next" basic block as the "false" target.
5356 MachineBasicBlock &MBB = *I.getParent();
5357 unsigned NextMBBNum = MBB.getNextNode()->getNumber();
5358 MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum);
5359 BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional))
5360 .addUse(I.getOperand(0).getReg())
5361 .addMBB(I.getOperand(1).getMBB())
5362 .addMBB(NextMBB)
5363 .constrainAllUses(TII, TRI, RBI);
5364 return true;
5365}
5366
5367bool SPIRVInstructionSelector::selectPhi(Register ResVReg,
5368 MachineInstr &I) const {
5369 auto MIB =
5370 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::PHI))
5371 .addDef(ResVReg);
5372 const unsigned NumOps = I.getNumOperands();
5373 for (unsigned i = 1; i < NumOps; i += 2) {
5374 MIB.addUse(I.getOperand(i + 0).getReg());
5375 MIB.addMBB(I.getOperand(i + 1).getMBB());
5376 }
5377 MIB.constrainAllUses(TII, TRI, RBI);
5378 return true;
5379}
5380
5381bool SPIRVInstructionSelector::selectGlobalValue(
5382 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const {
5383 // FIXME: don't use MachineIRBuilder here, replace it with BuildMI.
5384 MachineIRBuilder MIRBuilder(I);
5385 const GlobalValue *GV = I.getOperand(1).getGlobal();
5386 Type *GVType = toTypedPointer(GR.getDeducedGlobalValueType(GV));
5387
5388 std::string GlobalIdent;
5389 if (!GV->hasName()) {
5390 unsigned &ID = UnnamedGlobalIDs[GV];
5391 if (ID == 0)
5392 ID = UnnamedGlobalIDs.size();
5393 GlobalIdent = "__unnamed_" + Twine(ID).str();
5394 } else {
5395 GlobalIdent = GV->getName();
5396 }
5397
5398 // Behaviour of functions as operands depends on availability of the
5399 // corresponding extension (SPV_INTEL_function_pointers):
5400 // - If there is an extension to operate with functions as operands:
5401 // We create a proper constant operand and evaluate a correct type for a
5402 // function pointer.
5403 // - Without the required extension:
5404 // We have functions as operands in tests with blocks of instruction e.g. in
5405 // transcoding/global_block.ll. These operands are not used and should be
5406 // substituted by zero constants. Their type is expected to be always
5407 // OpTypePointer Function %uchar.
5408 if (isa<Function>(GV)) {
5409 const Constant *ConstVal = GV;
5410 MachineBasicBlock &BB = *I.getParent();
5411 Register NewReg = GR.find(ConstVal, GR.CurMF);
5412 if (!NewReg.isValid()) {
5413 const Function *GVFun =
5414 STI.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)
5415 ? dyn_cast<Function>(GV)
5416 : nullptr;
5417 SPIRVTypeInst ResType = GR.getOrCreateSPIRVPointerType(
5418 GVType, I,
5419 GVFun ? SPIRV::StorageClass::CodeSectionINTEL
5420 : addressSpaceToStorageClass(GV->getAddressSpace(), STI));
5421 if (GVFun) {
5422 // References to a function via function pointers generate virtual
5423 // registers without a definition. We will resolve it later, during
5424 // module analysis stage.
5425 Register ResTypeReg = GR.getSPIRVTypeID(ResType);
5426 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
5427 Register FuncVReg =
5428 MRI->createGenericVirtualRegister(GR.getRegType(ResType));
5429 MRI->setRegClass(FuncVReg, &SPIRV::pIDRegClass);
5430 GR.assignSPIRVTypeToVReg(ResType, FuncVReg, *GR.CurMF);
5431 MachineInstrBuilder MIB1 =
5432 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
5433 .addDef(FuncVReg)
5434 .addUse(ResTypeReg);
5435 MachineInstrBuilder MIB2 =
5436 BuildMI(BB, I, I.getDebugLoc(),
5437 TII.get(SPIRV::OpConstantFunctionPointerINTEL))
5438 .addDef(ResVReg)
5439 .addUse(ResTypeReg)
5440 .addUse(FuncVReg);
5441 GR.add(ConstVal, MIB2);
5442 // mapping the function pointer to the used Function
5443 GR.recordFunctionPointer(&MIB2.getInstr()->getOperand(2), GVFun);
5444 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
5445 MIB1.constrainAllUses(TII, TRI, RBI);
5446 MIB2.constrainAllUses(TII, TRI, RBI);
5447 return true;
5448 }
5449 MachineInstrBuilder MIB3 =
5450 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
5451 .addDef(ResVReg)
5452 .addUse(GR.getSPIRVTypeID(ResType));
5453 GR.add(ConstVal, MIB3);
5454 MIB3.constrainAllUses(TII, TRI, RBI);
5455 return true;
5456 }
5457 assert(NewReg != ResVReg);
5458 return BuildCOPY(ResVReg, NewReg, I);
5459 }
5460 auto GlobalVar = cast<GlobalVariable>(GV);
5461 assert(GlobalVar->getName() != "llvm.global.annotations");
5462
5463 // Skip empty declaration for GVs with initializers till we get the decl with
5464 // passed initializer.
5465 if (hasInitializer(GlobalVar) && !Init)
5466 return true;
5467
5468 const std::optional<SPIRV::LinkageType::LinkageType> LnkType =
5469 getSpirvLinkageTypeFor(STI, *GV);
5470
5471 const unsigned AddrSpace = GV->getAddressSpace();
5472 SPIRV::StorageClass::StorageClass StorageClass =
5473 addressSpaceToStorageClass(AddrSpace, STI);
5474 SPIRVTypeInst ResType =
5475 GR.getOrCreateSPIRVPointerType(GVType, I, StorageClass);
5476 Register Reg = GR.buildGlobalVariable(
5477 ResVReg, ResType, GlobalIdent, GV, StorageClass, Init,
5478 GlobalVar->isConstant(), LnkType, MIRBuilder, true);
5479 // TODO: For AMDGCN, we pipe externally_initialized through via
5480 // HostAccessINTEL, with ReadWrite (3) access, which is we then handle during
5481 // reverse translation. We should remove this once SPIR-V gains the ability to
5482 // express the concept.
5483 if (GlobalVar->isExternallyInitialized() &&
5484 STI.getTargetTriple().getVendor() == Triple::AMD) {
5485 constexpr unsigned ReadWriteINTEL = 3u;
5486 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::HostAccessINTEL,
5487 {ReadWriteINTEL});
5488 MachineInstrBuilder MIB(*MF, --MIRBuilder.getInsertPt());
5489 addStringImm(GV->getName(), MIB);
5490 }
5491 return Reg.isValid();
5492}
5493
5494bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
5495 SPIRVTypeInst ResType,
5496 MachineInstr &I) const {
5497 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
5498 return selectExtInst(ResVReg, ResType, I, CL::log10);
5499 }
5500
5501 // There is no log10 instruction in the GLSL Extended Instruction set, so it
5502 // is implemented as:
5503 // log10(x) = log2(x) * (1 / log2(10))
5504 // = log2(x) * 0.30103
5505
5506 MachineIRBuilder MIRBuilder(I);
5507 MachineBasicBlock &BB = *I.getParent();
5508
5509 // Build log2(x).
5510 Register VarReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
5511 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
5512 .addDef(VarReg)
5513 .addUse(GR.getSPIRVTypeID(ResType))
5514 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
5515 .addImm(GL::Log2)
5516 .add(I.getOperand(1))
5517 .constrainAllUses(TII, TRI, RBI);
5518
5519 // Build 0.30103.
5520 assert(ResType->getOpcode() == SPIRV::OpTypeVector ||
5521 ResType->getOpcode() == SPIRV::OpTypeFloat);
5522 // TODO: Add matrix implementation once supported by the HLSL frontend.
5523 SPIRVTypeInst SpirvScalarType = ResType->getOpcode() == SPIRV::OpTypeVector
5524 ? SPIRVTypeInst(GR.getSPIRVTypeForVReg(
5525 ResType->getOperand(1).getReg()))
5526 : ResType;
5527 Register ScaleReg =
5528 GR.buildConstantFP(APFloat(0.30103f), MIRBuilder, SpirvScalarType);
5529
5530 // Multiply log2(x) by 0.30103 to get log10(x) result.
5531 auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector
5532 ? SPIRV::OpVectorTimesScalar
5533 : SPIRV::OpFMulS;
5534 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
5535 .addDef(ResVReg)
5536 .addUse(GR.getSPIRVTypeID(ResType))
5537 .addUse(VarReg)
5538 .addUse(ScaleReg)
5539 .constrainAllUses(TII, TRI, RBI);
5540 return true;
5541}
5542
5543bool SPIRVInstructionSelector::selectModf(Register ResVReg,
5544 SPIRVTypeInst ResType,
5545 MachineInstr &I) const {
5546 // llvm.modf has a single arg --the number to be decomposed-- and returns a
5547 // struct { restype, restype }, while OpenCLLIB::modf has two args --the
5548 // number to be decomposed and a pointer--, returns the fractional part and
5549 // the integral part is stored in the pointer argument. Therefore, we can't
5550 // use directly the OpenCLLIB::modf intrinsic. However, we can do some
5551 // scaffolding to make it work. The idea is to create an alloca instruction
5552 // to get a ptr, pass this ptr to OpenCL::modf, and then load the value
5553 // from this ptr to place it in the struct. llvm.modf returns the fractional
5554 // part as the first element of the result, and the integral part as the
5555 // second element of the result.
5556
5557 // At this point, the return type is not a struct anymore, but rather two
5558 // independent elements of SPIRVResType. We can get each independent element
5559 // from I.getDefs() or I.getOperands().
5560 if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
5561 MachineIRBuilder MIRBuilder(I);
5562 // Get pointer type for alloca variable.
5563 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5564 ResType, MIRBuilder, SPIRV::StorageClass::Function);
5565 // Create new register for the pointer type of alloca variable.
5566 Register PtrTyReg =
5567 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
5568 MIRBuilder.getMRI()->setType(
5569 PtrTyReg,
5570 LLT::pointer(storageClassToAddressSpace(SPIRV::StorageClass::Function),
5571 GR.getPointerSize()));
5572
5573 // Assign SPIR-V type of the pointer type of the alloca variable to the
5574 // new register.
5575 GR.assignSPIRVTypeToVReg(PtrType, PtrTyReg, MIRBuilder.getMF());
5576 MachineBasicBlock &EntryBB = I.getMF()->front();
5577 MachineBasicBlock::iterator VarPos =
5578 getFirstValidInstructionInsertPoint(EntryBB);
5579 auto AllocaMIB =
5580 BuildMI(EntryBB, VarPos, I.getDebugLoc(), TII.get(SPIRV::OpVariable))
5581 .addDef(PtrTyReg)
5582 .addUse(GR.getSPIRVTypeID(PtrType))
5583 .addImm(static_cast<uint32_t>(SPIRV::StorageClass::Function));
5584 Register Variable = AllocaMIB->getOperand(0).getReg();
5585
5586 MachineBasicBlock &BB = *I.getParent();
5587 // Create the OpenCLLIB::modf instruction.
5588 auto MIB =
5589 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
5590 .addDef(ResVReg)
5591 .addUse(GR.getSPIRVTypeID(ResType))
5592 .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
5593 .addImm(CL::modf)
5594 .setMIFlags(I.getFlags())
5595 .add(I.getOperand(I.getNumExplicitDefs())) // Floating point value.
5596 .addUse(Variable); // Pointer to integral part.
5597 // Assign the integral part stored in the ptr to the second element of the
5598 // result.
5599 Register IntegralPartReg = I.getOperand(1).getReg();
5600 if (IntegralPartReg.isValid()) {
5601 // Load the value from the pointer to integral part.
5602 auto LoadMIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5603 .addDef(IntegralPartReg)
5604 .addUse(GR.getSPIRVTypeID(ResType))
5605 .addUse(Variable);
5606 LoadMIB.constrainAllUses(TII, TRI, RBI);
5607 return true;
5608 }
5609
5610 MIB.constrainAllUses(TII, TRI, RBI);
5611 return true;
5612 } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) {
5613 assert(false && "GLSL::Modf is deprecated.");
5614 // FIXME: GL::Modf is deprecated, use Modfstruct instead.
5615 return false;
5616 }
5617 return false;
5618}
5619
5620// Generate the instructions to load 3-element vector builtin input
5621// IDs/Indices.
5622// Like: GlobalInvocationId, LocalInvocationId, etc....
5623
5624bool SPIRVInstructionSelector::loadVec3BuiltinInputID(
5625 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
5626 SPIRVTypeInst ResType, MachineInstr &I) const {
5627 MachineIRBuilder MIRBuilder(I);
5628 const SPIRVTypeInst Vec3Ty =
5629 GR.getOrCreateSPIRVVectorType(ResType, 3, MIRBuilder, false);
5630 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5631 Vec3Ty, MIRBuilder, SPIRV::StorageClass::Input);
5632
5633 // Create new register for the input ID builtin variable.
5634 Register NewRegister =
5635 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
5636 MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 64));
5637 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
5638
5639 // Build global variable with the necessary decorations for the input ID
5640 // builtin variable.
5641 Register Variable = GR.buildGlobalVariable(
5642 NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
5643 SPIRV::StorageClass::Input, nullptr, true, std::nullopt, MIRBuilder,
5644 false);
5645
5646 // Create new register for loading value.
5647 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
5648 Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
5649 MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 64));
5650 GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
5651
5652 // Load v3uint value from the global variable.
5653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5654 .addDef(LoadedRegister)
5655 .addUse(GR.getSPIRVTypeID(Vec3Ty))
5656 .addUse(Variable);
5657
5658 // Get the input ID index. Expecting operand is a constant immediate value,
5659 // wrapped in a type assignment.
5660 assert(I.getOperand(2).isReg());
5661 const uint32_t ThreadId = foldImm(I.getOperand(2), MRI);
5662
5663 // Extract the input ID from the loaded vector value.
5664 MachineBasicBlock &BB = *I.getParent();
5665 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
5666 .addDef(ResVReg)
5667 .addUse(GR.getSPIRVTypeID(ResType))
5668 .addUse(LoadedRegister)
5669 .addImm(ThreadId);
5670 MIB.constrainAllUses(TII, TRI, RBI);
5671 return true;
5672}
5673
5674// Generate the instructions to load 32-bit integer builtin input IDs/Indices.
5675// Like LocalInvocationIndex
5676bool SPIRVInstructionSelector::loadBuiltinInputID(
5677 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
5678 SPIRVTypeInst ResType, MachineInstr &I) const {
5679 MachineIRBuilder MIRBuilder(I);
5680 const SPIRVTypeInst PtrType = GR.getOrCreateSPIRVPointerType(
5681 ResType, MIRBuilder, SPIRV::StorageClass::Input);
5682
5683 // Create new register for the input ID builtin variable.
5684 Register NewRegister =
5685 MIRBuilder.getMRI()->createVirtualRegister(GR.getRegClass(PtrType));
5686 MIRBuilder.getMRI()->setType(
5687 NewRegister,
5688 LLT::pointer(storageClassToAddressSpace(SPIRV::StorageClass::Input),
5689 GR.getPointerSize()));
5690 GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
5691
5692 // Build global variable with the necessary decorations for the input ID
5693 // builtin variable.
5694 Register Variable = GR.buildGlobalVariable(
5695 NewRegister, PtrType, getLinkStringForBuiltIn(BuiltInValue), nullptr,
5696 SPIRV::StorageClass::Input, nullptr, true, std::nullopt, MIRBuilder,
5697 false);
5698
5699 // Load uint value from the global variable.
5700 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad))
5701 .addDef(ResVReg)
5702 .addUse(GR.getSPIRVTypeID(ResType))
5703 .addUse(Variable);
5704
5705 MIB.constrainAllUses(TII, TRI, RBI);
5706 return true;
5707}
5708
5709SPIRVTypeInst SPIRVInstructionSelector::widenTypeToVec4(SPIRVTypeInst Type,
5710 MachineInstr &I) const {
5711 MachineIRBuilder MIRBuilder(I);
5712 if (Type->getOpcode() != SPIRV::OpTypeVector)
5713 return GR.getOrCreateSPIRVVectorType(Type, 4, MIRBuilder, false);
5714
5715 uint64_t VectorSize = Type->getOperand(2).getImm();
5716 if (VectorSize == 4)
5717 return Type;
5718
5719 Register ScalarTypeReg = Type->getOperand(1).getReg();
5720 const SPIRVTypeInst ScalarType = GR.getSPIRVTypeForVReg(ScalarTypeReg);
5721 return GR.getOrCreateSPIRVVectorType(ScalarType, 4, MIRBuilder, false);
5722}
5723
5724bool SPIRVInstructionSelector::loadHandleBeforePosition(
5725 Register &HandleReg, SPIRVTypeInst ResType, GIntrinsic &HandleDef,
5726 MachineInstr &Pos) const {
5727
5728 assert(HandleDef.getIntrinsicID() ==
5729 Intrinsic::spv_resource_handlefrombinding);
5730 uint32_t Set = foldImm(HandleDef.getOperand(2), MRI);
5731 uint32_t Binding = foldImm(HandleDef.getOperand(3), MRI);
5732 uint32_t ArraySize = foldImm(HandleDef.getOperand(4), MRI);
5733 Register IndexReg = HandleDef.getOperand(5).getReg();
5734 std::string Name =
5735 getStringValueFromReg(HandleDef.getOperand(6).getReg(), *MRI);
5736
5737 bool IsStructuredBuffer = ResType->getOpcode() == SPIRV::OpTypePointer;
5738 MachineIRBuilder MIRBuilder(HandleDef);
5739 SPIRVTypeInst VarType = ResType;
5740 SPIRV::StorageClass::StorageClass SC = SPIRV::StorageClass::UniformConstant;
5741
5742 if (IsStructuredBuffer) {
5743 VarType = GR.getPointeeType(ResType);
5744 SC = GR.getPointerStorageClass(ResType);
5745 }
5746
5747 Register VarReg =
5748 buildPointerToResource(SPIRVTypeInst(VarType), SC, Set, Binding,
5749 ArraySize, IndexReg, Name, MIRBuilder);
5750
5751 // The handle for the buffer is the pointer to the resource. For an image, the
5752 // handle is the image object. So images get an extra load.
5753 uint32_t LoadOpcode =
5754 IsStructuredBuffer ? SPIRV::OpCopyObject : SPIRV::OpLoad;
5755 GR.assignSPIRVTypeToVReg(ResType, HandleReg, *Pos.getMF());
5756 BuildMI(*Pos.getParent(), Pos, HandleDef.getDebugLoc(), TII.get(LoadOpcode))
5757 .addDef(HandleReg)
5758 .addUse(GR.getSPIRVTypeID(ResType))
5759 .addUse(VarReg)
5760 .constrainAllUses(TII, TRI, RBI);
5761 return true;
5762}
5763
5764void SPIRVInstructionSelector::errorIfInstrOutsideShader(
5765 MachineInstr &I) const {
5766 if (!STI.isShader()) {
5767 std::string DiagMsg;
5768 raw_string_ostream OS(DiagMsg);
5769 I.print(OS, true, false, false, false);
5770 DiagMsg += " is only supported in shaders.\n";
5771 report_fatal_error(DiagMsg.c_str(), false);
5772 }
5773}
5774
5775namespace llvm {
5776InstructionSelector *
5777createSPIRVInstructionSelector(const SPIRVTargetMachine &TM,
5778 const SPIRVSubtarget &Subtarget,
5779 const RegisterBankInfo &RBI) {
5780 return new SPIRVInstructionSelector(TM, Subtarget, RBI);
5781}
5782} // namespace llvm
MRI
unsigned const MachineRegisterInfo * MRI
Definition AArch64AdvSIMDScalarPass.cpp:103
UseMI
MachineInstrBuilder & UseMI
Definition AArch64ExpandPseudoInsts.cpp:123
GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_PREDICATES_INIT
GET_GLOBALISEL_TEMPORARIES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Generic
@ Generic
Definition AArch64MCAsmInfo.cpp:24
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
selectUnmergeValues
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Definition ARMInstructionSelector.cpp:264
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
true
basic Basic Alias true
Definition BasicAliasAnalysis.cpp:2037
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Binding
DXIL Resource Implicit Binding
Definition DXILResourceImplicitBinding.cpp:185
DEBUG_TYPE
#define DEBUG_TYPE
Definition GenericCycleImpl.h:31
GenericMachineInstrs.h
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LLVMIntType
LLVMTypeRef LLVMIntType(unsigned NumBits)
Definition Core.cpp:717
NumOps
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
Definition ItaniumDemangle.h:3452
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2119
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2120
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
II
uint64_t IntrinsicInst * II
Definition NVVMIntrRange.cpp:46
getName
static StringRef getName(Value *V)
Definition ProvenanceAnalysisEvaluator.cpp:20
getFCmpOpcode
static unsigned getFCmpOpcode(CmpInst::Predicate Pred, unsigned Size)
Definition RISCVInstructionSelector.cpp:1825
getOneFP
static APFloat getOneFP(const Type *LLVMFloatTy)
Definition SPIRVInstructionSelector.cpp:2388
isUSMStorageClass
static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVInstructionSelector.cpp:2121
isASCastInGVar
static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg)
Definition SPIRVInstructionSelector.cpp:2132
mayApplyGenericSelection
static bool mayApplyGenericSelection(unsigned Opcode)
Definition SPIRVInstructionSelector.cpp:869
getZeroFP
static APFloat getZeroFP(const Type *LLVMFloatTy)
Definition SPIRVInstructionSelector.cpp:2374
ExtInstList
std::vector< std::pair< SPIRV::InstructionSet::InstructionSet, uint32_t > > ExtInstList
Definition SPIRVInstructionSelector.cpp:42
intrinsicHasSideEffects
static bool intrinsicHasSideEffects(Intrinsic::ID ID)
Definition SPIRVInstructionSelector.cpp:583
getBoolCmpOpcode
static unsigned getBoolCmpOpcode(unsigned PredNum)
Definition SPIRVInstructionSelector.cpp:2362
getICmpOpcode
static unsigned getICmpOpcode(unsigned PredNum)
Definition SPIRVInstructionSelector.cpp:2322
isOpcodeWithNoSideEffects
static bool isOpcodeWithNoSideEffects(unsigned Opcode)
Definition SPIRVInstructionSelector.cpp:649
addMemoryOperands
static void addMemoryOperands(MachineMemOperand *MemOp, MachineInstrBuilder &MIB, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry &GR)
Definition SPIRVInstructionSelector.cpp:1578
isConstReg
static bool isConstReg(MachineRegisterInfo *MRI, MachineInstr *OpDef)
Definition SPIRVInstructionSelector.cpp:518
getPtrCmpOpcode
static unsigned getPtrCmpOpcode(unsigned Pred)
Definition SPIRVInstructionSelector.cpp:2350
getVectorSizeOrOne
unsigned getVectorSizeOrOne(SPIRVTypeInst Type)
Definition SPIRVInstructionSelector.cpp:2827
isDead
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition SPIRVInstructionSelector.cpp:683
SPIRV
spirv structurize SPIRV
Definition SPIRVStructurizer.cpp:1222
BaseType
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
Definition SafepointIRVerifier.cpp:311
StringExtras.h
This file contains some functions that are useful when dealing with strings.
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:114
Y
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
X
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::APFloatBase::IEEEsingle
static const fltSemantics & IEEEsingle()
Definition APFloat.h:296
llvm::APFloatBase::IEEEdouble
static const fltSemantics & IEEEdouble()
Definition APFloat.h:297
llvm::APFloatBase::IEEEhalf
static const fltSemantics & IEEEhalf()
Definition APFloat.h:294
llvm::APFloat::getOne
static APFloat getOne(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative One.
Definition APFloat.h:1143
llvm::APFloat::getZero
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Definition APFloat.h:1134
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition APInt.h:235
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:676
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition InstrTypes.h:679
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition InstrTypes.h:705
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition InstrTypes.h:706
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition InstrTypes.h:682
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition InstrTypes.h:691
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition InstrTypes.h:680
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition InstrTypes.h:681
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition InstrTypes.h:700
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition InstrTypes.h:699
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition InstrTypes.h:703
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition InstrTypes.h:690
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition InstrTypes.h:684
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition InstrTypes.h:687
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition InstrTypes.h:701
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition InstrTypes.h:688
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition InstrTypes.h:683
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition InstrTypes.h:685
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition InstrTypes.h:698
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition InstrTypes.h:704
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition InstrTypes.h:692
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition InstrTypes.h:702
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition InstrTypes.h:689
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition InstrTypes.h:686
llvm::Constant::getNullValue
static LLVM_ABI Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition Constants.cpp:374
llvm::DenseMapBase::size
unsigned size() const
Definition DenseMap.h:110
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition Function.cpp:358
llvm::GIntrinsic::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition GenericMachineInstrs.h:531
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition GlobalValue.h:207
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition GlobalValue.h:663
llvm::GlobalValue::InternalLinkage
@ InternalLinkage
Rename collisions when linking (static functions).
Definition GlobalValue.h:60
llvm::IntegerType::get
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition Type.cpp:318
llvm::LLT::scalar
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition LowLevelType.h:43
llvm::LLT::isValid
constexpr bool isValid() const
Definition LowLevelType.h:146
llvm::LLT::getNumElements
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition LowLevelType.h:160
llvm::LLT::isVector
constexpr bool isVector() const
Definition LowLevelType.h:149
llvm::LLT::pointer
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition LowLevelType.h:58
llvm::LLT::fixed_vector
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition LowLevelType.h:101
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition MachineBasicBlock.h:1269
llvm::MachineBasicBlock::getFirstNonPHI
LLVM_ABI iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition MachineBasicBlock.cpp:200
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:325
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:343
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:801
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition MachineFunction.h:752
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:237
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition MachineIRBuilder.h:335
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition MachineIRBuilder.h:423
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition MachineIRBuilder.h:289
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition MachineIRBuilder.h:311
llvm::MachineInstrBuilder::constrainAllUses
void constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition MachineInstrBuilder.h:441
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register use operand.
Definition MachineInstrBuilder.h:225
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition MachineInstrBuilder.h:379
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition MachineInstrBuilder.h:191
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition MachineInstr.h:599
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition MachineInstr.h:371
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition MachineInstr.h:602
llvm::MachineInstr::getNumExplicitDefs
LLVM_ABI unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Definition MachineInstr.cpp:869
llvm::MachineInstr::emitGenericError
LLVM_ABI void emitGenericError(const Twine &ErrMsg) const
Definition MachineInstr.cpp:2373
llvm::MachineInstr::getMF
LLVM_ABI const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition MachineInstr.cpp:786
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition MachineInstr.h:523
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition MachineInstr.h:607
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition MachineMemOperand.h:141
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition MachineMemOperand.h:143
llvm::MachineOperand::getImm
int64_t getImm() const
Definition MachineOperand.h:560
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition MachineOperand.h:331
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition MachineOperand.h:575
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition MachineOperand.h:372
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::MachineRegisterInfo::use_instr_iterator
defusechain_instr_iterator< true, false, false, true > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
Definition MachineRegisterInfo.h:478
llvm::MachineRegisterInfo::def_instr_iterator
defusechain_instr_iterator< false, true, false, true > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
Definition MachineRegisterInfo.h:399
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::MachineRegisterInfo::setType
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition MachineRegisterInfo.cpp:185
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition RegisterBankInfo.h:40
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::Register::isValid
constexpr bool isValid() const
Definition Register.h:112
llvm::Register::isPhysical
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:83
llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned
bool isScalarOrVectorSigned(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1443
llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage
SPIRVTypeInst getOrCreateOpTypeSampledImage(SPIRVTypeInst ImageType, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:1691
llvm::SPIRVGlobalRegistry::assignSPIRVTypeToVReg
void assignSPIRVTypeToVReg(SPIRVTypeInst Type, Register VReg, const MachineFunction &MF)
Definition SPIRVGlobalRegistry.cpp:130
llvm::SPIRVGlobalRegistry::getRegClass
const TargetRegisterClass * getRegClass(SPIRVTypeInst SpvType) const
Definition SPIRVGlobalRegistry.cpp:2050
llvm::SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst
MachineInstr * getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD)
Definition SPIRVGlobalRegistry.cpp:2115
llvm::SPIRVGlobalRegistry::isAggregateType
bool isAggregateType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.h:371
llvm::SPIRVGlobalRegistry::getScalarOrVectorBitWidth
unsigned getScalarOrVectorBitWidth(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1408
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType
SPIRVTypeInst getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:1821
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVVectorType
SPIRVTypeInst getOrCreateSPIRVVectorType(SPIRVTypeInst BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder, bool EmitIR)
Definition SPIRVGlobalRegistry.cpp:1920
llvm::SPIRVGlobalRegistry::buildGlobalVariable
Register buildGlobalVariable(Register Reg, SPIRVTypeInst BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, const std::optional< SPIRV::LinkageType::LinkageType > &LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
Definition SPIRVGlobalRegistry.cpp:780
llvm::SPIRVGlobalRegistry::getResultType
SPIRVTypeInst getResultType(Register VReg, MachineFunction *MF=nullptr)
Definition SPIRVGlobalRegistry.cpp:1291
llvm::SPIRVGlobalRegistry::getScalarOrVectorComponentCount
unsigned getScalarOrVectorComponentCount(Register VReg) const
Definition SPIRVGlobalRegistry.cpp:1381
llvm::SPIRVGlobalRegistry::getTypeForSPIRVType
const Type * getTypeForSPIRVType(SPIRVTypeInst Ty) const
Definition SPIRVGlobalRegistry.h:324
llvm::SPIRVGlobalRegistry::isBitcastCompatible
bool isBitcastCompatible(SPIRVTypeInst Type1, SPIRVTypeInst Type2) const
Definition SPIRVGlobalRegistry.cpp:1459
llvm::SPIRVGlobalRegistry::getOrCreateConstFP
Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:334
llvm::SPIRVGlobalRegistry::getRegType
LLT getRegType(SPIRVTypeInst SpvType) const
Definition SPIRVGlobalRegistry.cpp:2077
llvm::SPIRVGlobalRegistry::invalidateMachineInstr
void invalidateMachineInstr(MachineInstr *MI)
Definition SPIRVGlobalRegistry.cpp:233
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVBoolType
SPIRVTypeInst getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder, bool EmitIR)
Definition SPIRVGlobalRegistry.cpp:1895
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVPointerType
SPIRVTypeInst getOrCreateSPIRVPointerType(const Type *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC)
Definition SPIRVGlobalRegistry.cpp:1958
llvm::SPIRVGlobalRegistry::isScalarOfType
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Definition SPIRVGlobalRegistry.cpp:1346
llvm::SPIRVGlobalRegistry::getSPIRVTypeID
Register getSPIRVTypeID(SPIRVTypeInst SpirvType) const
Definition SPIRVGlobalRegistry.cpp:1122
llvm::SPIRVGlobalRegistry::getOrCreateConstInt
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:387
llvm::SPIRVGlobalRegistry::getOrCreateConstIntArray
Register getOrCreateConstIntArray(uint64_t Val, size_t Num, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:646
llvm::SPIRVGlobalRegistry::findValueAttrs
bool findValueAttrs(const MachineInstr *Key, Type *&Ty, StringRef &Name)
Definition SPIRVGlobalRegistry.h:176
llvm::SPIRVGlobalRegistry::retrieveScalarOrVectorIntType
SPIRVTypeInst retrieveScalarOrVectorIntType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1437
llvm::SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding
Register getOrCreateGlobalVariableWithBinding(SPIRVTypeInst VarType, uint32_t Set, uint32_t Binding, StringRef Name, MachineIRBuilder &MIRBuilder)
Definition SPIRVGlobalRegistry.cpp:885
llvm::SPIRVGlobalRegistry::changePointerStorageClass
SPIRVTypeInst changePointerStorageClass(SPIRVTypeInst PtrType, SPIRV::StorageClass::StorageClass SC, MachineInstr &I)
Definition SPIRVGlobalRegistry.cpp:1969
llvm::SPIRVGlobalRegistry::getOrCreateConstVector
Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Definition SPIRVGlobalRegistry.cpp:597
llvm::SPIRVGlobalRegistry::buildConstantFP
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType=nullptr)
Definition SPIRVGlobalRegistry.cpp:501
llvm::SPIRVGlobalRegistry::addGlobalObject
void addGlobalObject(const Value *V, const MachineFunction *MF, Register R)
Definition SPIRVGlobalRegistry.h:122
llvm::SPIRVGlobalRegistry::getScalarOrVectorComponentType
SPIRVTypeInst getScalarOrVectorComponentType(SPIRVTypeInst Type) const
Definition SPIRVGlobalRegistry.cpp:1395
llvm::SPIRVGlobalRegistry::recordFunctionPointer
void recordFunctionPointer(const MachineOperand *MO, const Function *F)
Definition SPIRVGlobalRegistry.h:259
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVFloatType
SPIRVTypeInst getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:1874
llvm::SPIRVGlobalRegistry::getPointeeType
SPIRVTypeInst getPointeeType(SPIRVTypeInst PtrType)
Definition SPIRVGlobalRegistry.cpp:1448
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVType
SPIRVTypeInst getOrCreateSPIRVType(const Type *Type, MachineInstr &I, SPIRV::AccessQualifier::AccessQualifier AQ, bool EmitIR)
Definition SPIRVGlobalRegistry.h:310
llvm::SPIRVGlobalRegistry::isScalarOrVectorOfType
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
Definition SPIRVGlobalRegistry.cpp:1353
llvm::SPIRVGlobalRegistry::setCurrentFunc
MachineFunction * setCurrentFunc(MachineFunction &MF)
Definition SPIRVGlobalRegistry.h:364
llvm::SPIRVGlobalRegistry::getOrCreateConstNullPtr
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVTypeInst SpvType)
Definition SPIRVGlobalRegistry.cpp:729
llvm::SPIRVGlobalRegistry::getSPIRVTypeForVReg
SPIRVTypeInst getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
Definition SPIRVGlobalRegistry.cpp:1280
llvm::SPIRVGlobalRegistry::getDeducedGlobalValueType
Type * getDeducedGlobalValueType(const GlobalValue *Global)
Definition SPIRVGlobalRegistry.h:212
llvm::SPIRVGlobalRegistry::getOrCreateUndef
Register getOrCreateUndef(MachineInstr &I, SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII)
Definition SPIRVGlobalRegistry.cpp:2016
llvm::SPIRVGlobalRegistry::getPointerStorageClass
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
Definition SPIRVGlobalRegistry.cpp:1479
llvm::SPIRVIRMapping::erase
bool erase(const MachineInstr *MI)
Definition SPIRVIRMapping.h:211
llvm::SPIRVIRMapping::add
bool add(SPIRV::IRHandle Handle, const MachineInstr *MI)
Definition SPIRVIRMapping.h:189
llvm::SPIRVIRMapping::find
Register find(SPIRV::IRHandle Handle, const MachineFunction *MF)
Definition SPIRVIRMapping.h:235
llvm::SPIRVSubtarget::isPhysicalSPIRV
bool isPhysicalSPIRV() const
Definition SPIRVSubtarget.h:92
llvm::SPIRVSubtarget::isAtLeastSPIRVVer
bool isAtLeastSPIRVVer(VersionTuple VerToCompareTo) const
Definition SPIRVSubtarget.cpp:140
llvm::SPIRVSubtarget::canUseExtInstSet
bool canUseExtInstSet(SPIRV::InstructionSet::InstructionSet E) const
Definition SPIRVSubtarget.cpp:127
llvm::SPIRVSubtarget::isLogicalSPIRV
bool isLogicalSPIRV() const
Definition SPIRVSubtarget.h:89
llvm::SPIRVSubtarget::canUseExtension
bool canUseExtension(SPIRV::Extension::Extension E) const
Definition SPIRVSubtarget.cpp:123
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
Remove pointer from the set.
Definition SmallPtrSet.h:404
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition SmallPtrSet.h:389
llvm::SmallPtrSetImpl::contains
bool contains(ConstPtrType Ptr) const
Definition SmallPtrSet.h:461
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition SmallPtrSet.h:527
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition SmallVector.h:946
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition SmallVector.h:666
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:419
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1205
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition StringRef.h:143
llvm::StructType::get
static LLVM_ABI StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition Type.cpp:413
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
llvm::Type::HalfTyID
@ HalfTyID
16-bit floating point type
Definition Type.h:56
llvm::Type::FloatTyID
@ FloatTyID
32-bit floating point type
Definition Type.h:58
llvm::Type::DoubleTyID
@ DoubleTyID
64-bit floating point type
Definition Type.h:59
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:352
llvm::Type::isStructTy
bool isStructTy() const
True if this is an instance of StructType.
Definition Type.h:261
llvm::Type::isAggregateType
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition Type.h:304
llvm::Type::getTypeID
TypeID getTypeID() const
Return the type id for the type.
Definition Type.h:136
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition User.h:207
llvm::Value::hasName
bool hasName() const
Definition Value.h:262
llvm::Value::getName
LLVM_ABI StringRef getName() const
Return a constant reference to the value's name.
Definition Value.cpp:322
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition ilist_node.h:348
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::IsConst
constexpr char IsConst[]
Key for Kernel::Arg::Metadata::mIsConst.
Definition AMDGPUMetadata.h:197
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:34
llvm::rdf::Def
NodeAddr< DefNode * > Def
Definition RDFGraph.h:384
llvm::rdf::Instr
NodeAddr< InstrNode * > Instr
Definition RDFGraph.h:389
llvm::rdf::Use
NodeAddr< UseNode * > Use
Definition RDFGraph.h:385
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
llvm::buildOpName
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
Definition SPIRVUtils.cpp:187
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1739
llvm::getIConstValSext
int64_t getIConstValSext(Register ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:464
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isTypeFoldingSupported
bool isTypeFoldingSupported(unsigned Opcode)
Definition SPIRVUtils.cpp:1064
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
llvm::Int32Ty
FunctionAddr VTableAddr uintptr_t uintptr_t Int32Ty
Definition InstrProf.h:296
llvm::addNumImm
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
Definition SPIRVUtils.cpp:156
llvm::salvageDebugInfo
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition Utils.cpp:1726
llvm::constrainSelectedInstRegOperands
LLVM_ABI void constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition Utils.cpp:155
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition TargetOpcodes.h:30
llvm::createVirtualRegister
Register createVirtualRegister(SPIRVTypeInst SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF)
Definition SPIRVUtils.cpp:890
llvm::getArrayComponentCount
unsigned getArrayComponentCount(const MachineRegisterInfo *MRI, const MachineInstr *ResType)
Definition SPIRVUtils.cpp:1101
llvm::getIConstVal
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:458
llvm::createContinuedInstructions
SmallVector< MachineInstr *, 4 > createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode, unsigned MinWC, unsigned ContinuedOpcode, ArrayRef< Register > Args, Register ReturnRegister, Register TypeID)
Definition SPIRVUtils.cpp:955
llvm::getMemSemanticsForStorageClass
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.cpp:373
llvm::storageClassToAddressSpace
constexpr unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.h:247
llvm::getFirstValidInstructionInsertPoint
MachineBasicBlock::iterator getFirstValidInstructionInsertPoint(MachineBasicBlock &BB)
Definition SPIRVUtils.cpp:1107
llvm::buildOpDecorate
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition SPIRVUtils.cpp:214
llvm::getOpVariableMBBIt
MachineBasicBlock::iterator getOpVariableMBBIt(MachineInstr &I)
Definition SPIRVUtils.cpp:299
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1082
llvm::toTypedPointer
Type * toTypedPointer(Type *Ty)
Definition SPIRVUtils.h:461
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::isGenericCastablePtr
constexpr bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC)
Definition SPIRVUtils.h:232
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition SmallVector.h:1131
llvm::passCopy
MachineInstr * passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1069
llvm::isa
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
llvm::getSpirvLinkageTypeFor
std::optional< SPIRV::LinkageType::LinkageType > getSpirvLinkageTypeFor(const SPIRVSubtarget &ST, const GlobalValue &GV)
Definition SPIRVUtils.cpp:1199
llvm::errs
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition raw_ostream.cpp:904
llvm::addressSpaceToStorageClass
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
Definition SPIRVUtils.cpp:333
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition AtomicOrdering.h:56
llvm::getMemScope
SPIRV::Scope::Scope getMemScope(LLVMContext &Ctx, SyncScope::ID Id)
Definition SPIRVUtils.cpp:409
llvm::createSPIRVInstructionSelector
InstructionSelector * createSPIRVInstructionSelector(const SPIRVTargetMachine &TM, const SPIRVSubtarget &Subtarget, const RegisterBankInfo &RBI)
Definition SPIRVInstructionSelector.cpp:5777
llvm::getStringValueFromReg
std::string getStringValueFromReg(Register Reg, MachineRegisterInfo &MRI)
Definition SPIRVUtils.cpp:146
llvm::foldImm
int64_t foldImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:1091
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::ArrayRef
ArrayRef(const T &OneElt) -> ArrayRef< T >
llvm::getDefInstrMaybeConstant
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:435
llvm::BitWidth
constexpr unsigned BitWidth
Definition BitmaskEnum.h:219
llvm::cast
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:559
llvm::hasInitializer
bool hasInitializer(const GlobalVariable *GV)
Definition SPIRVUtils.h:349
llvm::addStringImm
void addStringImm(const StringRef &Str, MCInst &Inst)
Definition SPIRVUtils.cpp:117
llvm::getVRegDef
MachineInstr * getVRegDef(MachineRegisterInfo &MRI, Register Reg)
Definition SPIRVUtils.cpp:843
llvm::getMemSemantics
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord)
Definition SPIRVUtils.cpp:391
llvm::getLinkStringForBuiltIn
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue)
Definition SPIRVBaseInfo.cpp:202
llvm::isTriviallyDead
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition Utils.cpp:221
N
#define N
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