GATE 2026 OS PYQs | MEMORY MANAGEMENT AND VIRTUAL MEMORY

Consider contiguous allocation of physical memory to processes using a variable partitioning scheme. Suppose there are 8 holes in the memory of sizes: 20 KB, 4 KB, 25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are adjacent. Two processes arrive in order:

P1 = 16 KB
P2 = 9 KB

They are allocated memory using the best-fit technique. After allocating space to P1 and P2, the number of holes of size less than 8 KB is _______. Note 1K=2¹⁰

[GATE 2026 || SET-2 NAT || 2-mark]

[Tex]\begin{aligned} &\text{A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB.} \\ &\text{TLB reach is defined as the total amount of physical memory that} \\ &\text{can be accessed through the TLB entries.} \\ &\text{The paging system uses pages of size 4 KB. The virtual address space is 64 GB} \\ &\text{and physical address space is 1 GB.} \\ &\text{If each TLB entry stores:} \\ &\quad\bullet\ \text{a 4-bit process id} \\ &\quad\bullet\ \text{page number} \\ &\quad\bullet\ \text{frame number} \\ &\quad\bullet\ \text{a 2-bit control field} \\ &\text{then the size of the TLB (in bytes) is \_\_\_\_\_\_.} \\ &\textbf{Note:} \\ &1\text{K} = 2^{10}, 1\text{M} = 2^{20}, 1\text{G} = 2^{30}. \end{aligned}[/Tex]

[GATE 2026 || SET-2 NAT || 2-mark]

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a Translation Lookaside Buffer (TLB). Assume that when a page is evicted from main memory, the corresponding blocks in the cache are marked invalid.

For a given memory reference, which of the following sequences of events can NEVER happen? [GATE 2026 || SET-1 MSQ || 2-mark]