uv-xiao

I am a Ph.D. candidate at the School of IC, Peking University, advised by Prof. Yun Liang. My research focuses on software techniques for compiler-architecture-hardware full-stack co-optimization, with emphasis on domain-specific languages (DSLs), compiler techniques, and hardware synthesis frameworks. Before that, I received my Bachelor of Science in EECS at Peking University in 2022.

My research work centers on developing EDA software techniques that bridge the gap between high-level architectural specifications and low-level hardware implementations. I have contributed to several projects focusing on multi-level intermediate representations, hardware synthesis frameworks, and domain-specific processor customization. Notable contributions include the development of the open-source hardware description language Cement (FPGA 2024) and the high-level synthesis framework Hector (ICCAD 2022), as well as work on automatic accelerator generation with control flow and data access optimization (Cayman, DAC 2025). Currently, I am working on frameworks for automatic processor instruction customization using equivalence anti-unification techniques and full-stack solutions for domain-specific processor design (ISAMORE, to appear at ASPLOS 2026).

I’m thinking about exploring composite compilation techniques that integrate formal methods with large language models for architecture-hardware co-optimization (EggMind, to come soon). I’m also interested in software techniques for architecture exploration with comprehensive modeling of data movement patterns and microarchitecture design spaces in mind, and get both hardware and evaluation in ONE CLICK. My ultimate dream is to establish comprehensive frameworks that enable unified abstraction-based architecture performance analysis, automatic optimization, and seamless hardware implementation generation. To achieve this goal, I initiated the APS project together with my lab classmates.

Based on my accumulated skills in compilation technology, DSL, and architecture, I am actively exploring a new generation of AI compiler frameworks. The system software stack for deploying and training LLM spans multiple levels including infrastructure, graph compilation, and operator compilation, and requires retargetable capabilities for different hardware architectures. I believe the potential role of compilation in the AI system stack has yet to be fully realized. Currently, I am deeply researching frameworks and optimizations for MegaKernels that can fully leverage compilation (both graph-level and kernel-level) potential in multi-node scenarios. I hope to share my results as soon as possible.