I've seen that Xilinx is getting rid of XDL as of ISE 14. Is this still true? I've also looked at the TCL interface to "replace" it, but is doesn't seem to provide similar functionality at all.
Is there a plan for support going forward? I'm currently designing for a Zynq, which appears to require ISE 14 for support.
~John
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We are currently looking into a Vivado equivalent for XDL and are very optimistic. This may require some changes in the RapidSmith infrastructure/interface since it is XDL-based, but thus far we have made every effort to preserve existing code.
FYI: the ISE 14.x tools do in fact support XDL, but 14.7 is the last iteration of the ISE that Xilinx will ever produce. Back in August 2013, support for certain Zynq parts was added to RapidSmith - see the changelog for details.
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Good to hear... I just downloaded ISE 13.4, but I guess I'll just ignore it. Guess I should have just tried 14 to start with.
I was actually looking into XDL both for use with RapidSmith and using it directly. Could you shed some light on the Vivado equivalent? If possible, I'd like to look over some documents myself. Is it indeed the TCL interface whose commands are specified in UG835?
Thanks,
John
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I'll sum things up for you as best I can: Under the sponsorship of the NSF Center for High-Performance Reconfigurable Computing (CHREC), we have spent the last year investigating Vivado's TCL interface and have built a library of RapidSmith-like TCL functions.
We learned that, while it is possible to manipulate designs using Vivado's TCL interface in a way similar to RapidSmith, TCL as a language is unfit to provide a framework for building CAD tools. In other words, TCL is too slow and cumbersome to do anything other than making small, incremental changes to a design.
This being the case, we began investigating ways to extract information from Vivado that could then be read into RapidSmith. For instance, we are finishing up a TCL proc "write_XDLRC" which will output device information extracted from Vivado to the XDLRC format. We have other methods in the works that export and import design information, through the TCL interface.
UG835 is an excellent document to start with - it will outline all of the TCL procedures that Xilinx has augmented to Vivado's TCL interpreter. With these commands you can grab pointers to sites, tiles, just about anything and print out information about them.
Does this help?
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Hi, the write_XDLRC and other methods sounds really interesting. When will these be released in to the public domain?
I'm looking at device information extraction from Vivado myself and would be interested to compare notes. It seems there are subtle differences in wire naming and connectivity between ISE XDLRC and Vivado.
Best regards,
Tim
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The XDLRC creation for Vivado devices is available as part of the tincr library. Tincr also provides some added functionality for modifying designs in Vivado. However, we currently don't have any solution yet for importing placement and routing information from RapidSmith into Vivado.
Hi Everyone-
I've seen that Xilinx is getting rid of XDL as of ISE 14. Is this still true? I've also looked at the TCL interface to "replace" it, but is doesn't seem to provide similar functionality at all.
Is there a plan for support going forward? I'm currently designing for a Zynq, which appears to require ISE 14 for support.
~John
Hello John-
We are currently looking into a Vivado equivalent for XDL and are very optimistic. This may require some changes in the RapidSmith infrastructure/interface since it is XDL-based, but thus far we have made every effort to preserve existing code.
FYI: the ISE 14.x tools do in fact support XDL, but 14.7 is the last iteration of the ISE that Xilinx will ever produce. Back in August 2013, support for certain Zynq parts was added to RapidSmith - see the changelog for details.
Good to hear... I just downloaded ISE 13.4, but I guess I'll just ignore it. Guess I should have just tried 14 to start with.
I was actually looking into XDL both for use with RapidSmith and using it directly. Could you shed some light on the Vivado equivalent? If possible, I'd like to look over some documents myself. Is it indeed the TCL interface whose commands are specified in UG835?
Thanks,
John
I'll sum things up for you as best I can: Under the sponsorship of the NSF Center for High-Performance Reconfigurable Computing (CHREC), we have spent the last year investigating Vivado's TCL interface and have built a library of RapidSmith-like TCL functions.
We learned that, while it is possible to manipulate designs using Vivado's TCL interface in a way similar to RapidSmith, TCL as a language is unfit to provide a framework for building CAD tools. In other words, TCL is too slow and cumbersome to do anything other than making small, incremental changes to a design.
This being the case, we began investigating ways to extract information from Vivado that could then be read into RapidSmith. For instance, we are finishing up a TCL proc "write_XDLRC" which will output device information extracted from Vivado to the XDLRC format. We have other methods in the works that export and import design information, through the TCL interface.
UG835 is an excellent document to start with - it will outline all of the TCL procedures that Xilinx has augmented to Vivado's TCL interpreter. With these commands you can grab pointers to sites, tiles, just about anything and print out information about them.
Does this help?
Yes, that helps a good deal. I look forward to seeing methods for importing/exporting designs. Thanks for all your hard work!
~John
Hi, the write_XDLRC and other methods sounds really interesting. When will these be released in to the public domain?
I'm looking at device information extraction from Vivado myself and would be interested to compare notes. It seems there are subtle differences in wire naming and connectivity between ISE XDLRC and Vivado.
Best regards,
Tim
Hi,
any updates on that?
Cheers
The XDLRC creation for Vivado devices is available as part of the tincr library. Tincr also provides some added functionality for modifying designs in Vivado. However, we currently don't have any solution yet for importing placement and routing information from RapidSmith into Vivado.
http://sourceforge.net/p/tincr/wiki/intro/