Search Results for "altera"
Sort By:
Showing 23 open source projects for "altera"
View related business solutions-
Our Free Plans just got better! | Auth0You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
-
Enterprise-grade ITSM, for every businessFreshservice is an intuitive, AI-powered platform that helps IT, operations, and business teams deliver exceptional service without the usual complexity. Automate repetitive tasks, resolve issues faster, and provide seamless support across the organization. From managing incidents and assets to driving smarter decisions, Freshservice makes it easy to stay efficient and scale with confidence.
-
1
Open-Source, JavaScript based, 2d, space shooter game.
-
2
MSX Disk Interface Emulator
A Interface to adapt modern SD Card to the old MSX computers
...For the MSX it will be as if there is a magnetic disk drive with a real magnetic disk but for real it will be accessing a .dsk file inside a sdcard. Development tools used are: - Kicad version 2013-07-07 - Microchip XC8 v1.21 (free mode) - Micrchip MPLAB X IDE v1.90 - Altera´s Quartus Web Edition 11.0 UPDATE 2014-11-05 =============== Now it is working and the SVN repositories has it all: Schematics, PCB layout, firmware for the CPLD and the firmware for the MCU. But you have to download by your own the firmware for the 49F010 on the internet. -
3
IwaRifas
Gerenciador de Rifas
- Gerencia rifas (adiciona, altera, remove); - Realiza o sorteio de rifas; - Gera historico de rifas concluidas; - Visual moderno; - Não precisa instalar; - Gratuito; -
4
bel_fft
FFT co-processor in Verilog based on the KISS FFT
...It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1. -
Find Hidden Risks in Windows Task SchedulerWindows Task Scheduler might be hiding critical failures. Download the free JAMS diagnostic tool to uncover problems before they impact production—get a color-coded risk report with clear remediation steps in minutes.
-
5
LArIAT FPGA Trigger
Firmware (VHDL source) for the CAEN V1495 board
This is the source for a customized firmware that runs on the Altera Cyclone I FPGA mounted on a CAEN V1495 VME board. It was written in support of the LArIAT - Liquid Argon in The trigger module takes 16 ECL/LVDS inputs, in our case from various beamline counters. It has a custom firmware which looks for user programmable patterns corresponding to “good” events. A good pattern results in a fast trigger output and starts a clock. -
6
RPTParse
Quartus project compilation reports parsing tool
Altera Quartus creates .rpt files during synthesis, place&route and bitstream generation stages of FPGA project compilation. Verification engineer checks these reports, finds warning messages and put them into own report. But big projects can contain a lot of warnings, and manual warning search is very boring and long process. That's why this parsing tool was created. -
7
Darkest Dungeon Trainer
Trainer para el juego Darkest Dungeon
Este trainner lo hice para bajar un poco la dificultad del juego, no altera la dificultad de los combates o la cantidad de tesoros que puedes encontrar una vez emprendido el viaje a una mazmorra. Lo que si hace es reducir los costos de todos los items (excepto los abalorios) como así también reduce los costos de las actualizaciones del armamento y el uso de los diferentes establecimientos que alberga el pueblo (Abadía, Taberna, Diligencia,etc.) -
8
cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
...The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers. -
9
ADopenPOWERLINK
openPOWERLINK with Analog Devices ADSP-CM408F Mixed Signal Controller
ADopenPOWERLINK is an open source Ethernet Powerlink Controlled Node (Slave) solution using the Analog Devices ADSP-CM408F mixed signal processor (http://www.analog.com), along with Altera FPGA as network communication processor. The solution is based on openPOWERLINK provided by SYSTEC electronic (http://www.systec-electronic.com), B&R (http://www.br-automation.com) and Kalycito (http://www.kalycito.com). This release contains the necessary and required packages and documentation to setup the power-link controlled node using Analog Devices ADZS-CM408 EZLITE development board (http://www.analog.com/en/processors-dsp/cm4xx/adsp-cm408f/products/cm40x-ez/eb.html) as application processor, and a Terasic DE2-115 Altera FPGA development board as a communication processor. -
MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
-
10
Low latency trading platform
The documents for my achievements of the low latency technology
...Stock exchange client Java RCP/Apache_Active_MQ/Plugins/QuickFIX/SLF4J/XstreamApache_LOG4J To see how the software trading client work. Through this way, I made deep understanding to how we can reduce the trading latency based on FPGA technology. Altera OpenCL (on going, just for academic research) OpenCL/Perl/Bat/C++/DDR2/Ethernet/UcOS/Nios II/ Make modification of the Alter OpenCL SDK except the OpecCL C to HDL synthesis to use Ethernet to communicate between Host and Kernel. Rewrite the perl command lines to meet special aims. Monte Carlo Black Schole simulation and QuantLib based on OpenCL standard. -
11
Altera Terra is a Civ-like turn-based strategy game, mainly designed for easy extensibility. Still in the first stages of development, there already is a version you can take a peek at.
-
12
MPuCOS
multiple processors uC/OS
we modify MicroC/OS-II to Multiple processors system -
13
relogio-digital
Relogio digital em VHDL
Este é a descrição de um relogio digital em VHDL para ser implementado em um placa DE2 da terasic e simulado usando o ambiente de desenvolvimento da altera Quartus II. -
14
The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard.
-
15
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
-
16
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
-
17
-
18
Script PHP para monitoramento de conexão com a internet, dispara um número X de pings contra N endereços IPs e/ou nomes, se a perda de pacotes for maior que um valor Y pode opcionalmente executar um script externo e no retorno do link executar outro.
-
19
A version of the classic game Space Invaders developed in MIPS Assembly and implemented on the Altera DE2 board.
-
20
M.J.K. é um programa que facilita o uso da linguagem japonesa em teclados ocidentais. Ele altera o modo como o sistema entende o que é digitado no teclado.
-
21
This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.
-
22
-
23
An operating system for an educational robot based on a Nios II board from Altera. Implemented in Nios II assember and C/C++.
- Previous
- You're on page 1
- Next
