MRISC32 is a 32-bit RISC/vector ISA (instruction set architecture).

Some of the goals of the ISA are:

• Create a clean, modern ISA that is equally attractive to software, hardware and compiler developers.
• Enable high performance implementations, with good scalar and vector integer and floating-point support.
• Enable resource and energy efficient implementations of both in-order and out-of-order machines.

MRISC32 is inspired by architectures such as Cray-1, MIPS and RISC-V, and tries to combine the good parts without repeating some unfortunate design decisions (e.g. delay slots and lack of useful addressing modes).

• Unified scalar/vector/integer/floating-point ISA
• Load/store architecture, suitable for pipelining
• Two register files:
  • 32 scalar registers
  • 32 vector registers
• Fixed size 32 bits wide instruction words:
  • Easily decoded instructions (no microcode is needed)
  • Efficient use of the available instruction space, with room for future extensions
• Powerful addressing modes:
  • Wide range PC-relative and absolute addressing for load/store and branches
  • Scaled indexed load/store addressing (register + scale * register)
  • Gather/scatter and stride-based vector load/store
• No condition code register:
  • Compare instructions generate bit masks (all 1:s or all 0:s)
  • Branch instructions can act on bit masks and signed scalars
  • Bit masks can further be used for masking, arithmetic and conditional moves
• Dynamic and future proof vector model:
  • Most instructions can operate on both scalar and vector registers
  • Vector operation lengths are variable on a per-instruction basis
  • Each vector register can hold at least 16 32-bit elements
  • Implementers may choose to provide significantly larger registers
  • Software is binary compatible between different vector register sizes
• 8-bit and 16-bit data types can be packed in 32-bit chunks:
  • Most instructions offer increased parallelism for packed data types:
    • 2x parallelism for 16-bit data types
    • 4x parallelism for 8-bit data types
  • Supports packed integer, fixed point and floating-point types
• Supports IEEE 754 floating-point
• Supports fixed point operations
• Some parts of the ISA are optional:
  • It is possible to create a very lightweight MRISC32 core
  • Things like floating-point and vector operations are optional

MRISC32-A1

The first implementation of the MRISC32 ISA is MRISC32-A1, which is a soft processor implemented in portable VHDL, suitable for running on an FPGA. It is a 9-stage pipelined, single issue, in order architecture (i.e. it can execute at most one operation per clock cycle), and it implements the entire MRISC32 ISA.

The CPU easily fits in a low- to mid-range FPGA, such as the MAX® 10, in which it consumes about 12K logic elements and runs at 70-100 MHz at the time of writing. It can also be configured to use much less resources (down to 30% of the full design) by disabling certain features, such as floating-point support.

MC1

The MC1 (short for MRISC32 Computer 1), is a small open source computer for FPGA:s, hosting an MRISC32-A1 CPU core. One of its main features is its flexible video subsystem that makes it suitable for graphical applications.

The MRSIC32 ISA and the MRISC32-A1 implementation are still in development. Several aspects such as exception handling and memory management are still undefined.