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A-layoutArea: Memory layout of typesArea: Memory layout of typesC-cleanupCategory: PRs that clean code up or issues documenting cleanup.Category: PRs that clean code up or issues documenting cleanup.T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.
Description
See here for an elaboration of the redundancy. Below follows the original issue that lead to us looking into this.
I just discovered something rather strange in our enum layouts: std::sync::atomic::Ordering has
abi: Scalar(
Initialized {
value: Int(
I8,
false,
),
valid_range: 0..=4,
},
),
but its variants look like
Layout {
size: Size(1 bytes),
align: AbiAndPrefAlign {
abi: Align(1 bytes),
pref: Align(8 bytes),
},
abi: Aggregate {
sized: true,
},
fields: Arbitrary {
offsets: [],
memory_index: [],
},
largest_niche: None,
variants: Single {
index: 0,
},
max_repr_align: None,
unadjusted_abi_align: Align(1 bytes),
},
Note the abi: Aggregate!
I am surprised that this has not already lead to ICEs in CTFE/Miri -- via downcasting, one can end up with Immediate::Scalar that have Aggregate ABI, which can quickly panic.
This is a bug, right? If the enum has Scalar layout, then all its variants should also have that layout? For ScalarPair enums, this seems to already be the case.
Cc @oli-obk @eddyb
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A-layoutArea: Memory layout of typesArea: Memory layout of typesC-cleanupCategory: PRs that clean code up or issues documenting cleanup.Category: PRs that clean code up or issues documenting cleanup.T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.