Bottom 128 bits of icache data_sram unused

[povik]

Hello CVA6 team,

we've added CVA6 to OpenROAD-flow-scripts and we're seeing puzzling features in the netlist around memory macros.

We've pulled 3a389af and should be using this configuration: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/f53fbce71af0e7965b3fa76396ff6d3e8121b6bb/flow/designs/src/cva6/core/include/cv32a65x_config_pkg.sv. We've patched in custom memory macros.

After synthesis, on the following memory instances, we're seeing the bottom 128 bits of data output unused, and the corresponding data inputs tied off to zero.

gen_cache_hpd.i_cache_subsystem.i_cva6_icache.gen_sram[0].data_sram.gen_techno_cut.genblk1.i_tc_sram_wrapper
gen_cache_hpd.i_cache_subsystem.i_cva6_icache.gen_sram[1].data_sram.gen_techno_cut.genblk1.i_tc_sram_wrapper

Is this expected? I believe the unused slice corresponds to USER_WIDTH. What's the purpose of the "user" data? I couldn't find this documented anywhere though it seems related to some configuration options on the design.

Thanks much!

cc @maliberty @jeffng-or

[JeanRochCoulon]

@Gchauvon

[JeanRochCoulon]

@yanicasa

[Gchauvon]

Like many "user" signal in bus interfarce, it is for user-specific usage. Common usage, are ECC, debug, tracing, security, safety features...

I believe user signal of the cache should be connected to user signal of the AXI BUS. So a memory access should update data and user in the cache. In cv32a65x configuration, those signals are enabled and tied to 0.