diff --git a/clash-prelude/src/Clash/Prelude/Testbench.hs b/clash-prelude/src/Clash/Prelude/Testbench.hs
index ad9e7f16d0..7d88ca3a58 100644
--- a/clash-prelude/src/Clash/Prelude/Testbench.hs
+++ b/clash-prelude/src/Clash/Prelude/Testbench.hs
@@ -18,6 +18,7 @@ Maintainer :  Christiaan Baaij <christiaan.baaij@gmail.com>
 module Clash.Prelude.Testbench
   ( -- * Testbench functions for circuits
     assert
+  , assertBitVector
   , ignoreFor
   , outputVerifier'
   , outputVerifierBitVector'
@@ -69,6 +70,22 @@ assert msg actual expected ret =
   hideReset (hideClock E.assert) msg actual expected ret
 {-# INLINE assert #-}
 
+-- | The same as 'assert', but can handle don't care bits in it's expected value.
+assertBitVector
+  :: (KnownNat n, HiddenClock dom , HiddenReset dom )
+  => String
+  -- ^ Additional message
+  -> Signal dom (BitVector n)
+  -- ^ Checked value
+  -> Signal dom (BitVector n)
+  -- ^ Expected value
+  -> Signal dom b
+  -- ^ Return value
+  -> Signal dom b
+assertBitVector msg actual expected ret =
+  hideReset (hideClock E.assertBitVector) msg actual expected ret
+{-# INLINE assertBitVector #-}
+
 -- |
 --
 -- Example: