Bad time complexity for VHDL, not Verilog

[DigitalBrains1]

The file below exposes bad time complexity in the normalization phase of generating VHDL, whereas Verilog is near-instant. With a vector of length 25 as below, the numbers are:
VDHL: Clash: Normalisation took 3.052s
Verilog: Clash: Normalisation took 0.027s
More lengths:

• 30:
  VHDL: Clash: Normalisation took 6.543s
  Verilog: Clash: Normalisation took 0.031s
• 35:
  VHDL: Clash: Normalisation took 12.721s
  Verilog: Clash: Normalisation took 0.034s
• 40:
  VHDL: Clash: Normalisation took 22.088s
  Verilog: Clash: Normalisation took 0.037s

This is with CλaSH master. Using 1.2.4 seems to exhibit the same problem but less pronounced.

module LongVecCompl where

import Clash.Prelude

topEntity
  :: SystemClockResetEnable
  => Signal System (Bool, Unsigned 8)
{-# NOINLINE topEntity #-}
topEntity = f (packetVecToStreamVec $(listToVecTH [1 :: Unsigned 8 .. 25]))

f :: forall n
   . (SystemClockResetEnable, KnownNat n, 1 <= n)
  => Vec n (Bool, Unsigned 8)
  -> Signal System (Bool, Unsigned 8)
f is = (is!!) <$> sel
 where
  sel :: Signal System (Index n)
  sel = register 0 $ satSucc SatWrap <$> sel

packetVecToStreamVec pkt =    map (\e -> (True, e)) (init pkt)
                           :< (False, last pkt)

[DigitalBrains1]

The code can be further reduced while keeping the problematic behaviour:

module LongVecCompl where

import Clash.Prelude

topEntity
  :: SystemClockResetEnable
  => Signal System (Unsigned 8)
  -> Signal System (Bool, Unsigned 8)
{-# NOINLINE topEntity #-}
topEntity = fmap (packetVecToStreamVec (replicate d25 0) !!)

packetVecToStreamVec pkt =    map (\e -> (True, e)) (init pkt)
                           :< (False, last pkt)

[leonschoorl]

For some reason when compiling to Verilog the map isn't evaluated.
When compiling to VHDL or SystemVerilog it is evaluated.