Memory inference fails for read-after-write

[eddiehung]

Steps to reproduce the issue

... but works for read-before-write.

./yosys -p "synth -run coarse; memory_bram -rules +/xilinx/brams.txt; stat" ram1.v -f "verilog -DBUG"

module reg_file(input wire clk,
                input wire wr_en,
                input wire [9:0] w_addr,
                input wire [9:0] r_addr,
                input wire [17:0] w_data,
                output reg [17:0] r_data);

  reg [17:0] ram [0:1023];

  always @(posedge clk)
  begin
    r_data <= ram[w_addr];
    if (wr_en) begin
      ram[w_addr] <= w_data;
`ifdef BUG
      r_data <= w_data;
`endif
    end
  end

endmodule

Expected behavior

Successful inference (as is the case when -DBUG omitted):

   Number of cells:                 16
     $__XILINX_RAMB18_SDP            2
     $dff                            2
     $eq                             4
     $mux                            7
     $pmux                           1

Actual behavior

Failed inference:

<<SNIP>>
      Read port #0 is in clock domain \clk.
        Mapped to bram port A1.1.
      Read port #1 is in clock domain !~async~.
        Bram port A1.2 has incompatible clock type.
        Failed to map read port #1.
<<SNIP>>
No acceptable bram resources found.
<<SNIP>>
   Number of cells:                  4
     $dff                            1
     $mem                            1
     $mux                            2

[eddiehung]

Testcase derived from dual port RAM template: https://github.com/alexforencich/verilog-cam/blob/master/rtl/ram_dp.v

[daveshah1]

Yosys currently expects a register on the address port to infer read-after-write memory:

module reg_file(input wire clk,
                input wire wr_en,
                input wire [9:0] w_addr,
                input wire [9:0] r_addr,
                input wire [17:0] w_data,
                output [17:0] r_data);

  reg [17:0] ram [0:1023];
  reg [9:0] r_addr_reg;
  always @(posedge clk)
  begin
    r_addr_reg <= r_addr;
    if (wr_en) begin
      ram[w_addr] <= w_data;
    end
  end

  assign r_data = ram[r_addr_reg];
endmodule

For comparison, your example produces:

memory_dff would need to be modified to recognise this mux and make a transparent port. But I think there could be a semantics issue here as we move towards supporting TDP RAM - unlike the current semantics where transparent read ports are considered read-after-write for all write ports, this kind of Verilog specifies read-after-write for same-port accesses only. Not sure whether cross-port accesses might be into UB anyway though.