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{{short description|Shading language}}
{{Use American English|date=February 2023}}
{{Use mdy dates|date=February 2023}}
[[File:HLSL-Examples-1.PNG|thumb|300px|A scene containing several different 2D HLSL shaders. [[Distortion]] of the statue is achieved purely physically, while the texture of the rectangular frame beside it is based on color intensity. The square in the background has been [[linear transformation|transformed]] and [[rotation|rotated]]. The partial [[Transparency (graphic)|transparency]] and [[reflection (computer graphics)|reflection]] of the water in the foreground are added by a shader applied finally to the entire scene.]]
The '''High-Level Shader Language'''<ref>{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-writing-shaders-9 |title=Writing HLSL Shaders in Direct3D 9 |website=[[Microsoft Docs]] |access-date=
HLSL is analogous to the [[GLSL]] shading language used with the [[OpenGL]] standard. It is very similar to the [[Nvidia Cg]] shading language, as it was developed alongside it. Early versions of the two languages were considered identical, only marketed differently.<ref>{{cite web|url=http://www.fusionindustries.com/default.asp?page=cg-hlsl-faq|archive-url=https://web.archive.org/web/20120824051248/http://www.fusionindustries.com/default.asp?page=cg-hlsl-faq|url-status=dead|archive-date=
HLSL programs come in six forms: [[pixel shader]]s (fragment in GLSL), [[vertex shader]]s, [[geometry shader]]s, [[compute shader]]s, [[tessellation shader]]s (Hull and Domain shaders), and [[ray tracing shader]]s (Ray Generation Shaders, Intersection Shaders, Any Hit/Closest Hit/Miss Shaders). A vertex shader is executed for each vertex that is submitted by the application, and is primarily responsible for transforming the vertex from object space to view space, generating texture coordinates, and calculating lighting coefficients such as the vertex's normal, tangent, and bitangent vectors. When a group of vertices (normally 3, to form a triangle) come through the vertex shader, their output position is interpolated to form pixels within its area; this process is known as [[rasterization]].
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Optionally, an application using a Direct3D 10/11/12 interface and Direct3D 10/11/12 hardware may also specify a geometry shader. This shader takes as its input some vertices of a primitive (triangle/line/point) and uses this data to generate/degenerate (or [[Tessellation (computer graphics)|tessellate]]) additional primitives or to change the type of primitives, which are each then sent to the rasterizer.
D3D11.3 and D3D12 introduced Shader Model 5.1<ref>{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/shader-model-5-1-objects |title=Shader Model 5.1 Objects |website=[[Microsoft Docs]] |access-date=
==Shader model comparison==
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{| class="wikitable"
! Pixel shader version
!1.0
!1.1
!1.2
1.3<ref name="PS1-3">{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx9-graphics-reference-asm-ps-differences |title=Pixel Shader Differences |work=[[Microsoft Docs]] |date=August 19, 2020 |access-date=February 22, 2021}}</ref>
!1.4<ref name="PS1-3"/> !!2.0<ref name="PS1-3"/><ref name=SM2>{{cite web |url=https://docs.microsoft.com/en-us/previous-versions/ms810449(v=msdn.10) |title=Introduction to the DirectX 9 High-Level Shader Language |last1=Peeper |first1=Craig |last2=Mitchell |first2=Jason L. |date=July 2003 |work=[[Microsoft Docs]] |access-date=February 22, 2021}}</ref>!!2.0a<ref name="PS1-3"/><ref name=SM2/><ref name="VS2.0a">{{cite web |url=https://www.anandtech.com/show/1034/4 |title=NVIDIA Introduces GeForce FX (NV30) |last=Shimpi |first=Anand Lal |author-link=Anand Lal Shimpi |work=[[AnandTech]] |access-date=February 22, 2021}}</ref>!!2.0b<ref name="PS1-3"/><ref name=SM2/><ref name="PS2.0b">{{cite web |url=https://www.anandtech.com/show/1314/4 |title=ATI Radeon X800 Pro and XT Platinum Edition: R420 Arrives |first=Derek |last=Wilson |work=[[AnandTech]] |access-date=February 22, 2021}}</ref>!!3.0<ref name="PS1-3"/><ref name=SM3>Shader Model 3.0, Ashu Rege, NVIDIA Developer Technology Group, 2004.</ref>!!4.0<ref name=D3D10>The Direct3D 10 System, David Blythe, Microsoft Corporation, 2006.</ref>4.1<ref name="SM4.1">{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-sm4-registers-ps-4-1 |title=Registers - ps_4_1 |website=[[Microsoft Docs]] |date=August 23, 2019 |access-date=February 22, 2021}}</ref>
5.0<ref name="SM5">{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/registers---ps-5-0 |title=Registers - ps_5_0 |website=[[Microsoft Docs]] |date=August 23, 2019 |access-date=February 22, 2021}}</ref>
|-
!Dependent texture limit
|4
|4
|4||6 || 8 ||Unlimited ||8 ||Unlimited ||Unlimited
|-
!Texture instruction limit
|4
|4
|4||6 * 2 ||32 ||Unlimited ||Unlimited ||Unlimited ||Unlimited
|-
!Arithmetic instruction limit
|8
|8
|8
|8 * 2
|64
|Unlimited
|Unlimited
|Unlimited
|Unlimited
|-
!Position register
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Instruction slots
|8
|8 + 4
|8 + 4||(8 + 6) * 2 ||64 + 32 ||512 ||512 ||≥ 512 ||≥ 65536
|-
!Executed instructions
|8
|8 + 4
|8 + 4||(8 + 6) * 2 ||64 + 32 ||512 ||512 ||65536 ||Unlimited
|-
!Texture indirections
|4
|4
|4||4 ||4 ||Unlimited ||4 ||Unlimited ||Unlimited
|-
!Interpolated registers
|2 + 4
|2 + 4
|2 + 4||2 + 6 ||2 + 8 ||2 + 8 ||2 + 8 ||10 ||32
|-
!Instruction predication
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{Yes}} || {{No}} || {{Yes}} || {{No}}
|-
!Index input registers
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Temp registers
|2
|2 + 4
|3 + 4||6 ||12 to 32 ||22 ||32 ||32 ||4096
|-
!Constant registers
|8
|8
|8||8 ||32 ||32 ||32 ||224 ||16×4096
|-
!Arbitrary [[Swizzling (computer graphics)|swizzling]]
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Gradient instructions
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Loop count register
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Face register (2-sided lighting)
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}}
|-
!Dynamic flow control
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}} (24) || {{Yes}} (64)
|-
!Bitwise Operators
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}}
|-
!Native Integers
|{{No}}
|{{No}}
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}}
|}
*'''PS 1.0''' — Unreleased [[3dfx]] Rampage, DirectX 8
*'''PS 1.1''' — [[GeForce 3]], DirectX 8
*'''PS 1.2''' — [[3Dlabs]] Wildcat VP, DirectX 8.
*'''PS 1.3''' — [[GeForce 4 Ti]], DirectX 8.
*'''PS 1.4''' — [[ATI Radeon R200 series|Radeon
*'''Shader Model 2.0''' — [[ATi Radeon R300 Series|Radeon
*'''Shader Model 2.0a''' — [[GeForce FX|GeForce FX/PCX]]-optimized model, DirectX 9.0a
*'''Shader Model 2.0b''' — [[Radeon R420|Radeon
*'''Shader Model 3.0''' — [[Radeon X1000]] and [[GeForce 6]], DirectX 9.0c
*'''Shader Model 4.0''' — [[Radeon HD 2000]] and [[GeForce 8]], DirectX 10
*'''Shader Model 4.1''' — [[Radeon HD 3000]] and [[GeForce 200]], DirectX 10.1
*'''Shader Model 5.0''' — [[Radeon HD 5000 series|Radeon HD 5000]] and [[GeForce 400]], DirectX 11
*'''Shader Model 5.1''' — [[Graphics Core Next#first|GCN 1+]], Fermi+, DirectX 12 (11_0+) with WDDM 2.0
*'''Shader Model 6.0''' — GCN 1+, Kepler+, DirectX 12 (11_0+) with WDDM 2.1
*'''Shader Model 6.1''' — GCN 1+, Kepler+, DirectX 12 (11_0+) with WDDM 2.3
*'''Shader Model 6.2''' — GCN 1+, Kepler+, DirectX 12 (11_0+) with WDDM 2.4
*'''Shader Model 6.3''' — GCN 1+, Kepler+, DirectX 12 (11_0+) with WDDM 2.5
*'''Shader Model 6.4''' — GCN 1+, Kepler+, Skylake+, DirectX 12 (11_0+) with WDDM 2.6
*'''Shader Model 6.5''' — GCN 1+, Kepler+, Skylake+, DirectX 12 (11_0+) with WDDM 2.7
*'''Shader Model 6.6''' — GCN 4+, Maxwell+, DirectX 12 (11_0+) with WDDM 3.0
*'''Shader Model 6.7''' — GCN 4+, Maxwell+, DirectX 12 (12_0+) with WDDM 3.1
*'''Shader Model 6.8''' — RDNA 1+, Maxwell 2+, DirectX 12 (
"32 + 64" for ''Executed Instructions'' means "32 texture instructions and 64 arithmetic instructions."
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{| class="wikitable"
! Vertex shader version
!1.0
!1.1<ref name="VS1-3">{{cite web |url=https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx9-graphics-reference-asm-vs-differences |title=Vertex Shader Differences |work=[[Microsoft Docs]] |date=August 19, 2020 |access-date=February 22, 2021}}</ref>
!2.0<ref name="SM2" /><ref name="VS1-3" /><ref name="VS2.0a" /> !!2.0a<ref name="SM2" /><ref name="VS1-3" /><ref name="VS2.0a" /> !!3.0<ref name="SM3" /><ref name="VS1-3" /> !!4.0<ref name="D3D10" /> <br>4.1<ref name="SM4.1" /> <br>5.0<ref name="SM5" />
|-
!# of instruction slots
|128
|128 ||256 ||256 ||≥ 512 ||≥ 65536
|-
!Max # of instructions executed
|128
|128 ||1024 ||65536 ||65536 ||Unlimited
|-
![[Branch predication|Instruction predication]]
|{{No}}|| {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}}
|-
!Temp registers
|12
|12 ||12 ||16 ||32 ||4096
|-
!# constant registers
|≥ 96
|≥ 96 ||≥ 256 ||256 ||≥ 256 ||16×4096
|-
!Address register
|{{No}}
|{{Yes}}
|{{Yes}}
|{{Yes}}
|{{Yes}}
|{{Yes}}
|-
!Static flow control
|{{No}}|| {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}}
|-
!Dynamic flow control
|{{No}}|| {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}}
|-
!Dynamic flow control depth
|{{N/A}}|| {{N/A}} || {{N/A}} || 24 || 24 || 64
|-
!Vertex texture fetch
|{{No}}|| {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}}
|-
!# of texture samplers
| {{N/A}}|| {{N/A}} || {{N/A}} || {{N/A}} || 4 ||128
|-
![[Geometry instancing]] support
|{{No}}|| {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}}
|-
!Bitwise operators
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}}
|-
!Native integers
|{{No}}|| {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}}
|}
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* [https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-pguide Programming guide for HLSL] at [[Microsoft Docs]]
* [https://web.archive.org/web/20100215205220/http://ati.amd.com/developer/ShaderX2_IntroductionToHLSL.pdf Introduction to the DirectX 9 High Level Shading Language], (ATI) AMD developer central
* [http://www.riemers.net/Tutorials/DirectX/Csharp3/index.php Riemer's HLSL Introduction & Tutorial (includes sample code)] {{Webarchive|url=https://web.archive.org/web/20081119034954/http://www.riemers.net/Tutorials/DirectX/Csharp3/index.php |date=November 19, 2008 }}
* [http://www.neatware.com/lbstudio/web/hlsl.html HLSL Introduction]
* [https://github.com/microsoft/DirectXShaderCompiler/blob/master/docs/DXIL.rst DirectX Intermediate Language] (DXIL) specification
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