US Patent 8178402 - Self-assembly of CNT transistors

http://www.freepatentsonline.com/8178402.html

This patent from Intel teaches how to align and immobilize carbon nanotubes as the channels of field effect transistors using molecular functionalization of the ends of the nanotubes. Claim 1 reads:

1. A method comprising:

selectively severing a portion of a carbon nanotube;

functionalizing an exposed portion of the carbon nanotube, wherein opposed ends of said carbon nanotubes are functionalized differently; and

placing the carbon nanotube on a transistor substrate, wherein a source region of the transistor substrate attracts one end of said carbon nanotube and a drain region attracts the opposite end of said carbon nanotube.

US Patent 8174084 - CNT stress sensor

http://www.freepatentsonline.com/8174084.html

This patent from Intel teaches how carbon nanotubes can be used to understand the effects of stress on integrated circuits. Claim 1 reads:

1. A stress sensor comprising:

a die having an opening formed in a semiconductor substrate of the die said semiconductor substrate having a top surface;

a plurality of carbon nanotubes having first ends opposite second ends disposed in the opening wherein said plurality of carbon nanotubes are embedded within said semiconductor substrate wherein said plurality of carbon nanotubes are aligned in a direction parallel to said top surface of said semiconductor substrate; and

first and second contacts electrically connectable with the first and second ends of the plurality of carbon nanotubes, respectively.

US Patent 8173259 - Nanoparticle layers with CTE compensation

http://www.freepatentsonline.com/8173259.html

Mismatch of coefficients of thermal expansion (CTE) is a significant problem when attempting to interface silicon and polymer or organic substrates. This patent from Intel teaches how providing a gradient of nanoparticles can provide an interface to avoid problems from CTE mismatch. Claim 1 reads:

1. A structure comprising:

a first layer of at least one of a plurality of functionalized nanoparticles and polymer material disposed on a substrate, wherein the first layer comprises a physical property; and

a second layer of at least one of a plurality of functionalized nanoparticles and polymer material disposed on the first layer,

wherein the first layer comprises the physical property, and wherein at least one of the first layer and the second layer of functionalized nanoparticles comprises metallic functionalized nanoparticles; and

a property gradient extending from the first layer to the second layer.

US Patent 8134684 - Immersion lithography using hafnium-based nanoparticles

http://www.freepatentsonline.com/8134684.html


This patent is based on a collaboration between Sematech and Intel and teaches how hafnium dioxide nanoparticles can be used to create fluids to improve the resolution of immersion lithography tools. Claim 1 reads:

1. A composition of matter comprising:

a medium; and

Hafnium dioxide nanoparticles incorporated in the medium, the Hafnium dioxide nanoparticles having a diameter less than or equal to about 15 nanometers;

wherein said composition of matter is an immersion fluid or a resist.

US Patent 8133585 - Reducing contact resistance of CNT material

http://www.freepatentsonline.com/8133585.html

Intel has been working on developing new forms of heat sink materials for microcircuit packaging using carbon nanotubes. This most recent patent teaches a thermally conductive nanotube material with improved adhesion and reduced contact resistance. Claim 1 reads:

1. A thermally and electrically conductive structure comprising:

a carbon nanotube having an outer surface;

a carbon coating covering at least a portion of the outer surface of the carbon nanotube;

a transition layer exterior to the carbon coating; and

a metal layer exterior to the transition layer.

US Patent 8125075 - CNT micro-chimney for die level cooling

http://www.freepatentsonline.com/8125075.html

This patent from Intel is the latest in a series of patents teaching ways carbon nanotubes can be used in semiconductor packaging for cooling. Claim 1 reads:

1. A method of packaging a semiconductor comprising:

forming a cavity within a die near a region heated by an integrated circuit;

growing, within the cavity, a plurality of carbon nanotubes coupled to the die;

adding a saturated mixture of working fluid to the cavity; and

sealing the saturated mixture within the cavity.

US Patent 8100314 - CNT solder

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Electromigration is the transport of material due to ion drift and can be damaging to solder at high current densities. This patent from Intel teaches using carbon nanotubes to form a solder in which electromigration problems are reduced. Claim 1 reads:


1. A bump comprising:

a solder paste comprising solder powder and a paste ingredient mixed with the solder powder; and

carbon nanotubes (CNTs) dispersed within the solder paste with a pre-defined volume fraction, wherein the pre-defined volume fraction ranges from approximately 30% to 40%, to provide high electrical conductivity;

wherein the solder paste is attached to at least one of a die or a package substrate.

US Patent 8004076 - CNT interconnect for microelectronic package

http://www.freepatentsonline.com/8004076.html

This patent from Intel teaches a way to deal with the problem of stress caused by thermal expansion in semiconductor packaging by using carbon nanotube interconnects. Claim 1 reads:

1. A method of forming a microelectronic package, comprising:

providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer;

coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate;

removing the silicon substrate from the packaging substrate; and

disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.

US Patent 8004043 - CNTFET logic

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This patent from Intel appears to include some basic claims covering a carbon nanotube based logic system useful as building blocks for nanoscale reconstruction of inverter, NAND, and NOR logic gates. Claim 1 reads:

1. An integrated circuit, comprising:

first and second CNTFETs coupled in series between high and low supply references, the first CNTFET having a top gate to provide a logical input to receive High and Low logical values, the second CNTFET having a top gate coupled to a bias supply so that the second CNTFET provides an active load for the first CNTFET to provide suitable logical High and Low output levels.

US Patent 7985627 - CNT thermal interface

http://www.freepatentsonline.com/7985627.html

This patent is the latest in a series of patents from Intel teaching ways to use carbon nanotubes to achieve high thermal conduction interfaces to cool integrated circuit packaging. Claim 1 reads:

1. A method, comprising:

oxidizing at least one nanotube rope in acid to cut it into short nanotubes with open ends having carboxyl linkages attached thereto;

forming organic moieties at the open ends; tethering an end of the short nanotubes to a surface of a first object; and

placing a surface of a second object in contact with another end of the short nanotubes to form a thermal path between the surface of the first object and the surface of the second object.

US Patent 7983020 - CNT coated capacitor electrodes

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This patent from Intel teaches how carbon nanotubes can be used to improve the decoupling capacitance used in delivering power to CPUs. Claim 1 reads:

1. A device comprising:

a capacitor comprising a first and second electrode and a capacitor dielectric between the first and second electrodes;

wherein at least one of the first and second electrodes comprise a plurality of carbon nanotubes coupled thereto; and

wherein the plurality of the carbon nanotubes are in direct physical contact with the capacitor dielectric.

US Patent 7982204 - Unstable nanowire nitrides to form semiconductor structures

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This patent from Intel teaches how metal nanowire nitrides can be used to improve layer adhesion during semiconductor fabrication processes. Claim 5 reads:

5. A semiconductor structure comprising:

a substrate;

a metal nanowire nitride layer over said substrate; and

a region of substantially nitride free metal formed in said layer.

US Patent 7964447 - CNT thermal interface

http://www.freepatentsonline.com/7964447.html

This patent from Intel teaches the fabrication of a thermal interconnect between IC packages and heat spreaders using carbon nanotube arrays. Claim 1 reads:

1. A process comprising:

growing a first carbon nanotube (CNT) array on a first substrate in a first pattern;

growing a second CNT array on a second substrate in a second pattern that is geometrically complementary to the first pattern; and

assembling the first CNT array and the second CNT array such that the first substrate and the second substrate are joined at the first CNT array and the second CNT array.

US Patent 7964174 - Multi-diameter nanotube

http://www.freepatentsonline.com/7964174.html

Carbon nanotubes are usually classified in terms of single walled, double walled, or multiwalled types wherein each nanotube type typically has uniform diameter. This patent from Intel teaches a method of manufacturing an individual nanotube which mixes different diameters and which may play a role in developing nanotube heterojunction electronics. Claim 1 reads:

1. A method, comprising:

forming a first portion of a nanotube with a first diameter;

after forming the first portion, attaching the first portion of a nanotube to a particle; and

after attaching, forming a second portion of the nanotube with a second diameter on the particle coupled to the first portion of the nanotube.

US Patent 7952212 - Nanoparticle filler for IC packaging

http://www.freepatentsonline.com/7952212.html

IC packaging can suffer from delamination problems due to the high heat flux from microprocessors. This patent from Intel teaches concentrating nanoparticles in regions susceptible to delamination in order to provide a self-healing effect. Claim 1 reads:

1. An apparatus comprising:

a package including an integrated circuit, the package further including one or more regions of adjoining materials of different composition wherein one of the materials includes a polymeric material that includes a polymer matrix having at least one high energy region; and

a mobile nanoparticle filler dispersed substantially throughout the polymer matrix with an increased concentration in the high energy region.

US Patent 7886813 - Thermal interface with CNTs and particles

http://www.freepatentsonline.com/7886813.html

Intel continues to focus their carbon nanotube patents on new type of thermal cooling materials. This latest patent combines carbon nanotubes with metallic particles to create a composite material used to dissipate heat in high performance ICs. Claim 1 reads:

1. A thermal conducting material comprising:

a matrix material;

a distribution of separate particles within the matrix material, at least one particle including:

a heat conducting particle; and

a carbon nanotube structure attached at only one end to a surface of the heat conducting particle, and configured to remain attached at the same attachment location on the heat conducting particle during spreading of the thermal conducting material.

US Patent 7851790 - Isolated germanium nanowire on silicon fin

http://www.freepatentsonline.com/7851790.html

Germanium was the first material used for transistors but was quickly replaced with silicon which was found to produce better thermal stability and provide manufacturing advantages. As higher speed electronics are desired germanium may again become an option due to its higher mobility. This patent from Intel teaches a germanium nanowire as a channel of FinFET type transistors. Claim 1 reads:

1. A Germanium nanowire of comprising:

a Germanium core; and

a Silicon Oxide shell disposed around said Gemanium core;

wherein the Germanium nanowire comprises a diameter of 30-45 nm.

US Patent 7821061 - Ge/SiGe multigate nanowire transistor

http://www.freepatentsonline.com/7821061.html

In the early days of transistors germanium was considered as a leading semiconductor material since it has a superior high electron mobility which allows for fast switching. Silicon eventually became dominant due to better thermal stability and the ease of oxide growth on Si surfaces but as device miniaturization continues the relative benefits of Ge are being reconsidered. This patent from Intel proposes a transistor design based on both Si and Ge materials forming a nanowire channel. Claim 1 reads:  

1. A microelectronic structure comprising:

a substrate including a lower Si substrate and an insulating layer on the substrate;

a projection on the substrate projecting above the insulating layer and including a center region comprising a floating nanowire channel comprising Ge/Si1-yGey and a covering region enclosing the center region, wherein the covering region comprises an insulation covering surrounding the nanowire channel and electrically insulating the nanowire channel and

wherein both the center region and an interface between the center region and the covering region has substantially no dislocation defects.

US Patent 7799849 - Self-healing nanomaterial

http://ip.com/patent/US7799849

This patent from Intel is related to semiconductor packaging and teaches a material to heal cracks in the packaging using an encapsulated nanoparticle composite. Claim 1 reads:

1. A method to fabricate a self-healing material comprising:

mixing nanoscale material with a healing agent to form a healing mixture;

encapsulating the healing mixture to form a plurality of self-healing capsules; and

dispersing the self-healing capsules in a polymer to fabricate the self-healing material.

US Patent 7784178 - CNT-LCP material for semiconductor fab container

http://ip.com/patent/US7784178

Semiconductor fabrication wafer containers are purged with inert gases such as nitrogen to reduce moisture, oxygen, or other contaminants. However, the barrier materials typically used in such containers make repeated purging necessary. This patent from Intel teaches using a liquid crystal polymer with carbon nanomaterial as the barrier material to reduce the frequency of purging. Claim 1 reads:

1. An apparatus, comprising:

an enclosure to contain one or more environmentally sensitive devices associated with semiconductor manufacture,

the enclosure comprising a liquid crystal polymer (LCP) to provide a barrier against at least water and oxygen and providing purging requirements of purging of between about 30 to 50 hours to maintain a relative humidity in the enclosure of less than about 10%,

the liquid crystal polymer (LCP) comprising a carbon nanotube material, a carbon multi-wall nanotube (MWNT), or carbon powder in the LCP; and

a door coupled with the enclosure.